Combinational Logic circuits

In Digital Electronics there are a few basic arithmetic circuits like Binary
adder and Binary subtractor. These circuits can be operated with binary
values 0 and 1.

Binary Adder
The most basic arithmetic operation is addition. The circuit, which
performs the addition of two binary numbers is known as Binary adder.

a) Half Adder
Half adder is a combinational logic circuit with two inputs and two
outputs. The half adder circuit is designed to add two single bit
binary numbers A and B. It is the basic building block for addition of
two single bit numbers. This circuit has two outputs carry and sum.

Block diagram

Truth Table

Circuit Diagram
 b) Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit.
It can add two one-bit numbers A and B, and carry C from the addition of
previous lower bits. The full adder is a three input and two output
combinational circuit.

Block diagram

Truth Table

K-map for Carry K-map for Sum

Circuit Diagram

N-Bit Parallel Adder

The Full Adder is capable of adding only two single digit binary number
along with a carry input. But in practical we need to add binary numbers
which are much longer than just one bit. To add two n-bit binary numbers
we need to use the n-bit parallel adder. It uses a number of full adders in
cascade. The carry output of the previous full adder is connected to carry
input of the next full adder.

Example: 4 Bit Parallel Adder

In the block diagram, A0 and B0 represent the LSB of the four bit numbers
A and B. Hence Full Adder-0 is the lowest stage. Hence its Cin has been
permanently made 0. The rest of the connections are as shown in the
following fig. The four bit parallel adder is a very common logic circuit.

Block diagram
Half Subtractors
It is a combination circuit with two inputs and two outputs
(difference and borrow). It produces the difference between the
two input binary bits and also produces an output (Borrow) to
indicate if a 1 has been borrowed.
Truth Table

Circuit Diagram

Full Subtractors
The full subtractor is a combinational circuit with three inputs
A,B,C and two output D and C'. A is the 'minuend', B is
'subtrahend', C is the 'borrow' produced by the previous stage,
D is the difference output and C' is the borrow output.
Truth Table

From the truth table: Difference D=A B C

̅𝑩 + 𝑨
Borrow = 𝑨 ̅ 𝑪 + 𝑪𝑩

C is the borrow by previous lower bit =Bin

Circuit Diagram
Multiplexers
Multiplexer is a special type of combinational circuit. There are
n-data inputs, one output and m select inputs where 2m = n. It is
a digital circuit which selects one of the n data inputs and routes
it to the output. The selection of one of the n inputs is done by
the select inputs. Depending on the digital code applied at the
select inputs, one out of n data inputs is selected and
transmitted to the single output Y. E is called the strobe or
enable input which is useful for the cascading.
Block diagram

We can have 2:1 multiplexer, 4:1 multiplexer,16:1 multiplexer,32:1

multiplexer etc.
Block Diagrams

Four-to-One Multiplexer
In 4:1 MUX, there will be 4 input lines and 1 output line. And to
control which input should be selected out of these 4, we need 2
select lines.

In the following diagram D0, D1, D2 and D3 are the input lines
and A, B are the two select input lines. The combination of binary
numbers given to the select input lines will determine the output
of the MUX.
Example: Implement the boolean expression
F(A, B, C) = ∑ m(2,3,6,7) using a multiplexer.

Solution:
The inputs, corresponding to the minterms (2,3,6,7) are
connected to the logic 1 and remaining terms to the logic
0(grounded).
Example: Implement the boolean expression
F(A,B,C,D)=∑m(0,1,3,4,8,9,15) using
(a) 16:1 multiplexer.
(b) 8:1 multiplexer.

A B C Y
0 0 0 1
0 0 1 D
0 1 0 D’
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 D
Example: Implement the function by 8:1 MUX
F(A,B,C,D) = Ʃm(1, 3, 4, 11, 12, 13, 14, 15)

Truth Table for implementation of the expression by 8:1 Multiplexer

A B C Y
0 0 0 D
0 0 1 D
0 1 0 D’
0 1 1 0
1 0 0 0
1 0 1 D
1 1 0 1
1 1 1 1

De-Multiplexer
It is a combinational circuit that performs the reverse operation of
Multiplexer. It has single input, ‘m’ selection lines and maximum of
2m outputs. The input will be routed to one of these outputs based on the
values of selection lines.
1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 &
s0 and four outputs Y3, Y2, Y1 &Y0. The block diagram of 1x4
De-Multiplexer is shown in the following figure.

The single input ‘I’ will be routed to one of the four outputs, Y3 to Y0 based
on the values of selection lines s1 & s0. The Truth table of 1x4 De-
Multiplexer is shown below.
Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each
output as
 Y3=s1s0I
Y2=s1s0′I
Y1=s1′s0I
Y0=s1′s0′I
We can implement these Boolean functions using Inverters & 3-input
AND gates. The circuit diagram of 1x4 De-Multiplexer is shown in the
following figure.

Similarly, we can implement 1x8 De-Multiplexer and 1x16 De-Multiplexer

etc. by following the same procedure.

Decoder
A decoder is a multiple-input, multiple-output combinational
logic circuit.
For a different combination of n bit binary inputs, it produces a
2n coded output. The coded output is produced based on each
binary input.
It also has an enable input. When it is set to logic HIGH, the
coded output will be seen depending on the binary data input.
There are different type of decoders.
2 to 4 binary decoder

The 2 to 4 binary decoder has 2 binary inputs and 4 coded

outputs. The block diagram and circuit diagram is shown below.
A and B are the two inputs and the output produced is one of the
minterms the two inputs.

When Enable(EN) is set at logic 1, one of the outputs(Y 0, Y1, Y2,

Y3) will be HIGH for a given input. The remaining outputs will
be logic 0.
From the above truth table, when both the inputs A and B are 0,
Y0 will be at logic 1 and the remaining output pins are LOW or
logic 0.

Similarly, output pin Y1 will be at logic 1 for A = 0 and B = 1.

When the inputs A = 1 and B = 1, Y3 pin is at logic 1 and the
remaining pins are at logic 0.

In a similar way, 3 to 8 binary decoders, 4 to 16 binary decoders

can be constructed. When the number of input of a decoder
increases, the coded output also increases.
Encoder
An Encoder is a combinational circuit that performs the reverse
operation of Decoder. It will produce a binary code equivalent to
the decimal input, which is active High. Therefore, the encoder
encodes 2n input lines with ‘n’ bits.
Let, a 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two
outputs A1 & A0. The block diagram of 4 to 2 Encoder is
shown in the following figure.
At any time, only one of these 4 inputs can be ‘1’ in order to get
the respective binary code at the output.

4 to 2 Encoder
Description of the circuit
When no switch is pressed both the outputs A and B should be low. The
lower points of all the resistances are High or at logic 1 ( when no switch
is pressed). So both the inputs of both the NAND gates are 1. So outputs
A and B both are Low or 0.
When switch 1 is pressed output B should go high, so a connection is
made from lower point of resistance 1 ( this point is at logic 0 when switch
1 is pressed) to the input of lower NAND gate.
When switch 2 is pressed output A should go high, so a connection is
made from lower point of resistance 2 ( this point is at logic 0 when switch
2 is pressed) to the input of upper NAND gate.
When switch 3 is pressed both the outputs A and B should go high, so a
connection is made from lower point of resistance 3 ( this point is at logic
0 when switch 1 is pressed) to the input of both the NAND gates.

Comparator Circuit
A digital Comparator is a combinational circuit that compares two
binary numbers in order to find out whether one binary number
is equal, less than or greater than the other binary number. It has
two inputs A & B and three output terminals, one for A > B
condition, one for A = B condition and one for A < B condition.
1-Bit Comparator –
A comparator used to compare two bits is called a single bit
comparator. It consists of two inputs each for two single bit
numbers and three outputs to generate less than, equal to and
greater than between two binary numbers.

The truth table for a 1-bit comparator is given below:

From the above truth table logical expressions for each output
can be expressed as follows:
A>B: AB'
A<B: A'B
A=B: A'B' + AB
Looking at the truth table, A=B is (A>B NOR A<B)
By using these Boolean expressions, we can implement a logic
circuit for this comparator as given below:
2-Bit Comparator –

A comparator used to compare two binary numbers each of two

bits is called a 2-bit comparator. It consists of four inputs and
three outputs to generate less than, equal to and greater than
between two binary numbers.
The truth table for a 2-bit comparator is given below:
From the above truth table K-map for each output can be drawn as follows:
From the above K-maps logical expressions for each output can
be expressed as follows:

A>B:A1B1’ + A0B1’B0’ + A1A0B0’

A<B:A1’B1 + A0’B1B0 + A1’A0’B0
̅̅̅̅̅̅̅̅̅̅
Looking at the truth table, A=B is ( 𝐴 ̅̅̅̅̅̅̅̅̅̅
1 + 𝐵1 .𝐴0 + 𝐵0 )

By using these Boolean expressions, we can implement a logic

circuit for this comparator as given below:
Another Implementation :

Parity Generator and Parity Checker

What is a Parity Bit?
A parity bit is an extra bit in any binary message to make the total
number of 1’s either odd or even. We need to add the parity
bit to a signal. This is done by the Parity generator. This parity
inclusive binary message then transmits from transmitter to
receiver end.
The Parity Checker matches the number of 1’s at the receiver’s
end with that of the transmitter’s end to check for errors. If there
is a change in the number of 1s at the receiving end, then that
detects the presence of an error.
What is even parity and odd parity?
Even parity is the case when the total number of 1s in the data
even whereas in odd parity, it is odd.
How does a Parity Generator work?
The parity generators can create two parities. Even parity
generates a final message with an even number of 1s. So the
parity bit for an even number of 1s is 0. On the other hand, an
odd parity bit generates when the total number of 1s in the
bitstream is odd.
Even parity Generator
3 bit Even Parity Generator:

Suppose at the transmitting end, and we have a 3-bit message

signal that we wish to transmit using an even parity bit. Let A, B,
and C be input bits and P be output that is even parity bit. Even
parity generates as a result of the calculation of the number of
ones in the message bit. If the number of 1s is even P gets the
value as 0, and if it is odd, then the parity bit P gets the value 1.
Following is the truth table for 3-bit even parity generator.
3-bit even parity generator truth table
3 Bit Message Parity bit

A B C P

0 0 0 0
0 0 1 1
0 1 0 1

0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Solving the truth table for all the cases where P is 1 using Sum-
of-Products method:
This expression can be implemented using two Ex-OR gates.
3-bit even parity generator circuit

4 bit Even Parity Generator

P=A⊕B⊕C⊕D
4-bit even parity generator circuit

Odd Parity Generator

3-bit Odd Parity Generator

Suppose at the transmitting end now we have a 3-bit message

signal, and we wish to transmit it using odd parity. Then, the
parity bit generated, P, would be as a result of odd parity
generation. The total number of 1s in the input bits must be odd
for the odd parity bit. If the total number of 1s in input bits is
odd, then P gets the value 0, and if it is even then, P is assigned
the value 1.
3-bit Odd Parity Generator truth table
3 Bit Message Parity Bit
A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Solving the truth table for all the cases where P is 1 using Sum-
of-Products method:
P = A ⊕ B Ex-NOR C = Not of A ⊕ B ⊕ C

3-bit Odd Parity Generator circuit

4 bit odd parity Generator

P = NOT (A ⊕ B ⊕ C ⊕ D)

Parity Checker
A parity checker is a logical circuit that checks data transmission
errors.
XOR gates are used as parity checkers.
Binary Adder / Subtractor
The circuit, which can be used to perform either addition or
subtraction of two binary numbers at any time is known
as Binary Adder / subtractor. Both, Binary adder and
Binary subtractor contain a set of Full adders, which are
cascaded.

4-bit Binary Adder / Subtractor

The 4-bit binary adder / subtractor produces either the addition

or the subtraction of two 4-bit numbers based on the value of
initial carry, 𝐶0. Let the 4-bit binary
numbers, A=A3A2A1A0 and B=B3B2B1B0. The operation of 4-
bit Binary adder / subtractor is similar to that of 4-bit Binary
adder and 4-bit Binary subtractor.
Apply the normal bits of binary numbers A and B & initial carry,
C0 to a 4-bit binary adder. The block diagram of 4-bit binary
adder / subtractor is shown in the following figure.

If initial carry, 𝐶0 is zero, then each full adder gets the normal
bits of binary numbers A & B. So, the 4-bit binary adder /
subtractor produces an output, which is the addition of two
binary numbers A & B.
If initial carry, 𝐶0 is one, then each full adder gets the normal
bits of binary number A & 2’s complement of binary number B.
So, the 4-bit binary adder / subtractor produces an output,
which is the subtraction of two binary numbers A & B.
Therefore, with the help of additional Ex-OR gates, the same
circuit can be used for both addition and subtraction of two
multibit binary numbers.

7 segment Decoder
Most often seven-segment displays are used to display the digits
in digital watches, calculators, clocks, measuring instruments
and digital counters, etc. Generally, LCD and LED segments
provide the display output of numerical numbers and characters.

A display decoder is used to convert a BCD or a binary code into

a 7 segment code. It has 4 input lines and 7 output lines. Here we
design a simple display decoder circuit using logic gates.

A decoder is a combinational circuit which is used to convert a

binary or BCD (Binary Coded Decimal) number to the
corresponding decimal number . It can be a simple binary to
decimal decoder or a BCD to 7 segment decoder.

7 Segment Display Decoder Circuit Design

Step 1: A truth table is constructed with the combination of
inputs for each decimal number. For example, decimal number
1 would command a combination of b and c (refer the diagram
given below).
 7 Segment LED

Step 2: The second step involves constructing the truth table

listing the 7 display input signals, decimal number and
corresponding 4 digit binary numbers.

The figure below shows the truth table of a BCD to seven-

segment decoder. In the truth table , there are 7 different output
columns corresponding to each of the 7 segments.

Suppose the column for segment a shows the different

combinations for which it is to be illuminated. So ‘a’ is active for
the digits 0, 2, 3, 5, 6, 7, 8 and 9.

Decimal Digit
Inputs Outputs
Displayed

A B C D a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 0 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 0 0 1 1

Tableno.1 Truth Table of BCD-to-7 Segment Decoder

(i) K-map and Logic Diagram for Digital Output 'a':

For the Fig.(d) the simplified expressions is given by a = B‾

D‾ + BD + CD + A and the logic diagram is demonstrated in
Fig.(e) by using only NANDs.
 Fig.(e) Logic Diagram for Output 'a'

(ii) K-map and Logic Diagram for Digital Output 'b':

For the Fig.(f) the simplified expressions is specified by b = B‾ + C‾D‾ + CD and the logic
diagram is demonstrated in Fig.(g) by using only NANDs.

Fig.(g) Logic Diagram for Output 'b'

(iii) K-map and Logic Diagram for Digital Output 'c':

For the Fig.(h) the simplified expressions is specified by c = B + C‾ + D and the logic
diagram is demonstrated in Fig.(i)

Fig.(i) Logic Diagram for Output ' c '

(iv) K-map and Logic Diagram for Digital Output'd':

The simplified expressions for the Fig.(j) is given by

d = B‾D‾ + CD‾ + B‾C +BC‾D and the logic diagram is demonstrated in Fig.(k) by using
only NANDs.
 Fig.(k) Logic Diagram for Output ' d '

(v) K-map and Logic Diagram for Digital Output 'e':

For the Fig.(l) the simplified expressions is specified by e = B‾D‾ + CD‾ and the logic
diagram is demonstrated in Fig.(m) by using only NANDs.

Fig.(m) Logic Diagram for Output 'e'

(vi) K-map and Logic Diagram for Digital Output 'f':

For the Fig.(n) the simplified expressions is specified by f = A + C‾ D‾ + BC‾ +BD‾ and
the logic diagram is demonstrated in Fig.(o) by using only NANDs.
 Fig.(o) Logic Diagram for Output ' f'

(vii) K-map and Logic Diagram for Digital Output 'g':

For the Fig.(p) the simplified expressions is specified by g = A + BC‾ + B‾C+ CD‾ and the
logic diagram is demonstrated in fig.(q) by using only NANDs.

Fig.(q) Logic Diagram for Output ' g '

The complete circuit for all the inputs to the segments
a,b,c,d,e,f,g is represented in the above figure.

************************************