UNIT 3
COMBINATIONA
L CIRCUITS
Combinational Circuits
Some of the characteristics of combinational circuits are following:
• The output of combinational circuit at any instant of time,
depends
only on the levels present at input terminals.
• The combinational circuit do not use any memory. The previous state
of input does not have any effect on the present state of the circuit.
• A combinational circuit can have an 'n' number of inputs and 'm‘
number of outputs.
• Examples: Adders, subtractors, multiplier, decoder, encoder, Priority
encoder, multiplexers, demultiplexers, comprators, code
converter….etc.
ANALYSIS
PROCEDURE
ANALYSIS PROCEDURE
ANALYSIS PROCEDURE
DESIGN
PROCEDURE
Design Procedure
1. The problem is stated
2. The number of available input variables and required output
variables is determined.
3. The input and output variables are assigned lettersymbols.
4. The truth table that defines the required relationship betweeninputs
and outputs is derived.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.
Adder
Binary Adder: Half Adder(HA)
A Half Adder is a combinational circuit that accepts two binary digits on its inputs
A and B.
It produce two binary digits outputs, a sum bit (S) and a carry bit (C).
The simplest half-adder design, pictured incorporates an XOR gate for S and an
AND gate for C.
Sum <= A XOR B; Sum (S)=A’B+AB’
Carry <= A AND B; Carry (C) =AB
Binary Adder: Half Adder(HA)
Sum <= A XOR B; Sum (S)= A’B+AB’
Carry <= A AND B; Carry (C) =AB
A half-adder can be realized by using
one X-OR gate and one AND gate
Logic diagrams of half-adder
Half Adder using only NAND gates
Half Adder using only NOR gates
Binary Adder: Full Adder(FA)
. A full adder is a combinational circuit that performs the arithmetic sum of three
bits
. The full adder has three inputs and two outputs.
. The full-adder adds the bits A and B and the carry from the previous column called
the carry-in Cin and outputs the sum bit S and the carry bit called the carry-out Cout
Full Adder using Half adder & OR gate
Full Adder using AOI logic
Sum = S = A’B’Cin + A’BCin’ +AB’Cin’ +ABCin = A XOR B XOR C
Carry = Cout = AB + ACin + Bcin
Full Adder using only NAND gates
BINARY SUBTRACTORS
Half Subtractor
A Half-subtractor is a combinational circuit with two inputs A and B
and two outputs difference(d) and barrow(b).
Fig :Block diagram
Fig : Truth table
d=A′B+AB′=A B
b=A′B
Half Subtractor using only
NAND gates
Half Subtractor using only
NOR gates
BINARY
Full subtractor SUBTRACTORS
The full subtractor perform subtraction of three input bits: the
minuend , subtrahend , and borrow in and generates two output
bits difference and borrow out .
Full Subtractor
Full Subtractor using only
NAND gates
BINARY MULTIPLIER
A binary multiplier is an electronic circuit used in digital electronics,
such as a computer, to multiply two binary numbers. It is built using
binary adders.
Example: (101 x 011)
Partial products are: 101 × 1, 101 × 1, and 101 ×0
1 0 1
× 1 1
0
1 0 1
1 0 1
0 0 0
0 0 1 1 1 1
BINARY MULTIPLIER
• We can also make an n × m “block” multiplier and use that to
form partial products.
• Example: 2 × 2 – The logic equations for each partial-product
binary digit are shown below
• We need to "add" the columns to get the product bits P0, P1,
P2, and P3.
BINARY MULTIPLIER
A0
B1 B0
A1
B1 B0
HA HA
P3 P2 P1 P0
Fig 1: 2 x 2 multiplier
array
DECODER
• A binary decoder is a combinational logic circuit that converts
binary information from the n coded inputs to a maximum of 2n
unique outputs.
• We have following types of decoders 2x4,3x8,4x16….
2x4 decoder
Fig 1: Block diagram Fig 2:Truth table
3.5 Combinational Circuits
• This is what a 2-to-4 decoder looks like on the
inside.
If x = 0 and y = 1,
which output line
is enabled?
3 to 8(3x8) line decoder
Minterms using OR Gates
Minterms using NOR Gates
4x16 decoder using 3x8 decoders
Higher order decoder implementation using lower
order.
Decoders with an Enable Input
Constructing Larger Decoders
ENCODER
S
• An Encoder is a combinational circuit that performs the reverse
operation of Decoder. It has maximum of 2n input lines and ‘n’
output lines.
• It will produce a binary code equivalent to the input, which is
active
High.
Fig 1 :Block diagram of 4x2 encoder
Octal to Binary Encoder
(8 to 3 Encoder)
•
MULTIPLEXERS
• Multiplexer is a combinational circuit that has maximum of 2n data
inputs, ‘n’ selection lines and single output line. One of these data
inputs will be connected to the output based on the values of
selection lines.
• We have different types of multiplexers 2x1,4x1,8x1,16x1,32x1……
Y = S1 ‘ S0 ‘ I0 + S1 ‘ S0 I1 + S1 S0 ‘ I2 + S1S0I3
Fig 1: Block diagram Truth table
This is what a 4-to-1 multiplexer looks like on the inside.
If S0 = 1 and S1 = 0,
which input is
transferred to the
output?
MULTIPLEXERS
• Ex: 8x1
Multiplexer
Fig 2: 8x1 Multiplexerdiagram
Implementation of
Full Adder using MUX
DEMULTIPLEXER
• A demultiplexer is a device that takes a single input line and routes
it to one of several digital output lines.
• A demultiplexer of 2n outputs has n select lines, which are used to
select which output line to send the input.
• We have 1x2,1x4,8x1…. Demultiplexers.
Fig:1 Block diagram Truth table
DEMULTIPLEXER
Boolean functions for each output
as
Fig 2: Logic diagram
1:8 DeMux using two 1:4 Demux
Implementaion of Boolean function using Demux
F1(A,B,C) = ∑m (0,3,7) F2(A,B,C) = ∑m (1,2,5)
CODE CONVERTERS
A code converter is a logic circuit whose inputs are bit patterns
representing numbers (or character) in one code and whose
outputs are the corresponding representation in a different code.
Design of a 4-bit binary to gray code converter
Truth table
CODE CONVERTERS
K-map simplification
CODE CONVERTERS
Fig 1: Logic diagram
MAGNITUDE COMPARATOR
Magnitude comparator takes two numbers as input in binary form
and determines whether one number is greater than, less than or
equal to the other number.
1-Bit Magnitude Comparator
A comparator used to compare two bits is called a single bit
comparator.
Fig :1 Block
diagram
MAGNITUDE COMPARATOR
Fig 2: Logic diagram of 1-bit comparator
MAGNITUDE
COMPARATOR
• 2 Bit magnitude comparator
Fig :3 Block diagram
Fig :4 Truth
table
MAGNITUDE COMPARATOR
MAGNITUDE COMPARATOR
Fig 5:Logic diagram of 2-bit comparator
fig 5: Logic diagram for 2 – bit comparator
PROGRAMMABLE LOGIC ARRAY (PLA)
Programmable Logic Array
• A programmable logic array (PLA) is a type of logic device
that can be programmed to implement various kinds of
combinational logic circuits.
• The device has a number of AND and OR gates which are
linked together to give output or further combined with more
gates or logic circuits.
PROGRAMMABLE LOGIC ARRAY
Programmable LogicArray
Fig 1: Block diagram of
PLA
PROGRAMMABLE LOGIC ARRAY
PLA
F1 =AB’+AC+A’BC’
F2 = (AC+BC)’
Fig 2: PLA with 3-inputs 4 product terms and 2
outputs
PROGRAMMABLE LOGIC ARRAY
Programmable Logic Array
• Advantages
• PLA architecture is more efficient than a PROM.
• Disadvantage
• PLA architecture has two sets of programmable fuses due to which PLA
devices are difficult to manufacture, program and test.
• Applications:
• PLA is used to provide control over data path.
• PLA is used as a counter.
• PLA is used as decoders.
• PLA is used as a BUS interface in programmed I/O
PROGRAMMABLE LOGIC ARRAY
Programming
Table
First: lists the product terms numerically
Second: specifies the required paths inputs and
between AND gates
Third: specifies the paths between the AND and OR
gates
For each output variable, we may have a T(ture) or
C(complement) for programming the XOR gate
PROGRAMMABLE LOGIC ARRAY
Example
Implement the following two Boolean functions with a PLA:
F1(A, B,C) = ∑m (0, 1, 2, 4)
F2(A, B, C) = ∑m (0, 5, 6, 7)
The two functions are simplified in
the maps of given figure
PROGRAMMABLE LOGIC ARRAY
PLA table by simplifying the function
Both the true and
complement of the functions
are simplified in sum of
products.
We can find the same terms
from the group terms of the
functions of F1, F1’,F2 and F2’
which will make the minimum
terms.
F1 = (AB +AC + BC)’
F2 = AB + AC + A’B’C’
PROGRAMMABLE LOGIC
PLA implementation
ARRAY
