COMBINATIONAL CIRCUITS

Introduction

Combinational circuit consists of input variables, logic gates and output variables. The inputs and outputs are two
valued, i.e., 0 or 1.

The values of the output variables depend only on the present values of the input variables. The output does not
depend on the previous history of the inputs. In fact, an ideal combinational circuit acts instantly depending on the
input at that instant.

Circuits like adder, subtractor, multiplexers, demultiplexers, decoders, encoders are all examples of combinational
circuits
 HALF ADDER
The half adder operation needs two binary inputs: augend and addend bits and two binary outputs: Sum and Carry
Limitations:
In multidigit addition, we have to add two bits along with the carry of previous digit addition.
Effectively, such addition of three bits is not possible with half adder.
Hence half adder is not used in practice.
Example: Draw half adder using NAND gates
 FULL ADDER
There is a provision of generation and addition of carry bit in full adder while in half adder two inputs are added
but there is no provision to add a carry to the next higher significant bit which is obtained from the previous stage.

A full adder consists of three inputs and two outputs. The three input terminals used for A (Augend bit), B(Added
bit) and Cin represents the carry from the previous lower significant stage. The two output terminals produce a
sum and a carry.
Example: Full adder using two half adder
 HALF SUBTRACTOR
A half subtractor is combinational circuit which subtracts two bits and produces their difference D and borrow out
(Bout).

From the truth table, it is clear that

• A (minuend) and B (subtrahend) are two inputs

• The difference output is 0 if A = B.
• when A < B then the difference output is 1 with Bout as 1, then subtraction is done by borrowing 1 from the
next higher order bit.
• A > B then the difference output is 1
Limitations:
In multidigit subtraction, we have to subtract two bits along with the borrow of the previous digit subtraction.
Effectively, such subtraction requires subtraction of three bits, which is not possible with half adder.
Example: Draw half subtractor using NAND gates
 FULL SUBTRACTOR
To perform the subtraction of two multibit numbers where there may be a borrow from the previous bit position.

A full adder consists of three inputs and two outputs. The three input terminals used for A (minuend), B
(subtrahend) and Bin (previous borrow). The two output terminals are D (difference), Bout (output borrow) .
Further simplification
Full subtractor circuit
Borrow output

Example: Full subtractor using two half subtractor

 MULTIPLEXER or digital switch/ data selector
The term multiplex means "many into one". It means transmitting large information or inputs to single output. The
device which is used to convert many inputs into a single output is called a multiplexer.

A digital multiplexer (MUX) selects digital information from various input lines and transmits the selected
information to a single output. The selection of particular input line is controlled by a set of selection lines.

Generally, there are 2𝑛 input lines and n selection lines whose bit combination decides which input is to be
selected. The block diagram of a multiplexer with m (= 2𝑛 ) input lines, n selection lines and one output is shown:
Four to one multiplexer

The four inputs 𝐼𝑜 to 𝐼3 , a single output Y, and two selection lines 𝑆𝑜 and 𝑆1 are used to select one output of four
input lines. The logical expression for output Y in terms of input lines (𝐼𝑜 to 𝐼3 ) and the selection inputs (𝑆𝑜 and
𝑆1 ) can be obtained as follows:

𝑆1 = 0 and 𝑆0 =0 then data output 𝑌 = 𝐼0 Therefore, 𝑌 = 𝐼0 𝑆ഥ1 𝑆0 = 𝐼0 0ത . 0ത = 𝐼0 1.1 = 𝐼0

𝑆1 = 0 and 𝑆0 =1 then data output 𝑌 = 𝐼1 Therefore, 𝑌 = 𝐼1 𝑆ഥ1 𝑆0 = 𝐼0 0.
ത 1 = 𝐼0 1.1 = 𝐼1
𝑆1 = 0 and 𝑆0 =0 then data output 𝑌 = 𝐼2 Therefore, 𝑌 = 𝐼2 𝑆1 𝑆0 = 𝐼0 1.0ഥ = 𝐼0 1.1 = 𝐼2
𝑆1 = 0 and 𝑆0 =0 then data output 𝑌 = 𝐼3 Therefore,𝑌 = 𝐼2 𝑆1 𝑆0 = 𝐼0 1.1 = 𝐼0 1.1 = 𝐼3

𝑌 = 𝐼0 𝑆ഥ1 𝑆0 +𝐼1 𝑆ഥ1 𝑆0 +𝐼2 𝑆1 𝑆0 +𝐼3 𝑆1 𝑆0

Operation:
The operation of the circuit can be understood as follows. If we consider the case when 𝑆1 𝑆0 = 00 , it
means 𝑆1 𝑆0 = 00 is applied to the select lines, then AND gate associated with 𝐼0 𝑆ഥ1 𝑆0 will have two inputs
equal to 1 and third input will be 𝐼0 .

For other three AND gates, the output will be equal to 0 because at least one input will have zero value in
all the three AND gates. Hence the OR output is equal to the value of 𝐼0 .
Eight to one multiplexer

An eight to one multiplexer is same as four to one multiplexer. It has eight inputs, three selection lines and one
output.:
𝑌 = 𝐼0 𝑆2 𝑆ഥ1 𝑆0 +𝐼1 𝑆2 𝑆ഥ1 𝑆0 +𝐼2 𝑆2 𝑆1 𝑆0 +𝐼3 𝑆2 𝑆1 𝑆0 +𝐼4 𝑆2 𝑆ഥ1 𝑆0 +𝐼5 𝑆2 𝑆ഥ1 𝑆0 +𝐼6 𝑆2 𝑆1 𝑆0 +𝐼7 𝑆2 𝑆1 𝑆0
Multiplexer with an Enable input

Normally multiplexers have one additional input line that is referred to as enable input which controls the whole
multiplexer circuit operation and provides greater flexibility.

This enable input is also called strobe. Enable line may be active low or active high.

Active low means 𝐸 = 0 and active high means 𝐸 = 1. The four to one multiplexer is shown in fig. with enable
input 𝐸 = 1, i.e., active high. Therefore, output Y can be obtained only when E = 1.
Multiplexer with an Enable input

When 𝐸 = 0 then multiplexer is disabled but if 𝐸 = 1, then the multiplexer works normally. The logic expression
for a four to one multiplexer with an enable input can be immediately written as,

𝑌 = (𝐼0 𝑆ഥ1 𝑆0 +𝐼1 𝑆ഥ1 𝑆0 +𝐼2 𝑆1 𝑆0 +𝐼3 𝑆1 𝑆0 )𝐸

Higher order multiplexer
Generally, 2 to 1 line, 4 to 1 line, 8 to 1 line and 16 to 1 line multiplexers are commercially available.

By interconnecting several multiplexer in a treelink structure, it is possible to produce a large line multiplexer.

Figure demonstrates how four 4-1 line multiplexers are used to construct a 16-1 line multiplexer. Similarly, a 32 to 1
multiplexer can be constructed by using two 16-1 multiplexers or four 8-1 multiplexers or by using eight 4-1 multiplexers.
 DEMULTIPLEXER
Demultiplex means 'one into many'. It performs the opposite of multiplexer. It accepts one input and transmits it
over many output lines.

The selection lines decide to which output, the data input will be transmitted. If it has 𝑚 output lines and 𝑛 select
lines, then the relationship between 𝑚 and 𝑛 is as follows

𝟐𝒏 = 𝒎

The block diagram of 1: 𝑚 demux is shown. It has one input line, 𝑛 select lines and 𝑚 output lines. It converts the
serial data into parallel data, so demultiplexer is also called a data distributor or serial to parallel converter
𝟏: 𝟒 Demuliplexer

It has one input line 𝐷 and two select lines 𝑆 and 𝑆𝑜 . So, the output lines will be (2𝑛 = 22 = 4) four, i.e., 𝑌𝑜 , 𝑌1 , 𝑌2 , and 𝑌3 .
The truth table of 1: 4 Demux is as follows:
Operation:

If we consider the case when the select line inputs 𝑆1 𝑆0 = 00 is applied, then the data information in
transferred to 𝑌𝑜 output line. If input D is applied, the output at 𝑌𝑜 line will be D and other outputs will be 0.

Similarly, when the other combinations are applied to select lines, the corresponding output line will select
and data is transferred to the selected output line.

𝑌0 = 𝑆ഥ1 𝑆0 𝐷, 𝑌1 = 𝑆ഥ1 𝑆0 𝐷, 𝑌2 = 𝑆1 𝑆0 𝐷, 𝑌3 = 𝑆1 𝑆0 𝐷
𝟏: 𝟖 Demuliplexer

It has one input data line 𝐷 and three select lines (𝑛 = 3) . So, the output lines will be (2𝑛 = 23 = 8) four, i.e., 𝑌𝑜 , 𝑌1 , 𝑌2 ,
𝑌3 , 𝑌4 , 𝑌5 , 𝑌6 and 𝑌7 . The truth table of 1: 8 Demux is as follows:
 DECODER
Sometimes digital information represented in binary form must be converted into some other form. This is obtained
by multiple inputs-multiple outputs logic circuit known as decoder.

The most commonly used decoder is 𝑛 to 2𝑛 line decoder. The block diagram of (𝑛: 𝑚) decoder is shown. It has 𝑛
input lines and 𝑚 (= 2𝑛 ) output lines.

In a decoder, 𝑚 output lines are greater than 𝑛 input lines. But when input lines are equal to output lines then it is
known as a converter. It converts one form of n bit binary information into another form of m bit binary information.
For example, BCD to excess-3 code converter, binary to gray code converter etc.

In other case when m output lines are less than 2" then this type of decoder is known as function specific decoder.
For example, BCD to decimal decoder, BCD to seven segment decoder etc.

The main applications of decoder are data demultiplexing, digital display, digital to analog converters and memory
addressing.
𝟑 𝒕𝒐 𝟖 Decoder

It has three input lines, i.e., 𝑛 = 3(𝐴, 𝐵, 𝐶) and input lines and 𝑚 = 23 = 8 output lines, i.e., 𝑌𝑜 , 𝑌1 , 𝑌2 , 𝑌3 … … 𝑌7 .
Each expression on output line corresponds to a single minterm.

For example, when input ABC = 000 is applied, the output line 𝑌𝑜 will get enabled. It means the output line 𝑌𝑜 will give
logic 1 and output of other lines will be zero. So minterm ABC, i.e., ABC=000 is obtained at output line 𝑌𝑜 . The truth table
of 3-to-8-line decoder:

The Boolean expression of each output line is as follows:

𝑌0 = 𝐴ҧ𝐵ത 𝐶,ҧ 𝑌1 = 𝐴ҧ𝐵𝐶, ҧ 𝐶,ҧ 𝑌3 = 𝐴𝐵𝐶,
ത 𝑌2 = 𝐴𝐵 ҧ 𝑌4 = 𝐴𝐵ത 𝐶,ҧ 𝑌5 = 𝐴𝐵𝐶,
ത 𝑌6 = 𝐴𝐵 𝐶,ҧ 𝑌7 = 𝐴𝐵𝐶
Therefore, each output line of the decoder represents the
particular minterm of corresponding inputs applied to the
selected lines.

Hence, the 𝑛 𝑡𝑜 2𝑛 line decoder can be called as

minterm generator.

Any Boolean function can be implemented with decoder

and logic gates.
Decoder with an enable input

Generally, decoders have one or more additional input lines, which control the operation of the decoder, called enable
input E. The block diagram of 2: 4 line decoder with enable input is shown in fig. 4.37

If enable input is zero i.e. E = 0 then the decoder will be disabled. Then all the outputs of decoder will be zero. The output
will not depend on the inputs A and B.

When E = 1 is applied then decoder will get enabled and the output line will give output 1 by applying corresponding
input combination to the input lines A and B
BCD to Seven Segment Decoder
The seven segment display is used to display the decimal digits from 0 to 9.

The BCD to seven segment decoder accepts BCD inputs and displays the corresponding decimal digit.

The block diagram of BCD to 7 segment decoder is shown in fig. (a)

The seven segment display is composed of seven elements or segment. Each segment is a small light emitting diode (LED),
which glows when electrical current passes through it.
As shown in fig. (b) the segments are labelled from a to g.

The letters a, b, c, d, e, f and g run clockwise from the top of

each segment,

Based on which, we can display the digits 0 through 9 as shown

in fig. (c).

For example, to display 7, we need to light up segments a, b and

c and to display 0, we need segments a, b, c, d, e and f.
 The decoder accepts the 4-bit BCD
Design of BCD to Seven Segment Decoder inputs A,B,C, D and the seven outputs
are set to display the appropriate BCD
digit.

For example, if the BCD input

ABCD=0111 is applied to the decoder,
the output will display decimal seven.

It means the segments a, b and c will

glow and other segments will be off.
The outputs a, b, c will be on logic 1
and other will be on logic 0. Similarly,
all other conditions can be verified
from the truth table.

Since the input is in BCD form, so the

4-bit inputs from 0000 to 1001 (0 to 9)
will be valid and other six
combinations (1010 to 1111) will be
invalid.

For invalid combinations, the output

will be considered as don't care (d)
condition. These are not shown in truth
table.
 ENCODER
Like decoder, encoder also provides the conversion of binary information from one førm to another. Encoder performs
the opposite function of a decoder.

Its gives information in more compact form. Encoder has more input lines than output lines or say output lines are less
than the input lines. It has m input lines and n output lines.

From m input lines, only one is activated at a time and gives an equivalent code on n output lines.

Encoder is a digital or combinational circuit that converts an active signal into a coded output signal. Encoders are used
to reduce the number of bits needed to represent the given information.

A practical use of encoders is for transmitting information in a digital system. Encoding is also useful the if the
information is to be stored for later use because fewer bits are required to be stored.
Octal to Binary Encoder

Encoder is the inverse of decoder. We also studied the 3: 8 decoder where it accept a 3-bit input code and activates one of
the eight output lines respective to that code.

An octal to binary encoder perform the opposite function.

It accepts one of the eight inputs and produces a 3-bit output code respective to the activated input.