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Combinational Circuit Design: Multiplexers

A multiplexer (Mux) is a combinational circuit that selects one of several data input lines to pass to its output based on a digital select input. A Mux has multiple data inputs, a select input line, and one output. It uses enable logic gates to pass the signal from the selected data input to the output. Multiplexers can be used to implement any logic function by expressing the function terms and using the select lines. Decoders are the inverse of multiplexers, with n inputs and 2^n outputs, where only one output is asserted based on the input code value.

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0% found this document useful (0 votes)
60 views9 pages

Combinational Circuit Design: Multiplexers

A multiplexer (Mux) is a combinational circuit that selects one of several data input lines to pass to its output based on a digital select input. A Mux has multiple data inputs, a select input line, and one output. It uses enable logic gates to pass the signal from the selected data input to the output. Multiplexers can be used to implement any logic function by expressing the function terms and using the select lines. Decoders are the inverse of multiplexers, with n inputs and 2^n outputs, where only one output is asserted based on the input code value.

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DAFUQ MEOW:3
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Combinational Circuit Design

Functional units – Multiplexers and Decoders

Multiplexers
 Selecting data is an essential function in digital systems

 Functional blocks that perform selecting are called multiplexers

 A Multiplexer (or Mux) is a combinational circuit that has:


d0
 Multiple data inputs (typically 2n) to select from d1
2n Inputs

d2
Mux

. Y
 An n-bit select input S used for control .
.
d2n–1
 One output Y n
S
 The n-bit select input directs one of the data inputs to the output

1
Examples of Multiplexers
 2-to-1 Multiplexer Inputs Output
d0 0
if (S == 0) Y = d0 ; S d 0 d1 Y

Mux
Y
else Y = d1; 0 0 X 0 = d0
d1 1
0 1 X 1 = d0
Logic expression: 1 X 0 0 = d1
S 1 X 1 1 = d1
𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆
 4-to-1 Multiplexer d0 0 Inputs Output
d1 1 S1 S0 d0 d1 d2 d 3 Y

Mux
if (S1S0 == 00) Y = d0 ; Y
d2 2 0 0 0 X X X 0 = d0
else if (S1S0 == 01) Y = d1; d3 3 0 0 1 X X X 1 = d0
else if (S1S0 == 10) Y = d2; 2
0 1 X 0 X X 0 = d1
0 1 X 1 X X 1 = d1
else Y = d3; S1 S0
1 0 X X 0 X 0 = d2
1 0 X X 1 X 1 = d2
Logic expression:
1 1 X X X 0 0 = d3
𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆2 1 1 X X X 1 1 = d3

Implementing Multiplexers
d0
d0 0
Mux

𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆 Y
d1
d1 1
Enabling
S AND Gates
S

d0
d0 0
d1
d1 1
Mux

𝑌= 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 Y


d2 2 d2
d3 3 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆0
d3
2
S1 S0 Enabling
S1 AND Gates
S0

2
Implementing a Function with a Multiplexer
 A Multiplexer can be used to implement any logic function
 The function must be expressed using its minterms
 Example: Implement F(a, b, c) = ∑(1, 2, 6, 7) using a Mux
 Solution:
Inputs Output
0 0
a b c F
1 1
The inputs are 0 0 0 0
1 2

8-to-1 Mux
used as select 0 0 1 1
0 3
lines to a Mux. 0 1 0 1 F
0 1 1 0 0 4
An 8-to-1 1 0 0 0 0 5
Mux is used 1 0 1 0 1 6

because there 1 1 0 1 1 7
1 1 1 1
are 3 variables
S2 S1 S0 = a b c

Better Solution with a Smaller Multiplexer


 Re-implement F(a, b, c) = ∑(1, 2, 6, 7) using a 4-to-1 Mux
 We will use the two select lines for variables a and b
 Variable c and its complement are used as inputs to the Mux

Inputs Output Comment


a b c F F
0 0 0 0
F=c c 0
0 0 1 1
4-to-1 Mux

0 1 0 1
F = c' c' 1
0 1 1 0 F
1 0 0 0 0 2
F=0
1 0 1 0
1 1 0 1 1 3
F=1
1 1 1 1
S1 S0 = a b

3
Implementing Functions: Example 2
Implement F(a, b, c, d) = ∑(1,3,4,11,12,13,14,15) using 8-to-1 Mux
Inputs Output Comment
a b c d F F
0 0 0 0 0 d 0
0 0 0 1 1
F=d
0 0 1 0 0 1
0 0 1 1 1
F=d
2

8-to-1 Mux
0 1 0 0 1
0 1 0 1 0
F = d'
0 3
0 1 1 0 0 F
0 1 1 1 0
F=0 4
1 0 0 0 0 5
1 0 0 1 0
F=0
1 0 1 0 0 1 6
1 0 1 1 1
F=d
1 1 0 0 1
7
1 1 0 1 1
F=1
1 1 1 0 1
F=1 S2 S1 S0 = a b c
1 1 1 1 1

Binary Decoders
 Given a n-bit binary code, there are 2n possible code values

 The decoder has an output for each possible code value

 The n-to-2n decoder has n inputs and 2n outputs

 Depending on the input code, only one output is set to logic 1

 The conversion of input to output is called decoding

A decoder can have less


2n Outputs
n Inputs

n to 2n
than 2n outputs if some




Decoder
input codes are unused

4
Examples of Binary Decoders
Inputs Outputs
0 d0 a1 a0 d0 d1 d2 d3

4 Outputs
2 Inputs

a1 21 2-to-4 1 d1 0 0 1 0 0 0 Truth
a0 20 Decoder 2 d2 0 1 0 1 0 0
d3 1 0 0 0 1 0 Tables
3
1 1 0 0 0 1

Inputs Outputs
0 d0
a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7
1 d1
0 0 0 1 0 0 0 0 0 0 0
2 d2
8 Outputs
a2 22 0 0 1 0 1 0 0 0 0 0 0
3 Inputs

3-to-8 3 d3 0 1 0 0 0 1 0 0 0 0 0
a1 21
Decoder 4 d4 0 1 1 0 0 0 1 0 0 0 0
a0 20
5 d5 1 0 0 0 0 0 0 1 0 0 0
6 d6 1 0 1 0 0 0 0 0 1 0 0
d7 1 1 0 0 0 0 0 0 0 1 0
7
1 1 1 0 0 0 0 0 0 0 1

Decoder Implementation
Inputs Outputs 𝑎2
a1 a0 d 0 d 1 d 2 d 3 3-to-8 Decoder
0 0 1 0 0 0
𝑎1
0 1 0 1 0 0 𝑎0 𝑑0 = 𝑎2′ 𝑎1′ 𝑎0′
1 0 0 0 1 0
1 1 0 0 0 1
𝑑1 = 𝑎2′ 𝑎1′ 𝑎0
2-to-4
Decoder 𝑑2 = 𝑎2′ 𝑎1 𝑎0′
𝑎1
𝑎0 𝑑0 = 𝑎1′ 𝑎0′ 𝑑3 = 𝑎2′ 𝑎1 𝑎0
𝑑1 = 𝑎1′ 𝑎0 𝑑4 = 𝑎2 𝑎1′ 𝑎0′
𝑑2 = 𝑎1 𝑎0′ 𝑑5 = 𝑎2 𝑎1′ 𝑎0
𝑑3 = 𝑎1 𝑎0 𝑑6 = 𝑎2 𝑎1 𝑎0′
𝑑7 = 𝑎2 𝑎1 𝑎0
Each decoder output is a minterm

5
Using Decoders to Implement Functions
 A decoder generates all the minterms
 A Boolean function can be expressed as a sum of minterms
 Any function can be implemented using a decoder + OR gate
Note: the function must not be minimized
 Example: Full Adder sum = ∑(1, 2, 4, 7), cout = ∑(3, 5, 6, 7)
Inputs Outputs
d0
a b c cout sum
d1
0 0 0 0 0 sum
d2
0 0 1 0 1 a 22
0 1 0 0 1 3-to-8 d3
b 21
0 1 1 1 0 Decoder d4
1 0 0 0 1 c 20 cout
d5
1 0 1 1 0 d6
1 1 0 1 0
1 1 1 1 1 d7

Using Decoders to Implement Functions


 Good if many output functions of the same input variables
 If number of minterms is large  Wider OR gate is needed
 Use NOR gate if number of maxterms is less than minterms
 Example: f = ∑(2, 5, 6), g = ∏(3, 6)  g' = ∑(3, 6), h = ∑(0, 5)
Inputs Outputs
a b c f g h d0
0 0 0 0 1 1 d1 f
0 0 1 0 1 0 d2
a 22
0 1 0 1 1 0 3-to-8 d3
b 21 g
0 1 1 0 0 0 Decoder d4
c 20
1 0 0 0 1 0 d5
1 0 1 1 1 1 d6 h
1 1 0 1 0 0 d7
1 1 1 0 1 0

6
2-to-4 Decoder with Enable Input
Truth Table
0 d0
Inputs Outputs a1 21
2-to-4 1 d1
a0 20
d2
EN a1 a0 d0 d1 d2 d3 Decoder 2
EN 3 d3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0 𝑎1
1 1 0 0 0 1 0
𝑎0 𝑑0 = 𝐸𝑁 𝑎1′ 𝑎0′
1 1 1 0 0 0 1
𝑑1 = 𝐸𝑁 𝑎1′ 𝑎0

If EN input is zero then 𝑑2 = 𝐸𝑁 𝑎1 𝑎0′


all outputs are zeros, 𝑑3 = 𝐸𝑁 𝑎1 𝑎0
regardless of a1 and a0 𝐸𝑁

Building Larger Decoders


 Larger decoders can be build using smaller ones
 A 3-to-8 decoder can be built using:
Two 2-to-4 decoders with Enable and an inverter (1-to-2 decoder)
Inputs Outputs a2
0 d0
a2 a1 a0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 a1 a1 Top
1 d1
0 0 0 1 0 0 0 0 0 0 0 a0 a0 2-to-4
Decoder
2 d2
0 0 1 0 1 0 0 0 0 0 0 EN 3 d3
0 1 0 0 0 1 0 0 0 0 0
1-to-2 Decoder

0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
0 d4
a1 Bottom
1 d5
1 0 1 0 0 0 0 0 1 0 0 a0 2-to-4
Decoder
2 d6
1 1 0 0 0 0 0 0 0 1 0
EN 3 d7
1 1 1 0 0 0 0 0 0 0 1

7
BCD to 7-Segment Decoder
 Seven-Segment Display:
 Made of Seven segments: light-emitting diodes (LED)
 Found in electronic devices: such as clocks, calculators, etc.

a
I3 BCD to b
I2 c
 BCD to 7-Segment Decoder I1
7-Segment d
e
I0 Decoder f
g
 Accepts as input a BCD decimal digit (0 to 9)
 Generates output to the seven LED segments to display the BCD digit
 Each segment can be turned on or off separately

BCD to 7-Segment Decoder


Specification: Truth Table
 Input: 4-bit BCD (I3, I2, I1, I0) BCD input 7-Segment Output
I3 I2 I1 I0 a b c d e f g
 Output: 7-bit (a, b, c, d, e, f, g)
0 0 0 0 1 1 1 1 1 1 0
 Display should be OFF for Non-BCD 0 0 0 1 0 1 1 0 0 0 0
input codes. 0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
Implementation can use:
0 1 0 0 0 1 1 0 0 1 1
 A binary decoder 0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
 Additional gates
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1010 to 1111 0 0 0 0 0 0 0

8
Implementing a BCD to 7-Segment Decoder
Truth Table
a
I3 I2 I1 I0 a b c d e f g
0
b 0 0 0 0 1 1 1 1 1 1 0
1
2 0 0 0 1 0 1 1 0 0 0 0
c
0 0 1 0 1 1 0 1 1 0 1
I3 4-to-10 3
I2 4 d 0 0 1 1 1 1 1 1 0 0 1
Binary 0 1 0 0 0 1 1 0 0 1 1
I1 5
I0 Decoder 6 e 0 1 0 1 1 0 1 1 0 1 1
7 0 1 1 0 1 0 1 1 1 1 1
8 0 1 1 1 1 1 1 0 0 0 0
9 f 1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
𝐼3 (𝐼2 + 𝐼1 ) g 1010 – 1111 0 0 0 0 0 0 0
Input > 9
NOR gate is used for 0's

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