COMBINATIONAL CIRCUITS

Combinational Circuit
• When logic gates are connected Combinational
together to produce a specified Inputs circuit Outputs
output for certain specified
combinations of input variables,
with no storage involved, the
resulting circuit is called
combinational logic.

• The output variables at all times

depend on the combination of
input variables.
•Example: ~(A*B) and ~(C*D) with an OR gate
 Combinational Circuits

Applications:
• Derive the boolean expression for some binary calculation (e.g.,
addition)
• Then build the circuit using the various logic gates
 Half Adder
– Notice that sum computes the same as XOR and carry
computes the same as AND
– We build an Adder using just one XOR and one AND gate

Block diagram Logic Diagram

 Half Adder

Truth table K-Map

 Full Adder
• The half adder really only does half
the work
– adds 2 bits, but only 2 bits
• If we want to add 2 n-bit numbers, we
need to also include the carry in from
the previous half adder which is
possible using full adder circuit.

• The sum is 1 only if one of x, y and

carry in are 1, or if all three are 1, the
sum is 0 otherwise

• The carry out is 1 if two or three of x, y

and carry in were 1, 0 otherwise
Full Adder
 Full Adder

or

Implementation using two half-adders and an OR gate

 Subtractors
A half-subtractor is a combinational circuit that subtracts
two bits and produces their difference.
• Half subtractor

Truth table K-Map

 Subtractors

Limitations of half subtractor

In multidigit subtraction ,we have to subtract two bits along with

the borrow of the previous digit subtraction. Effectively such subtraction
requires subtraction of three bits, This is not possible with half-subtractor.
 Full Subtractor
A full subtractor is a combinational circuit that performs a subtraction
between three bits taking into account borrow of the lower significant
stage.

Truth table K-Map

 Full Subtractor

Boolean function for difference and borrow

Full Subtractor

Logic diagram
 Full Subtractor
Implementation using two half-subtractors
and an OR gate
 Serial Adder/Subtractor
Two numbers stored in right shift registers A and B can be added serially.

Serial Adder
 Parallel Adder
• A single full adder is capable of adding two one-bit numbers and an
carry.

• In order to add binary numbers with more than one bit, additional full
adders must be employed.

• A n-bit, parallel adders can be constructed using number of full adder

circuits connected in parallel i.e. the carry output of each adder is
connected to the carry input of the next higher-order adder.
Parallel Adder
n-bit parallel adder

4-bit parallel adder

 Parallel Adder
4-bit binary parallel adder(IC74LS83)

Eight bit adder using two 74823IC’s

 Parallel Subtractor
• Subtraction of binary numbers can be done most
conveniently by means of complements.

• Subtaction A-B can be done by taking 2’s complement of

B and adding it to A.

• Take 1’s complement of B (using an inverter)and add one

to LSB pair of bits
Parallel Subtractor
 Parallel Adder/Subtractor
• The addition and subtraction operations can combined into one ciruit with one
common binary adder using an XOR gate with each full adder.
• Mode M controls the operation of the circuit.
• M=0; Adder M=1; Subtractor
• When M=0, we have, the full adders receive the value of B, with
the input carry being zero, it performs the function of A+B.
• When M=1,we have .The B inputs are all
complemented and a 1 is added through input carry.The circuit performs the
operation A plus the 2’s Complement of b,i.e., A-B.
Parallel Adder/Subtractor
Comparison-Serial/Parallel Adder
 BCD Adder
• It is a circuit that adds two BCD digits and produces a sum digit also
in BCD.
• To implement the BCD Adder we require:
– 4-bit binary adder for initial addition
– Logic circuit to detect sum greater than 9
– One more 4-bit adder to add six in the sum if the sum is greater than 9 or
carry is 1.
– The logic circuit to detect sum >9 can be determined by simplifying the
boolean expression of given truth table.
 BCD Adder

Y=S3S2+S3S1

Logical expression to add 6

Truth table
BCD Adder
Design-8 bit BCD Adder(IC74283)
 Magnitude Comparator
• A comparator is a special
combinational circuit designed
primarily to compare the relative
magnitude of two binary numbers.
i.e.,(A<B,A=B,A>B).

• Depending upon the relative

magnitudes of the two number, one
of the outputs will be high.
Design of 2 bit comparator using gates
Design of 2 bit comparator using
gates
Logic diagram of 2- bit comparator
Design of 8- bit comparator using
IC7485
Binary to BCD Code Converter
Binary to BCD Code Converter
Binary to BCD Code Converter
Logic diagram-(Binary-BCD)
BCD to Binary Converter
BCD to Binary Converter
BCD to Binary Converter
BCD to Binary Converter
Logic diagram-(BCD to Binary)
 BCD to Excess 3 Converter
• XS3 code can be obtained by adding 3 to
each BCD number.
BCD to Excess 3 Converter
BCD to Excess 3 Converter
Excess-3 to BCD Converter
Excess-3 to BCD Converter
Excess-3 to BCD Converter
Binary to Gray Code Converter-
Truth table
Binary to Gray Code Converter-K Map
Binary to Gray Code Converter-
logic diagram
Gray to Binary Code Converter-
Truth table
Gray to Binary Code Converter-K Map
Gray to Binary Code Converter-K
Map & logic diagram
BCD to Gray Code Converter-Truth table
BCD to Gray Code Converter-K Map
BCD to Gray Code Converter-Logic diagram
 Decoders
• A binary decoder has ‘n’ bit binary input
and a one activated exactly one of 2 n
outputs.
2-to-4-line decoder –Logic diagram
2-to-4-line decoder –Truth table
• If the enable input is
one,and only one , of the
outputs Y0 to Y3 is active
for the given input.

•If the enable input is 0,

then all the outputs are
0.
3-to-8-line decoder –Logic diagram
3-to-8-line decoder –Truth table
4x16 decoder using two 74LS138IC’s
BCD to Decimal Decoder
 Encoder
• An encoder is a digital circuit that performs the
inverse operation of a decoder.

• An encoder has 2n input lines and n output lines.

• In encoder the output lines generate the binary

code corresponding to the input value.
Decimal to BCD Encoder
Octal to Binary Encoder-Truth table
 Priority Encoder
• It is an encoder circuit that
includes priority function.

• If two or more inputs are

equal to 1 at the same time,
the input having the highest
priority will take
precedence.

• D3-higest priority ,
• D0- lowest priority.
4-bit Priority Encoder-K Map
4-bit Priority Encoder
 Multiplexers
• It is a digital switch. It allows digital
information from several sources to be routed
onto a single output line.

• Normally it has 2n input lines and n output

lines.

• Selection lines are decoded to select a

particular AND gate.

• Multiplexers means ‘many to one’.

• It is also called as data selector because the

output bit depends on the input data bit that is
selected.
 Multiplexers

Truth table
Logic diagram
Quadruple 2-to-1 line multiplexer
•It has 4 MUX each capable of
selecting one of the two input
lines.
•Output Y1 can be selected to
have the value of 1 or B1
respectively.
•The selection line ‘s’ selects
one of the two lines in all 4
MUX.
•The control input ‘E’ enables
the MUX in ‘0’ state and
disables them in ‘1’ state.
•When E=1,o/p have all o’s,
regardless of the value of S.
74xx151 8 to 1 multiplexer
Design of 32x1 MUX using two 74ls150 IC’S
Design of 32x1 MUX using four 8x1 MUX
AND 2X4 DECODER
 Implementation of Combinational
logic using MUX
• F(A,B,C)= Σ m(1,3,5,6)

MUX Implementation table

Truth table implementation
Implementation of Combinational
logic using MUX
 Implementation of Combinational
logic using MUX
• F(P,Q,R,S)= Σ m(0,1,3,4,8,9,15)

Implementation table
MUX implementation
 Implementation of Combinational
logic using MUX
F(A,B,C,D)=Σ(0,1,2,4,6,9,12,14)

Implementation table MUX Implementation

Implementation of Combinational
logic using MUX
Implementation of Combinational
logic using MUX
 Demultiplexers (DEMUX)
• It is a circuit that receives
information on a single line and
transmits this information on
one of 2n possible output lines.

• The selection of specific output

line is controlled by the values
of n selection lines.

• The single input variable Din

has a path to all four outputs,
but the input information is
directed to only one of the
output lines.
 Demultiplexers (DEMUX)

Function table Logic diagram

Design of 1:8 demux uing two 1:4 demux
Implementation of full subtractor using
demux