Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

The Devices
July 30, 2002

© Digital Integrated Circuits2nd Devices

 Goal of this chapter
 Present intuitive understanding of device
operation
 Introduction of basic device equations
 Introduction of models for manual
analysis
 Introduction of models for SPICE
simulation
 Analysis of secondary and deep-sub-
micron effects
 Future trends

© Digital Integrated Circuits2nd Devices

 The Diode
B Al A
SiO2

Cross-section of pn-junction in an IC process

A Al
p A

B B
One-dimensional
representation diode symbol

Mostly occurring as parasitic element in Digital ICs

© Digital Integrated Circuits2nd Devices

 Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n

hole drift
electron drift
Charge 
Density
+ x (b) Charge density.
Distance
-

Electrical 
Field x (c) Electric field.

V
Potential
 (d) Electrostatic
x potential.
-W 1 W2

© Digital Integrated Circuits2nd Devices

 Diode Current

© Digital Integrated Circuits2nd Devices

 Forward Bias

pn (W2)
pn0

Lp

np0

-W1 0 W2 x
p-region n-region

diffusion

Typically avoided in Digital ICs

© Digital Integrated Circuits2nd Devices
 Reverse Bias

pn0

np0

-W1 0 W2 x
p-region n-region

diffusion

The Dominant Operation Mode

© Digital Integrated Circuits2nd Devices

 Models for Manual Analysis


ID = IS(eV D/ T – 1) ID
+ +
+
VD VD VDon
–
– –

(a) Ideal diode model (b) First-order diode model

© Digital Integrated Circuits2nd Devices

 Junction Capacitance

© Digital Integrated Circuits2nd Devices

 Diffusion Capacitance

© Digital Integrated Circuits2nd Devices

 Secondary Effects
0.1
ID (A)

–0.1
–25.0 –15.0 –5.0 0 5.0
VD (V)

Avalanche Breakdown

© Digital Integrated Circuits2nd Devices

 Diode Model

RS

VD ID CD

© Digital Integrated Circuits2nd Devices

 SPICE Parameters

© Digital Integrated Circuits2nd Devices

 What is a Transistor?

A Switch! An MOS Transistor

VGS V T |VGS|

Ron
S D

© Digital Integrated Circuits2nd Devices

 The MOS Transistor

Polysilicon Aluminum

© Digital Integrated Circuits2nd Devices

MOS Transistors -
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

© Digital Integrated Circuits2nd Devices

Threshold Voltage: Concept
+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

© Digital Integrated Circuits2nd Devices

The Threshold Voltage

© Digital Integrated Circuits2nd Devices

 The Body Effect
0.9

0.85

0.8

0.75

0.7
VT (V)

0.65

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
VBS (V)

© Digital Integrated Circuits2nd Devices

 Current-Voltage Relations
A good ol’ transistor
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

© Digital Integrated Circuits2nd Devices

Transistor in Linear

VGS VDS
S
G ID
D

n+ –
V(x)
+ n+

L x

p-substrate

MOS transistor and its bias conditions

© Digital Integrated Circuits2nd Devices

Transistor in Saturation
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off

© Digital Integrated Circuits2nd Devices

Current-Voltage Relations
Long-Channel Device

© Digital Integrated Circuits2nd Devices

A model for manual analysis

© Digital Integrated Circuits2nd Devices

 Current-Voltage Relations
The Deep-Submicron Era
-4
x 10
2.5

VGS= 2.5 V
Early Saturation
2

VGS= 2.0 V
1.5
ID (A)

Linear
1
VGS= 1.5 V Relationship

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

© Digital Integrated Circuits2nd Devices

 Velocity Saturation
 n (m/s)

sat = 105
Constant velocity

Constant mobility (slope = µ)

c = 1.5  (V/µm)

© Digital Integrated Circuits2nd Devices

 Perspective

ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

© Digital Integrated Circuits2nd Devices
 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

© Digital Integrated Circuits2nd Devices

 ID versus VDS

-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
ResistiveSaturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5

ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

© Digital Integrated Circuits2nd Devices

A unified model
for manual analysis

S D

© Digital Integrated Circuits2nd Devices

 Simple Model versus SPICE
-4
x 10
2.5

VDS=VDSAT
2

Velocity
1.5
Saturated
ID (A)

Linear
1

VDSAT=VGT
0.5

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)

© Digital Integrated Circuits2nd Devices

 A PMOS Transistor
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8
VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

© Digital Integrated Circuits2nd Devices

 Transistor Model
for Manual Analysis

© Digital Integrated Circuits2nd Devices

 The Transistor as a Switch
VGS V T
Ron IDI
D VVGS ==VVD D
GS DD
S D
RRmid
mid

RR0
0

VVDS
DS
VVDD/2
DD/2
VVDD
DD

© Digital Integrated Circuits2nd Devices

 The Transistor as a Switch
5
x 10
7

5
Req (Ohm)

0
0.5 1 1.5 2 2.5
VDD (V)

© Digital Integrated Circuits2nd Devices

 The Transistor as a Switch

© Digital Integrated Circuits2nd Devices

MOS Capacitances
Dynamic Behavior

© Digital Integrated Circuits2nd Devices

Dynamic Behavior of MOS Transistor
G

CGS CGD

S D

CSB CGB CDB

© Digital Integrated Circuits2nd Devices

 The Gate Capacitance
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+

Cross section

© Digital Integrated Circuits2nd Devices

 Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

© Digital Integrated Circuits2nd Devices

Gate Capacitance

CG C
WLC ox WLC ox CG C
2WLC ox
CG CS 3
WLC ox C G CS = CG CD WLC ox
CGC B
2 2 CGCD

VG S 0 VDS /( VG S-VT) 1

Capacitance as a function of the

Capacitance as a function of VGS
(with VDS = 0) degree of saturation

© Digital Integrated Circuits2nd Devices

 Measuring the Gate Cap

3 102 16
10
9

Gate Capacitance (F)

V GS
8
I 7
6
5
4
3
2
2 2 2 1.52 1 2 0.5 0 0.5 1 1.5 2
V GS (V)

© Digital Integrated Circuits2nd Devices

 Diffusion Capacitance
Channel-stop implant
NA 1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS SubstrateN A

© Digital Integrated Circuits2nd Devices

Junction Capacitance

© Digital Integrated Circuits2nd Devices

Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest

© Digital Integrated Circuits2nd Devices

 Capacitances in 0.25 m CMOS
process

© Digital Integrated Circuits2nd Devices

The Sub-Micron MOS Transistor
 Threshold Variations
 Subthreshold Conduction
 Parasitic Resistances

© Digital Integrated Circuits2nd Devices

 Threshold Variations

VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering

the length (for low VDS ) (for low L)

© Digital Integrated Circuits2nd Devices

 Sub-Threshold Conduction
-2
10 The Slope Factor
Linear qVGS
CD
10
-4
I D ~ I 0e nkT
, n 1 
Cox
-6
10 Quadratic
S is VGS for ID2/ID1 =10
ID (A)

-8
10

-10 Exponential
10

-12 VT Typical values for S:

10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

© Digital Integrated Circuits2nd Devices

 Sub-Threshold ID vs VGS
qVGS
 qV
 DS 
I D I 0 e nkT  1  e kT 
 
 

VDS from 0 to 0.5V

© Digital Integrated Circuits2nd Devices

 Sub-Threshold ID vs VDS
qVGS
 qV
 DS 
I D I 0 e nkT  1  e kT  1   VDS 
 
 

VGS from 0 to 0.3V

© Digital Integrated Circuits2nd Devices

 Summary of MOSFET Operating
Regions
 Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence

© Digital Integrated Circuits2nd Devices

 Parasitic Resistances

Polysilicon gate
Drain
contact
G LD

VGS,eff

W
S D

RS RD

Drain

© Digital Integrated Circuits2nd Devices

 Latch-up

© Digital Integrated Circuits2nd Devices

 Future Perspectives

25 nm FINFET MOS transistor

© Digital Integrated Circuits2nd Devices