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Module3 - SPICE and CMOS VTC

The document discusses simulation tools used at various levels of abstraction in integrated circuit design. It focuses on circuit simulation tools like SPICE that use device models and a circuit netlist to predict circuit behavior. SPICE is introduced as the most widely used circuit simulator, along with some of its key MOSFET device models like BSIM that improve accuracy for modern transistors. The CMOS inverter is then analyzed as an example circuit, with its static behavior explained using a switch-level model and its voltage transfer characteristic graphically constructed from the load lines of the NMOS and PMOS transistors.

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dilshan singh
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170 views

Module3 - SPICE and CMOS VTC

The document discusses simulation tools used at various levels of abstraction in integrated circuit design. It focuses on circuit simulation tools like SPICE that use device models and a circuit netlist to predict circuit behavior. SPICE is introduced as the most widely used circuit simulator, along with some of its key MOSFET device models like BSIM that improve accuracy for modern transistors. The CMOS inverter is then analyzed as an example circuit, with its static behavior explained using a switch-level model and its voltage transfer characteristic graphically constructed from the load lines of the NMOS and PMOS transistors.

Uploaded by

dilshan singh
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Device Models

CMOS INVERTER
VTC

References
Weste
Baker
Kang
Rabaey
Fabricating chips is expensive and time-consuming, so designers
need simulation tools to explore the design space and verify
designs before they are fabricated.

Simulators operate at many levels of abstraction, from process


through architecture.
• Process simulators such as SUPREME, ATHENA, predict how
factors in the process recipe such as time and temperature
affect device physical and electrical characteristics.
• Circuit simulators such as SPICE and Spectre use device
models and a circuit netlist to predict circuit voltages and
currents, which indicate performance and power
consumption.
• Logic simulators such as ModelSim, Xilinx are widely
used to verify correct logical operation of designs
specified in a hardware description language (HDL).

• Architecture simulators, sometimes offered with a


processor’s development toolkit, work at the level of
instructions and registers to predict throughput and
memory access patterns, which influence design decisions
such as pipelining and cache memory organization.

• VLSI designers are primarily concerned with circuit and


logic simulation.
Is it better to predict circuit behavior using paper-and-pencil analysis ?
or with simulation?

• VLSI circuits are complex and modern transistors have nonlinear,


nonideal behavior, so simulation is necessary to accurately predict
detailed circuit behavior.

• Even when closed-form solutions exist for delay or transfer


characteristics, they are too time-consuming to apply by hand to large
numbers of circuits.

On the other hand, circuit simulation is notoriously prone to errors:

• garbage in, garbage out(GIGO).

• The simulator accepts the model of reality provided by the designer,


but it is very easy to create a model that is inaccurate or incomplete.
Moreover, the simulator only applies the stimulus provided by the
designer, and it is common to overlook the worst-case stimulus.
SPICE
• SPICE (Simulation Program with Integrated Circuit Emphasis) was
originally developed in the 1970s at Berkeley [Nagel75].

• It solves the nonlinear differential equations describing components such


as transistors, resistors, capacitors, and voltage sources.

• SPICE was originally developed in FORTRAN. There are free versions of


SPICE available on most platforms, but the commercial versions tend to offer more
robust numerical convergence. In particular, HSPICE is widely used in industry because
it converges well, supports the latest device and interconnect models, and has a large
number of enhancements for measuring and optimizing circuits.

• PSPICE is another commercial version with a free limited student version. LTSpice is also
a free version.

SPICE offers many ways to analyze circuits, but digital VLSI circuit designers are primarily
interested in DC and transient analysis that predicts the node voltages given inputs that
are fixed or arbitrarily changing in time.
Device Models

• SPICE provides a wide variety of MOS transistor models with


various trade-offs between complexity and accuracy. Level 1
and Level 3 models were historically important, but they are no
longer adequate to accurately model very small modern
transistors.

• BSIM (Berkeley Short-channel IGFET Model) are more accurate


and are presently the most widely used.

• BSIM refers to a family of MOSFET transistor models for


integrated circuit design.
• It also refers to the BSIM group located in the Department of
Electrical Engineering and Computer Sciences (EECS) at the
University of California, Berkeley, that develops these models.
• To attempt standardization of these models so that a
set of model parameters may be used in different
simulators, an industry working group was formed,
the Compact Model Coalition, to choose, maintain
and promote the use of standard models.

• BSIM models, developed at UC Berkeley are one of


these standards.

• They include BSIM3, BSIM4,  BSIM-BULK, BSIM-


SOI, BSIM-CMG, and BSIM-IMG.
Level 1 Models
The SPICE Level 1, or Shichman-Hodges Model [Shichman68] is closely related to the
Shockley model enhanced with channel length modulation and the body effect.

 
The parameters from the SPICE model are given in ALL CAPS. Notice that is
written instead as KP(Weff /Leff ), where KP is a model parameter playing the
role of k.

Weff and Leff are the effective width and length.


LAMBDA term (LAMBDA = 1/VA) models channel length modulation (
The threshold voltage is modulated by the source-to-body voltage Vsb through the
body effect

The gate capacitance is calculated from the oxide thickness TOX. The default gate
capacitance model in HSPICE is adequate for finding the transient response of digital circuits.

More elaborate models exist that capture nonreciprocal effects that are important for
analog design.

Level 1 models are useful for teaching because they are easy to correlate with hand
analysis, but are simplistic for modern design. The model also includes terms to compute the
diffusion capacitance,

.model NMOS NMOS (LEVEL=1 TOX=40e-10 KP=155E-6 LAMBDA=0.2


+ VTO=0.4 PHI=0.93 GAMMA=0.6
+ CJ=9.8E-5 PB=0.72 MJ=0.36
+ CJSW=2.2E-10 PHP=7.5 MJSW=0.1)
Level 2 and 3 Models

The SPICE Level 2 and 3 models add effects of velocity saturation, mobility
degradation, subthreshold conduction, and drain-induced barrier lowering.

The Level 2 model is based on the Grove-Frohman equations [Frohman69], while


the Level 3 model is based on empirical equations that provide similar accuracy,
faster simulation times, and better convergence.

However, these models still do not provide good fits to the measured I-V
characteristics of modern transistors.
BSIM Models

The Berkeley Short-Channel IGFET1 Model (BSIM) is a very


elaborate model that is now widely used in circuit simulation.
The models are derived from the underlying device physics but
use an enormous number of parameters to fit the behavior of
modern transistors.

BSIM versions 1, 2, 3v3, and 4 are implemented as SPICE levels


13, 39, 49, and 54, respectively.
• BSIM 3 and 4 require entire books [Cheng99, Dunga07] to
describe the models.
They include over 100 parameters and the device equations
span 27 pages.
• BSIM is quite good for digital circuit simulation.
Features of the model include:
• Continuous and differentiable I-V characteristics across subthreshold, linear,
and saturation regions for good convergence

• Sensitivity of parameters such as Vt to transistor length and width.

• Detailed threshold voltage model including body effect and drain-induced barrier
Lowering, Velocity saturation, mobility degradation, and other short-channel effects
Multiple gate capacitance models,
THE CMOS INVERTER
The inverter is truly the nucleus of all digital designs. Once
its operation and properties are clearly understood,
designing more intricate structures such as NAND gates,
adders, multipliers is greatly simplified.

We analyze the gate with respect to the different design metrics


• cost, expressed by the complexity and area
• integrity and robustness, expressed by the static (or
steady-state) behavior
• performance, determined by the dynamic (or transient)
response
• power consumption
The Static CMOS Inverter

the transistor is nothing more


than a switch with an infinite
off resistance
(for |VGS| < |VT|),

and a finite on-resistance


(for |VGS| > |VT|).
important properties of static CMOS can
be derived from this switch level view:
• The high and low output levels equal
VDD and GND, respectively; in other
words, the voltage swing is equal to the
supply voltage. This results in high noise
margins.
• The logic levels are not dependent
upon the relative device sizes, so that the
transistors can be minimum size. Gates
with this property are called ratioless.

This is in contrast with ratioed logic,


where logic levels are determined by the
relative dimensions of the composing
transistors.
• The input resistance of the CMOS inverter is extremely high,
as the gate of an MOS transistor is a virtually perfect insulator
and draws no dc input current.

• Since the input node of the inverter only connects to


transistor gates, the steady-state input current is nearly zero.
A single inverter can theoretically drive an infinite number of
gates (or have an infinite fan-out) and still be functionally
operational;

• No direct path exists between the supply and ground rails under
steady-state operating conditions (this is, when the input and
outputs remain constant). The absence of current flow (ignoring
leakage currents) means that the gate does not consume any
static power.
Voltage-Transfer characteristic (VTC)

VTC can be graphically deduced by


superimposing the current characteristics of the
NMOS and the PMOS devices. Such a graphical
construction is traditionally called a load-line
plot.
It requires that the I-V curves of the NMOS and
PMOS devices are transformed onto a common
coordinate set.
Let’s select the input voltage Vin, the output
voltage Vout and the NMOS drain current IDN as
the variables of choice.

• The PMOS I-V relations can be translated into


this variable space by the following relations
(the subscripts n and p denote the NMOS and
PMOS devices, respectively),
Assume VDD = 2.5 V
Load curves for NMOS and PMOS transistors of the static CMOS inverter (VDD = 2.5 V).
The dots represent the dc operation points for various input voltages.
For a dc operating points to be valid, the currents through the
NMOS and PMOS must be equal. It means that the dc points must
be located at the intersection of corresponding load lines. A number
of those points (for Vin = 0, 0.5, 1, 1.5, 2, and 2.5 V) are marked.

As can be observed, all operating points are located either at the


high or low output levels

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