ECE5307 – VLSI DESIGN

COMPOUND GATES

Compound gates can do any inverting function

Y = ( A • B) + (C • D)
Ex: AND-AND-OR-INV (AOI22)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
EXAMPLE: O3AI

Y = ( A + B + C) • D
EXAMPLE: O3AI

Y = ( A + B + C) • D

A
B
C D
Y
D
A B C
We must first complement this equation, and then apply
DeMorgan’s Theorem (several times!).

Y=A+B+AC
Y=A+B+AC

(
= A +B AC)( )
= (A + B )(A + C )

= (A + B )(A + C )
= AA + AC + BA + BC
= A (A + B + C ) + BC
= A + BC

Logically, this result says:

Y is low if A is high, OR
if both B AND C are high.

We can thus realize this logic with the following NMOS PDN:
 Y

A B

PDN C

Y = A + BC

Step2: Design the PUN

First, we must rewrite the Boolean function as:

(
Y = f A, B,C )
In other words, write the un-complemented output in terms
of complemented inputs.
Again, using DeMorgan’s Theorem:

Y = A + B + AC
= AB + A C
(
= A B+ C )
Logically, this result says:

Y is high if A is low AND

either B OR C are low.

We can thus realize this logic with the following PMOS PUN:
 VDD

B C

PUN Y

(
Y = A B+ C )

Thus, the entire CMOS realization is:

 VDD

B C

Y=A+B+AC

A B

C
11/14/2004 Example Another CMOS Logic Gate Synthesis.doc 1/4

Example: Another CMOS

Logic Gate Synthesis
Now let’s design a gate that realizes this Boolean algebraic
expression:
(
Y = A+B C )
Step 1: Design PDN

First, let’s rewrite Boolean expression as Y = f (A,B,C):

( )
Y = A +B C

Y = (A +B)C

( )
Y = A+B +C

Y = AB +C

Q: Yikes! We cannot write this expression explicitly in terms

of uncomplemented inputs A, B, and C ! The input C appears as
C in the expression. What do we do now?

A: An easy problem to solve! We can essentially make a

substitution of variables:
C= C
11/14/24

And thus:
Y = AB+ C

Therefore, the inputs to this logic gate should be A, B, and C’

(i.e, A, B, and the complement of C ).

Note that this Boolean expression “says” that:

“The ouput is low if either,A AND B are both high, OR C’ is

high”

Of course another way of “saying” this is:

“The output is low if either A AND B are both high, OR C is

low”

The PDN is therefore:

Y
Y = AB + C 
= AB + C

C = C
B
Step 2: Design the PUN

Note we have as similar problem as before—the expression

for Y cannot explicitly be written in terms of complemented
inputs A, B, and C:
(
Y = A+B C )
Note we can again solve this problem by using the same
substitution of variable C:

C= C
C= C

Therefore:
( )
Y = A + B C

= (A + B)C

This expression “says” that:

“The output will be high if, either A OR B are low, AND C’ is

low”

Which is equivalent to saying:

“The output will be high if, either A OR B are low, AND C is

high”

The CMOS digital logic device is therefore:

 VDD

A B

( )
Y = A+ B C 
C = C = (A + B )C

= (A + B )C
Y

C = C
B
NMOS CUTOFF

Let us assume Vs = Vb

No channel, if Vgs = 0
Ids = 0 Vgs = 0
g
Vgd
+ +
- -
s d

n+ n+

p-type body
b
NMOS LINEAR

•Channel forms if Vgs > Vt

Vgs > Vt
Vgd = Vgs
+ g +
•No Current if Vds = 0 - -
s d
n+ n+ Vds = 0

•Linear Region: p-type body

b

•If Vds > 0, Current flows Vgs > Vt

Vgs > Vgd > Vt
from d to s ( e- from S to D) + g +
- - Ids
s d
•Ids increases linearly n+ n+
0 < Vds < Vgs-Vt
with Vds if Vds > Vgs – Vt p-type body
b
•Similar to linear resistor
NMOS SATURATION
Channel pinches off if Vds > Vgs – Vt

Ids “independent” of Vds, i.e., current saturates

Similar to current source

Vgs > Vt
Pinch off Current + g
+
Vgd < Vt

- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
I-V CHARACTERISTICS
In Linear region, Ids depends on
• How much charge is in the channel

• How fast is the charge moving

NMOS LINEAR I-V
Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross

Qchannel
I ds =
t
= Cox
W V − V − Vds V
 gs  ds
 2 
t
L
W
 = Cox
=  Vgs − Vt − ds Vds
V
L
 2
 TRIODE REGION / LINEAR REGION

A voltage-controlled resistor @small VDS

B S D
- + ID
+++ VGS1>Vt increasing
+++
metal
VGS
- oxide
- - -
n+ n+
p

B S -+ D

+++ VGS2>VGS1
+++
+++
metal G
- oxide
- - - --
n+ n+
p
VDS
cut-off
B S -+ D 0.1 v
+++ VGS3>VGS2
+++
+++ +++
Increasing VGS puts more charge in
metal the channel, allowing more drain
- - oxide
-------
n+ n+ current to flow
p
SATURATION REGION
occurs at large VDS

As the drain voltage increases, the difference in voltage between the

drain and the gate becomes smaller. At some point, the difference is
too small to maintain the channel near the drain → pinch-off
gate
G
body source drain
B S - + D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
SATURATION REGION
occurs at large VDS
The saturation region is when the MOSFET experiences pinch-off.
Pinch-off occurs when VG - VD is less than VT.

gate
G
body source drain
B S - + D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
SATURATION REGION
occurs at large VDS

VGS - VDS < VT or VGD < VT

VDS > VGS - VT

gate
G
body source drain
+
B S - D
VD>>Vs
+++
+++
+++
metal
oxide

n+ n+
p
SATURATION REGION
once pinch-off occurs, there is no further increase in drain current

saturation
ID
triode

increasing VDS>VGS-VT
VGS VDS<VGS-VT

VDS

0.1 v
SIMPLIFIED MOSFET I-V EQUATIONS

Cut-off: VGS< VT
ID = IS = 0

Triode: VGS>VT and VDS < VGS-VT

ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS2]

Saturation: VGS>VT and VDS > VGS-VT

ID = 1/2kn’(W/L)(VGS-VT)2

where kn’= (electron mobility)x(gate capacitance)

= n(eox/tox) …electron velocity = nE

and VT depends on the doping concentration and gate material

used.
 MOSFET SCALING
Packing Density of MOSFETs in the chip should be as high as possible, the
sizes of the transistors are as small as possible.
The reduction of the sizes is commonly referred as Scaling
The operational characteristics of the MOS will change with the reduction
of its dimensions.
There are two basic types of size-reduction strategies: full scaling (also
called constant-field scaling) and constant voltage scaling.
The scaling reduces the total silicon area, thereby increasing the overall
functional density of the chip.
To describe device scaling, we introduce a constant scaling factor S > 1. All
horizontal and vertical dimensions of the large-size transistor are then
divided by this scaling factor to obtain the scaled device.
Table below shows the recent history of reducing feature sizes for the
typical CMOS gate-array process.
MOSFET SCALING
It is easy to recognize that the scaling of all
dimensions by a factor of S > 1 leads to
the reduction of the area occupied by the
transistor by a factor of S2

Full Scaling (Constant-Field Scaling

This scaling option attempts to preserve the
magnitude of internal electric fields in the
MOSFET, while the dimensions are scaled
down by a factor of S. To achieve this goal, all
potentials must be scaled down proportionally,
by the same scaling factor. Note that this
potential scaling also affects the threshold
voltage
 While the full scaling strategy dictates that the
Constant-Voltage Scaling
power supply voltage and all terminal voltages be
scaled down proportionally with the device
dimensions, the scaling of voltages may not be very
practical in many cases. In particular, the peripheral
and interface circuitry may require certain voltage
levels for all input and output voltages, which in turn
would necessitate multiple power supply voltages
and complicated level shifter arrangements. For
these reasons, constant-voltage scaling is usually
preferred over full scaling.

Constant field scaling Constant Voltage scaling

ACTIVITY
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of
each transistor will
increase decrease not change

Slide
ACTIVITY
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change

Slide
MOS INVERTER VOLTAGE TRANSFER CURVE
DC RESPONSE
DC Response: Vout vs. Vin for a gate
Ex: Inverter
• When Vin = 0 -> Vout = VDD

• When Vin = VDD -> Vout = 0

• In between, Vout depends on VDD

transistor size and current
Idsp
Vin Vout
• By KCL, must settle such that
Idsn
Idsn = |Idsp|

• We could solve equations

• But graphical solution gives more insight

Slide
TRANSISTOR OPERATION
Current depends on region of transistor behavior

For what Vin and Vout are nMOS and pMOS in

• Cutoff?

• Linear?

• Saturation?

Slide
NMOS OPERATION

Cutoff Linear Saturated

Vgsn < Vgsn > Vgsn >

VDD
Vdsn < Vdsn > Idsp
Vin Vout
Idsn

Slide
NMOS OPERATION
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Idsp
Vin Vout

Slide
Idsn
NMOS OPERATION
Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn V > V – V

dsn gsn tn

VDD

Idsp
Vgsn = Vin Vin Vout

Slide
Vdsn = Vout Idsn
NMOS OPERATION
Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

Vgsn = Vin
VDD

Vdsn = Vout Idsp

Vin Vout
Idsn

Slide
PMOS OPERATION
Cutoff Linear Saturated

Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout

Slide
Idsn
PMOS OPERATION
Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD

Idsp
Vin Vout
Idsn

Slide
PMOS OPERATION
Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

Vgsp = Vin - VDD
Vtp < 0
Vdsp = Vout - VDD

VDD

Idsp
Vin Vout
Idsn

Slide
 PMOS OPERATION
Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vdsp > Vgsp – Vtp
Vout < Vin - Vtp VDD
Vout > Vin - Vtp
Idsp
Vin Vout
Idsn
Vgsp = Vin - VDD Vtp < 0

Vdsp = Vout - VDD

Slide
I-V CHARACTERISTICS

Make pMOS is wider than nMOS such that n = p

Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Slide
Vgsp5
CURRENT VS. VOUT, VIN

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Slide
LOAD LINE ANALYSIS

For a given Vin:

• Plot Idsn, Idsp vs. Vout
• Vout must be where |currents| are equal in

Vin0 Vin5

Vin1 Vin4 VDD

Idsn, |Idsp|
Idsp
Vin Vout
Vin2 Vin3
Idsn
Vin3 Vin2
Vin4 Vin1

Slide
VDD
Vout
LOAD LINE ANALYSIS

Vin = 0

Vin0

Idsn, |Idsp|

Vin0
VDD
Vout

Slide
LOAD LINE ANALYSIS

Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout

Slide
LOAD LINE ANALYSIS

Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout

Slide
LOAD LINE ANALYSIS

Vin = 0.6VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout

Slide
LOAD LINE ANALYSIS

Vin = 0.8VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout

Slide
LOAD LINE ANALYSIS

Vin = VDD

Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout

Slide
DC TRANSFER CURVE

Transcribe points onto Vin vs. Vout plot

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

Slide
LOAD LINE SUMMARY

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

Slide
OPERATING REGIONS
Revisit transistor operating regions

Region nMOS pMOS VDD

A B

Vout
C
A
B
D
C E
0 Vtn VDD/2 VDD+Vtp
VDD
D Vin

Slide
OPERATING REGIONS
Revisit transistor operating regions

Region nMOS pMOS

A Cutoff Linear
VDD

B Saturation Linear A B

Vout
C Saturation Saturation C

D Linear Saturation
E Linear Cutoff D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

Slide
OPERATING REGIONS

Slide
OPERATING REGIONS

Slide
OPERATING REGIONS

Slide
OPERATING REGIONS

Slide
OPERATING REGIONS

Slide
BETA RATIO

If p / n  1, switching point will move from VDD/2

Called skewed gate
Other gates: collapse into equivalent inverter
VDD
p
= 10
n
Vout 2
1
0.5
p
= 0.1
n

0
VDD
Vin

Slide
NOISE MARGINS

How much noise can a gate input see before it does not
recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

Slide
LOGIC LEVELS

To maximize noise margins, select logic levels at

Vout

VDD

p/n > 1

Vin Vout

Vin
0
VDD

Slide
LOGIC LEVELS

To maximize noise margins, select logic levels at

• unity gain point of DC transfer characteristic
Vout

Unity Gain Points

VDD
Slope = -1
VOH

p/n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

Slide
PASS TRANSISTOR CIRCUITS

VDD VDD VDD

VDD VDD
VDD

VDD

VDD
VSS
NMOS PASS TRANSISTORS

We have assumed source is grounded

What if source > 0? VDD
• e.g. pass transistor passing VDD VDD
Let Vg = VDD
• Now if Vs > VDD-Vt, Vgs < Vt Vs
• Hence transistor would turn itself off
NMOS pass transistors pull-up no higher than VDD-Vtn
• Called a degraded “1”
• Approach degraded value slowly (low Ids)
PMOS pass transistors pull-down no lower than Vtp
• Called a degraded “0”
PASS TRANSISTOR CIRCUITS

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
Vs = |Vtp| VDD-Vtn
VDD VDD-2Vtn
VSS
PASS TRANSISTORS

Transistors can be used as switches

g g=0 Input g = 1 Output

s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
SIGNAL STRENGTH
Strength of signal
• How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
• But degraded or weak 1
pMOS pass strong 1
• But degraded or weak 0
Thus NMOS are best for pull-down network
Thus PMOS are best for pull-up network
 COMPLEMENTARY PASS LOGIC
For high performance design, a differential pass-
transistor logic family, called CPL or DPL, is commonly
used.
The basic idea is to accept true and complementary
inputs and produce true and complementary outputs.
A number of CPL gates (AND/NAND, OR/NOR, and
XOR/NXOR) are shown in Figure. below.
COMPLEMENTARY PASS LOGIC
 TRANSMISSION GATE LOGIC
The most widely-used solution to deal with the voltage-drop
problem is the use of transmission gates.

It builds on the complementary properties of NMOS and PMOS

transistors: NMOS devices pass a strong 0 but a weak 1, while
PMOS transistors pass a strong 1 but a weak 0.

The ideal approach is to use an NMOS to pull-down and a PMOS to

pull-up.

The transmission gate combines the best of both device flavors by

placing a NMOS device in parallel with a PMOS device.

The control signals to the transmission gate (C and C) are

complementary.
 TRANSMISSION GATES
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
TRANSMISSION GATES

Pass transistors produce degraded outputs

Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb
MULTIPLEXERS

2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 D0 0
0 X 1 Y
D1 1
1 0 X
1 1 X
MULTIPLEXERS
2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
GATE-LEVEL MUX DESIGN
=
YS+
D
1 S
D0(
to
oma
ny
tr
an
si
st
ors
)
How many transistors are needed?
GATE-LEVEL MUX DESIGN
=
YS+
D
1 S
D0(
to
oma
ny
tr
an
si
st
ors
)
How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
TRANSMISSION GATE MUX
Nonrestoring mux uses two transmission
gates
TRANSMISSION GATE MUX
Nonrestoring mux uses two transmission gates
• Only 4 transistors

D0
S Y
D1

S
D LATCH
When CLK = 1, latch is transparent
• Q follows D (a buffer with a Delay)
When CLK = 0, the latch is opaque
• Q holds its last value independent of D
a.k.a. transparent latch or level- sensitive latch

CLK CLK

D
Latch

D Q
Q
D LATCH DESIGN
Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

Old Q
CLK
 EXERCISE QUESTIONS
Implement the following logic gates using 2:1 Mux.

i. AND
ii. OR
iii. XOR
iv. XNOR
v. NOT
vi. NAND and
vii. NOR
 EXERCISE QUESTIONS
Draw the timing Diagram of the following logic
expressions with POSITIVE AND NEGATIVE
edge triggered clock

i. Y = A + B
ii. Y = AB
iii. Y = (AB)’
iv. Y = (A+B)’