MOS Field Effect

Transistor (MOSFET)
Şenol Mutlu
To learn about microprocessors such
RISC-V Dives Into AI. The
as ARM and RISC-V, you can take
adoption of RISC-V, a free and
EE443 course.
open-source computer
instruction-set architecture first
introduced in 2010, is taking off
like a rocket. According to
Semico Research Corp., the
number of chips that include at
least some RISC-V technology
will grow 73.6 percent per year
to 2027, when there will be some
The ET-SoC-1 packs more than 1,000 25 billion AI chips produced,
RISC-V cores onto a piece of silicon that accounting for US $291 billion in
consumes just 20 watts. revenue. IEEE Spectrum, 2022
Semiconductors and Electronic Devices 1
 MOS Field Effect Transistor (MOSFET)
•An electric field is applied normal to the surface of the
semiconductor (by applying a voltage to an overlying
electrode), to modulate the conductance of the
semiconductor
→Modulate drift current flowing between 2 contacts
(“source” and “drain”) by varying the voltage on the
“gate” electrode

EE130, UC Berkeley
Semiconductors and Electronic Devices 2
 The Bulk-Si MOSFET
Metal-Oxide-Semiconductor
Field-Effect Transistor: GATE LENGTH, Lg
OXIDE THICKNESS, Tox
Width, W
Gate
Desired characteristics:
• High ON current Source Drain
• Low OFF current
Substrate
M. Bohr, Intel Developer
JUNCTION DEPTH, Xj Forum, September 2004

• Current flowing between the SOURCE and DRAIN is

controlled by the voltage on the GATE electrode

CURRENT
• “N-channel” & “P-channel” MOSFETs VT
operate in a complementary manner
“CMOS” = Complementary MOS |GATE VOLTAGE|
EE130, UC Berkeley
Semiconductors and Electronic Devices 3
 Enhancement Mode vs. Depletion Mode

Enhancement Mode Depletion Mode

Conduction between source A gate voltage must be applied

and drain regions is enhanced to deplete the channel region
by applying a gate voltage in order to turn off the transistor

Semiconductors and Electronic Devices 4

 N-channel vs. P-channel
NMOS PMOS

N+ poly-Si P+ poly-Si

N+ N+ P+ P+

P-type Si n-type Si

• For current to flow, VGS > VT • For current to flow, VGS < VT

• Enhancement mode: VT > 0 • Enhancement mode: VT < 0

• Depletion mode: VT < 0 • Depletion mode: VT > 0

– Transistor is ON when VG=0V – Transistor is ON when VG=0V
D D
+ +
G G B VSD
B VDS +
+ +
+ VBS VSB
VGS VSG
- S- - S-
Semiconductors and Electronic Devices 5
 Qualitative Theory of the NMOSFET

VGS < VT:

VGS > VT :
Electrons flow from the
VDS  0 source to the drain by
drift, when VDS>0. (IDS
> 0.) The channel
potential varies from VS
VDS > 0 at the source end to VD
at the drain end. (The
inversion layer can be
modeled as a resistor.)
Linear region
The potential barrier to electron flow from the source
into the channel is lowered by applying VGS> VT
Semiconductors and Electronic Devices 6
VGS > VT VDS = VGS-VT When VD is increased to be
equal to VG-VT, the
inversion-layer charge
The depletion region near the drain widens (N+ drain is positively density at the drain end of
biased – i.e. reverse biased with respect to the substrate). the channel equals zero,
i.e. the channel becomes
VDS > VGS-VT “pinched off”
As VD is increased above
VG-VT, the length DL of the
“pinch-off” region increases.
High electrical field in this region act similar to the
collector-base junction in BJT in active mode, stripping
The voltage applied across
or collecting carriers from the channel. the inversion layer is
always VDsat=VGS-VT, and
so the current saturates:
If DL is significant
compared to L, then IDS will
𝐼𝐷𝑠𝑎𝑡 = 𝐼𝐷𝑆 ቚ
𝑉𝐷𝑆 =𝑉𝐷𝑠𝑎𝑡 increase slightly with
increasing VDS>VDsat, due to
“channel-length modulation”
Semiconductors and Electronic Devices 7
 Ideal MOSFET I-V Characteristics
(Enhancement Mode NMOS Transistor)

Saturation
Linear region
region

Cut-off
Region (IDS = 0)

VDsat=VGS-VT
Semiconductors and Electronic Devices 8
 Impact of Inversion-Layer Bias
• When a MOS device is biased into inversion, a pn
junction exists between the surface and the bulk.
• If the inversion layer contacts a heavily doped region
of the same type, it is possible to apply a bias to this
pn junction.

N+ poly-Si • VG is biased so that surface is inverted

+ + + + + + + + • n-type inversion layer is contacted by
SiO2 N+ region
- - - - - - - - -
N+
• If a bias VC is applied to the channel, A
p-type Si reverse bias (VB-VC) is applied between
the channel & body

Semiconductors and Electronic Devices 9

 Effect of VCB on fS, W, and VT
• Application of a reverse body bias → non-equilibrium
– 2 Fermi levels (one for n-region, one for p-region)
• separation = qVBC ➔fS is increased by VCB
• Reverse body bias widens W, increases Qdep
➔Qinv decreases with increasing VCB, for a given VGB
Qdep

2𝑞𝑁𝐴 𝜀𝑆𝑖 (2f𝐹 + 𝑉𝐶𝐵 )

𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝐶𝐵 + 2f𝐹 +
𝐶𝑜𝑥

fS
Vox

Reverse body bias increases Vt, hence decreases Qinv = Cox(Vg-Vt)

Semiconductors and Electronic Devices 10

 NMOSFET I-V Characteristics
• VD > VS
• Current in the channel flows by drift
• Channel voltage VC(y) varies continuously between
the source and the drain
2𝑞𝑁𝐴 𝜀𝑆𝑖 (2f𝐹 + 𝑉𝐶𝐵 (𝑦))
𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝐶𝐵 (𝑦) + 2f𝐹 +
𝐶𝑜𝑥
• Channel inversion charge density
𝑄𝑑𝑒𝑝 (𝑦)
𝑄𝑖𝑛𝑣 (𝑦) = −𝐶𝑜𝑥𝑒 𝑉𝐺 − 𝑉𝐹𝐵 − 𝑉𝐶𝐵 (𝑦) − 2𝜙𝑆 −
𝐶𝑜𝑥𝑒

W
Semiconductors and Electronic Devices 11
 1st-Order Approximation
• If we neglect the variation of Qdep with y, then

𝑄𝑑𝑒𝑝 = 2𝑞𝑁𝐴 𝜀𝑆𝑖 (2𝜙𝐹 + 𝑉𝑆𝐵 )

⇒ 𝑄𝑖𝑛𝑣 = −𝐶𝑜𝑥𝑒 𝑉𝐺 − 𝑉𝑇 + 𝑉𝑆𝐵 − 𝑉𝐶𝐵
𝑄𝑖𝑛𝑣 = −𝐶𝑜𝑥𝑒 𝑉𝐺 − 𝑉𝑇 + 𝑉𝑆 − 𝑉𝐶
where VT = threshold voltage at the source end:

2𝑞𝑁𝐴 𝜀𝑆𝑖 (2𝜙𝐹 + 𝑉𝑆𝐵 )

𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑆𝐵 + 2𝜙𝐹 +
𝐶𝑜𝑥
𝑑𝜙
𝐽𝑛 = 𝑞𝜇𝑛 𝑛Ε + 𝑞𝐷𝑛 ∇𝑛 ≈ 𝑞𝜇𝑛 𝑛Ε ≈ 𝐽𝑛𝑦 ≈ −𝑞𝜇𝑛 𝑛
𝑑𝑦
𝑥=𝑥𝑐 (𝑦)
𝐼𝐷 = − න න 𝐽𝑛𝑦 𝑑𝑥𝑑𝑧 = 𝑊 න 𝐽𝑛𝑦 𝑑𝑥
𝑥=0
Semiconductors and Electronic Devices 12
 NMOSFET Current (1st-order approx.)
• Consider an incremental length dy in the channel.
The voltage drop across this region is
𝜌𝑑𝑦 𝑑𝑦 𝐼𝐷𝑆 𝑑𝑦
𝑑𝑉𝐶 = 𝐼𝐷𝑆 𝑑𝑅 = 𝐼𝐷𝑆 = 𝐼𝐷𝑆 =−
𝑊𝑇𝑖𝑛𝑣 𝑞𝜇𝑒𝑓𝑓 𝑛𝑊𝑇𝑖𝑛𝑣 𝑄𝑖𝑛𝑣 𝜇𝑒𝑓𝑓 𝑊
𝐿 𝑉𝐷
න 𝐼𝐷𝑆 𝑑𝑦 = − න 𝜇𝑒𝑓𝑓 𝑊𝑄𝑖𝑛𝑣 (𝑉𝐶 )𝑑𝑉𝐶
0 𝑉𝑆
𝑉𝐷
𝑊
𝐼𝐷𝑆 = − 𝜇𝑒𝑓𝑓 න 𝑄𝑖𝑛𝑣 𝑉𝐶 𝑑𝑉𝐶
𝐿 𝑉𝑆
𝑊 𝑉𝐷𝑆
𝐼𝐷𝑆 = 𝜇𝑒𝑓𝑓 𝐶𝑜𝑥𝑒 𝑉𝐺 − 𝑉𝑇 − 𝑉𝐷𝑆 in the linear region
𝐿 2

𝑊
𝐼𝐷𝑆 = 𝐼𝐷𝑠𝑎𝑡 = 𝐶𝑜𝑥𝑒 𝜇𝑒𝑓𝑓 (𝑉𝐺 − 𝑉𝑇 )2 in the saturation region
2𝐿
Semiconductors and Electronic Devices 13
 Saturation Current, IDsat

• saturation region:
𝑉𝐷 ≥ 𝑉𝐷𝑠𝑎𝑡 = 𝑉𝐺 − 𝑉𝑇

𝑊
𝐼𝐷𝑠𝑎𝑡 = 𝐶𝑜𝑥𝑒 𝜇𝑒𝑓𝑓 (𝑉𝐺 − 𝑉𝑇 )2
2𝐿

2𝑞𝑁𝐴 𝜀𝑆𝑖 (2𝜙𝐹 + 𝑉𝑆𝐵 )

𝑉𝑇 = 𝑉𝐹𝐵 + 𝑉𝑆𝐵 + 2𝜙𝐹 +
𝐶𝑜𝑥

Semiconductors and Electronic Devices 14

 Effective Mobility
The mobility of carriers near the interface is significantly lower than carriers
in the semiconductor bulk due to interface scattering. Since the electron
concentration also varies with position, the average mobility of electrons in
the channel, known as the effective mobility, can be calculated by a
weighted average

For small values of VDS (i.e. for VDS << VG−VT),

𝑉𝐷𝑆
the NMOSFET can be modeled as a resistor: 𝑅𝐷𝑆 =
𝐼𝐷𝑆
𝑉𝐷𝑆
𝐼𝐷𝑆 = 𝑊𝑄𝑖𝑛𝑣 𝑣 = 𝑊𝑄𝑖𝑛𝑣 𝜇𝑒𝑓𝑓 Ε = 𝑊𝑄𝑖𝑛𝑣 𝜇𝑒𝑓𝑓
𝐿
where meff is the effective carrier mobility
𝑉𝐷𝑆 𝐿
𝑅𝐷𝑆 = =
𝐼𝐷𝑆 𝑊𝜇𝑒𝑓𝑓 𝐶𝑜𝑥𝑒 (𝑉𝐺 − 𝑉𝑇 )
Semiconductors and Electronic Devices 15
 MOSFET Threshold Voltage, VT
The expression that was previously derived for VT is the gate
voltage referenced to the body voltage that is required to reach the
threshold condition:

2qN A Si (2fF + VSB )

VT = VFB + VSB + 2fF +
Cox
Usually, the terminal voltages for a MOSFET are all referenced to
the source voltage. In this case,
2qN A Si (2fF + VSB )
VT = VFB + 2fF +
Cox
and the equations for IDS are

𝑊 𝑉𝐷𝑆 𝑊
𝐼𝐷𝑙𝑖𝑛 = 𝜇𝑒𝑓𝑓 𝐶𝑜𝑥𝑒 𝑉𝐺𝑆 − 𝑉𝑇 − 𝑉𝐷𝑆 𝐼𝐷𝑠𝑎𝑡 = 𝐶𝑜𝑥𝑒 𝜇𝑒𝑓𝑓 (𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐿 2 2𝐿

𝑉𝐷𝑆 < 𝑉𝐷𝑆𝑠𝑎𝑡 = 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷𝑆 ≥ 𝑉𝐷𝑆𝑠𝑎𝑡 = 𝑉𝐺𝑆 − 𝑉𝑇

Semiconductors and Electronic Devices 16

 The Body Effect
Note that VT is a function of VSB:
2qN A Si (2fF + VSB )
VT = VFB + 2fF +
Cox
2qN A Si (2fF ) 2qN A Si (2fF ) 2qN A Si (2fF + VSB )
= VFB + 2fF + − +
Cox Cox Cox

= VT 0 +
2qN A Si
Cox
( )
2fF + VSB − 2fF = VT 0 + g ( 2fF + VSB − 2fF )
where g is the body effect parameter

When the source-body pn junction is reverse-

biased, |VT| is increased. Usually, we want to
minimize g so that IDsat will be the same for all
transistors in a circuit
NMOS PMOS
Semiconductors and Electronic Devices 17
 P-Channel MOSFET
• The PMOSFET turns on when VGS < VTp
– Holes flow from SOURCE to DRAIN
 DRAIN is biased at a lower potential than the SOURCE
VG
• VDS < 0
VS VD
GATE IDS • IDS < 0
P+ P+ • |IDS| increases with
N • |VGS - VTp|
• |VDS| (linear region)
VB
• In CMOS technology, the threshold voltages
are usually symmetric: VTp = -VTn

Semiconductors and Electronic Devices 18

 PMOSFET I-V

• Linear region: 0 < 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇𝑝

𝑊 1
𝐼𝐷𝑆 = − 𝐶𝑜𝑥𝑒 𝜇𝑝,𝑒𝑓𝑓 (𝑉𝐺𝑆 − 𝑉𝑇𝑝 − 𝑉𝐷𝑆 )𝑉𝐷𝑆
𝐿 2

• Saturation region: 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇𝑝

𝑊
𝐼𝐷𝑆 = 𝐼𝐷𝑠𝑎𝑡 = − 𝐶𝑜𝑥𝑒 𝜇𝑝,𝑒𝑓𝑓 (𝑉𝐺𝑆 − 𝑉𝑇𝑝 )2
2𝐿

Semiconductors and Electronic Devices 19

 CMOS Devices and Circuits
CIRCUIT SYMBOLS NMOS:
N-channel P-channel VOUT saturation
INVERTER NMOS:
MOSFET MOSFET PMOS:
LOGIC SYMBOL cutoff

saturation
both
linear
G G PMOS:
linear
VDD
S D S D NMOS:
linear
PMOS:
CMOS INVERTER CIRCUIT
saturation
VDD
S
NMOS:
D linear
VIN VOUT PMOS:
D cutoff VIN

S 0 Vtn Vtp VDD

GND

• When VG = VDD , the NMOSFET is on and the PMOSFET is off.

• When VG = 0, the PMOSFET is on and the NMOSFET is off.
Semiconductors and Electronic Devices 20
 Common Source Amplifer
The gate is biased with a
positive voltage such that
VGS > Vth. The transistor is
in saturation.

DC Analysis:
𝑅2
𝑉𝐺𝑆 = 𝑉𝐷𝐷
𝑅1 + 𝑅2
𝑊
𝐼𝐷 = 𝐶𝑜𝑥𝑒 𝜇𝑒𝑓𝑓 (𝑉𝐺𝑆 − 𝑉𝑇 )2
2𝐿
𝑉𝐷𝑆 = 𝑉𝐷𝐷 - 𝐼𝐷 𝑅𝐷
Voltage gain:
𝑉𝑜𝑢𝑡 𝑉𝑑𝑠
𝐴𝑉 = = = 𝑔𝑚 𝑅𝑑
𝑉𝑖𝑛 𝑉𝑔𝑠

2𝐼𝐷 𝑊
𝑔𝑚 = 𝑡𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 = = 2𝐼𝐷 𝜇𝑛𝑒𝑓𝑓 𝐶𝑜𝑥𝑒
𝑉𝐺𝑆 − 𝑉𝑡 𝐿
Semiconductors and Electronic Devices 21