Ch 2: Basic MOS Device Physics

Text book: Design of Analog CMOS Integrated Circuits, B. Razavi, 2nd Edition,
McGraw Hill.

School of Electrical Engineering and Computer Science

National University of Sciences and Technology

Usman Khan, PhD

MOSFET Structure
2.1.2 MOSFET Structure
Figure 2.2 shows a simplified structure of an n-type MOS (NMOS) device. Fabricated on a p-type substrate
(also called the “bulk” or the “body”), the device consists of two heavily-doped n regions forming the
source and drain terminals, a heavily-doped (conductive) piece of polysilicon1 (simply called “poly”)
operating as the gate, and a thin layer of silicon dioxide (SiO2 ) (simply called “oxide”) insulating the gate
from the substrate. The useful action of the device occurs in the substrate region under the gate oxide.
Note that the structure is symmetric with respect to S and D.

G Poly D
S Oxide

W
tox

n+ n+
Leff

Ldrawn
p −substrate LD
Figure 2.2 Structure of a MOS device.

The lateral dimension of the gate along the source-drain path is called the length, L, and that perpen-
dicular to the length is called the width, W . Since the S/D junctions “side-diffuse” during fabrication, the
actual distance between the source and the drain is slightly less than L. To avoid confusion, we write,
L eff = L drawn − 2L D , where L eff is the “effective” length, L drawn is the total length,2 and L D is the amount
of side diffusion. As we will see later, L eff and the gate oxide thickness, tox , play an important role in the
performance of MOS circuits. Consequently, the principal thrust in MOS technology development is to
reduce both of these dimensions from one generation to the next without degrading other parameters of
◦
the device. Typical values at the time of this writing are L eff ≈ 10 nm and tox ≈ 15 A. In the remainder of
practiced in the problems at the end of the chapter.
We have thus far ignored the substrate on which the device is fabricated. In reality, the substrat
MOSFET Structure
potential greatly influences the device characteristics. That is, the MOSFET is a four-terminal device
Since in typical MOS operation, the S/D junction diodes must be reverse-biased, we assume that th
substrate of NMOS transistors is connected to the most negative supply in the system. For example, i
a circuit operates between zero and 1.2 volts, Vsub,NMOS = 0. The actual connection is usually provided
through an ohmic p + region, as depicted in the side view of the device in Fig. 2.3.

G
B S D

p+ n+ n+

p −substrate

Figure 2.3 Substrate connection.

In complementary MOS (CMOS) technologies, both NMOS and PMOS transistors are available. From
a simplistic viewpoint, the PMOS device is obtained by negating all of the doping types (including the
substrate) [Fig. 2.4(a)], but in practice, NMOS and PMOS devices must be fabricated on the same wafer
i.e., the same substrate. For this reason, one device type can be placed in a “local substrate,” usually called
a “well.” In today’s CMOS processes, the PMOS device is fabricated in an n-well [Fig. 2.4(b)]. Note tha
 MOSFET Structure
0 Chap. 2 Basic MOS Device Physics

G
B S D

n+ p+ p+

n−substrate

(a)
G G
B S D S D B

p+ n+ n+ p+ p+ n+

n −well
p −substrate

(b)
Figure 2.4 (a) Simple PMOS device; (b) PMOS inside an n-well.

NMOS PMOS NMOS PMOS NMOS PMOS

D S D S D D
MOSFET Structure
p+ n+ n+ p+ p+ n+

n −well
p −substrate

(b)
Figure 2.4 (a) Simple PMOS device; (b) PMOS inside an n-well.

NMOS PMOS NMOS PMOS NMOS PMOS

D S D S D D

G B G B G G G G

S D S D S S

(a) (b) (c)

Figure 2.5 MOS symbols.

2.2 MOS I/V Characteristics

In this section, we analyze the generation and transport of charge in MOSFETs as a function of the
terminal voltages. Our objective is to derive equations for the I/V characteristics such that we can elevate
 With L assumed constant, a saturated MOSFET can be used as a current source connected between the
drain and the source (Fig. 2.17), an important component in analog design. Note that the NMOS current
MOSFET Structure
source injects current into ground and the PMOS current source draws current from VD D . In other words,
only one terminal of each current source is “floating.” (It is difficult to design a current source that flows
between two arbitrary nodes of a circuit.)

▲ Example 2.2
On a VDS -VGS plane, show the regions of operation of an NMOS transistor.

VDS

Off Saturation
H
VT
−
S
VG
Triode

VTH VGS Figure 2.18 VDS -VGS plane showing

regions of operation.

Solution
Since the value of VDS with respect to VGS − VTH determines the region of operation, we draw the line VDS =
VGS − VTH in the plane, as shown in Fig. 2.18. If VGS > VTH , then the region above the line corresponds to satu-
ration, and that below the line corresponds to the triode region. Note that for a given VDS , the device eventually
leaves saturation as VGS increases. The minimum allowable VDS for operation in saturation is also called V D,sat .
It is important to bear in mind that V D,sat = VGS − VTH .
▲
Intrinsic Semiconductors
ID-VDS
Id(M2)
240µA

220µA

200µA

V1
M2 180µA

TestN 1
V2 160µA
1.4 .dc V1 0 0.7 0.01
140µA

120µA

100µA

.MODEL TestN NMOS (KP=90u VT0=0.7 LAMBDA=0.01) 80µA

60µA

40µA

20µA

0µA

-20µA
0.0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V
Intrinsic Semiconductors
ID-VDS
Id(M2)
240µA

210µA

V1
180µA
M2
TestN 1
V2
1.4 .dc V1 0 0.7 0.01 150µA

120µA

90µA

.MODEL TestN NMOS (KP=90u VT0=0.7 LAMBDA=0.01)

60µA

30µA

0µA

-30µA
0.0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V
Intrinsic Semiconductors

Id(M2)
ID-VGS
240µA

220µA

200µA

180µA
V1
M2
160µA
TestN 0.7
V2
1.4 .dc V2 0 1.4 0.01
140µA

120µA

100µA

.MODEL TestN NMOS (KP=90u VT0=0.7 LAMBDA=0.01)

80µA

60µA

40µA

20µA

0µA
0.0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 1.4V
 remains equal to I1 . In fact,
1.2weVcan=write
0.3 + 0.4 0.7 − V X 1 − 0.7
Second Order Effects1
I = µ C 1 n ox
W
(Vin − Vout − VTH )2 (2.26)
V X 1 = −8.83 V. For V X 1 < V X < 20, I D increases
L according to
q Body Effect
concluding $
that Vin − Vout is constant
1 W
!"
if I1 is constant [Fig. 2.25(b)].
" #%2
ID = µnVC
DDox
VGS − VT H 0 − γ 2" F − V X − 2" F
2
M1
L
Vin
b) shows the resulting behavior. Vin Vin
Vout Vout
Vout
I1
dy effect to manifest itself, the bulk potential, Vtsub , need not change:t if the sourc
ect to Vsub , the same (a) phenomenon occurs. (b) For example, consider (c) the circuit in F
Figure 2.25 (a) A circuit in which the source-bulk voltage varies with input level; (b) input and output voltages
body effect. Weeffect;
with no body note thatandasoutput
(c) input varies,
Vinvoltages with body closely follows the input because t
Vouteffect.
equal to INow
1 . In fact, we can write
suppose that the substrate is tied to ground and body effect is significant. Then, as V and hence
in
Vout become more positive, the potential difference between the source and the bulk increases, raising
1 that VW
the value of VTH . Equation (2.26) implies in − Vout must increase so as to 2maintain I D constant
[Fig. 2.25(c)]. I1 = µn Cox (Vin − Vout − VTH )
2 The changeLin the threshold voltage, e.g., as in Fig. 2.25(a), often
Body effect is usually undesirable.
complicates the design of analog (and even digital) circuits. Device technologists balance Nsub and Cox
ng thattoVobtain
in −aV out is constant
reasonable value for γ . if I1 is constant [Fig. 2.25(b)].

▲ Example 2.5
VDD
vi-3930640 book December 17, 201516:17 25

Second Order Effects

q Subthreshold Conduction
Sec. 2.3 Second-Order Effects 2

log I D
Exponential
1 decade

Square
Law

V TH Figure 2.28 MOS subthreshold char-

80 mV V GS acteristics.

they draw 18 mA when they are nominally off. Especially problematic in large circuits such as memories,
subthreshold conduction can result in significant power dissipation (or loss of analog information).
If a MOS device conducts for VGS < VTH , then how do we define the threshold voltage? Indeed,
numerous definitions have been proposed. One possibility is to extrapolate, on a logarithmic vertical
scale, the weak inversion and strong inversion characteristics and consider their intercept voltage as the
threshold (Fig. 2.28).
We now reexamine Eq. (2.19) for the transconductance of a MOS device operating in the subthresh-
old region. Is it possible to achieve an arbitrarily high transconductance by increasing W while main-
taining I D constant? Is it possible to obtain a higher transconductance than that of a bipolar transistor
(IC /VT ) biased at the same current? Equation (2.19) was derived from the square-law characteristic I D =
2
 Second Order Effects
q CMOS oxide breakdown
 Second Order Effects
q Punch through effect
MOS Device Layout

Sec. 2.4 MOS Device Models

Channel
Gate Area

W Contact
Windows

n+ n+ W Ldrawn

(a) (b)
Figure 2.29 Bird’s-eye and vertical views of a MOS device.

▲ Example 2.9
Draw the layout of the circuit shown in Fig. 2.30(a).

E Aluminum
E F
Wires
 ox
drain terminals (Fig. 2.34). This is because a change of "V in the gate voltage draws equal amounts
MOS Device Capacitance
harge from S and D. Thus, CGD = CGS = WLCox /2 + WCov .

2
WLCox + WCov
3
VD WLCox
C GS Saturation + WCov
2
Triode
WCov
Off CGD
VG

VTH VD + V TH VGS
Figure 2.34 Variation of gate-source and gate-drain capacitances versus VGS .

LetqusHomework:
now considerUnderstand
C G D and CGS2.34
. If in saturation, a MOSFET exhibits a gate-drain capacitance
ghly equal to WCov . As for CGS , we note that the potential difference between the gate and the
nnel varies from VGS at the source to VTH at the pinch-off point, resulting in a nonuniform vertical
tric field in the gate oxide as we travel from the source to the drain. It can be proved that the equivalent
acitance of this structure, excluding the gate-source overlap capacitance, equals (2/3)WLCox [1]. Thus,
= 2W L eff Cox /3 + WCov . The behavior of C G D and CGS in different regions of operation is plotted in
2.34. Note that the above equations do not provide a smooth transition from one region of operation
nother, creating convergence difficulties in simulation programs. This issue is revisited in Chapter 17.
 n+ p+ p+
NMOS vs PMOS
n−substrate

(a)
G G
B S D S D B

p+ n+ n+ p+ p+ n+

n −well
p −substrate

(b)
Figure 2.4 (a) Simple PMOS device; (b) PMOS inside an n-well.

q NMOS are superior

NMOS PMOS NMOS PMOS NMOS PMOS
D S D S D D
q Higher electron mobility (~ 2 times)
q Higher
G transconductance
B G B G G G G

q Higher gain
S D S D S S
q Should be preferred
(a) (b) (c)
Figure 2.5 MOS symbols.
 gate voltage, the current flows from one end of the fin to the other. The top view looks similar to that of
Fin FETa planar MOSFET [Fig. 2.42(b)].

Drain
Gate

Oxide
Source Drain
Gate
Length
Gate
HF

WF Source
Substrate

(a) (b)
Figure 2.42 (a) FinFET structure, and (b) top view.
q Advantage
As depicted in Fig. 2.42(a), the gate length can be readily identified, but how about the gate width?
q Low
We notearea:
that thehigh density
current flows on three facets of the fin. The equivalent channel width is therefore equal
to the sum of the fin’s width, W F , and twice its height, HF : W = W F + 2HF . Typically, W F ≈ 6 nm and
q Superior gate control
HF ≈ 50 nm.
q Since Hcurrent
Higher F is not under the circuit designer’s control, it appears that W F can be chosen so that W F +2H F
yields the desired transistor width. However, W F affects device imperfections such as source and drain
q series
Fasterresistance,
and lowchannel-length modulation, subthreshold conduction, etc. For this reason, the fin width
power consumption
is also fixed, dictating discrete values for the transistor width. For example, if W F + 2HF = 100 nm, then
q Lowtransistors
wider leakages can be obtained only by increasing the number of fins and only in 100-nm increments
 Sec. 2.6 Appendix B: Behavior of a MOS Device as a Capacitor
Fin FET
SF
Drain

Gate

Source
Figure 2.43 FinFET with multiple fins.

Figure 2.44 Layout of single- and

double-fin transistors.

2.6 Appendix B: Behavior of a MOS Device as a Capacitor

interface. We say that the MOSFET operates in the “accumulation” region. The two-terminal device c
MOSFET as a Capacitor
be viewed as a capacitor having a unit-area capacitance of Cox because the two “plates” of the capaci
are separated by tox .

VG < 0

640 book VG
December 17, 201516:17 38

+ + + + +
n+ + + + + n+

Figure 2.45 NMOS operating in

p −substrate Holes Chap. 2 Basic MOS Device Physics
accumulation mode.

C GS
As VGS rises, the density of holesStrong
Accumulation
at theInversion
interface falls, a depletion region begins to form under the oxid
and the device enters weak inversion. In this mode, the capacitance consists of the series combination
Cox and Cdep . Finally, as VGS exceeds VTH , the oxide-silicon interface sustains a channel and the unit-ar
capacitance returns to Cox . Figure 2.46 plots the behavior.
V TH V GS Figure 2.46 Capacitance-voltage
0 characteristic of an NMOS device.

References
q Homework: Understand 2.45 - 2.46
[1] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd ed. (New York: Wiley, 1986).
[2] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. (Boston: McGraw-Hill, 1999).
[3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices (New York: Cambridge University Press, 1998).
Homework

1. Read: Ch 2: Design of Analog CMOS Integrated Circuits, B. Razavi, 2nd Edition,

McGraw Hill.

2. Practice related examples and problems.