By Ms Payal Gupta

Chapter 5 & 6-CS

Processor Fundamentals
Central Processing Unit (CPU) Architecture
 Von Neumann model

o Von Neumann realized data & programs are indistinguishable and can, therefore, use the

same memory.

o Von Neumann's architecture uses a single processor.

o It follows a linear sequence of fetch–decode–execute operations for the set of instructions,

i.e. the program.

o To do this, the processor uses registers.

 Registers: smallest unit of storage of microprocessor; allows fast data transfer between other

registers

 General Purpose registers

o Used to temporarily store data values which have been read from memory or some

processed result

o Assembly language instructions can use it

 Special Purpose Registers

o Some are accessible by assembly language instructions

o Only holds either data or memory location, not both

o Particular purpose registers include:

 Program Counter (PC): holds the address of the next instruction to be fetched

 Memory Data Register (MDR): holds data value fetched from memory

 Memory Address Register (MAR): Holds the address of the memory cell of the program

which is to be accessed

 Accumulator (ACC): holds all values that are processed by arithmetic & logical operations.

 Index Register (IX): Stores a number used to change an address value

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 Current Instruction Register (CIR): Once program instruction is fetched, it is stored in CIR

and allows the processor to decode & execute it

 Status Register: holds results of comparisons to decide later for action, intermediate and

erroneous results of arithmetic performed

 The Processor (CPU)

o Arithmetic and Logic Unit (ALU): part of the processor that processes instructions which

require some form of arithmetic or logical operation

o Control Unit (CU): part of the CPU that fetches instructions from memory, decodes them &

synchronizes operations before sending signals to the computer’s memory, ALU and I/O

devices to direct how to respond to instructions sent to the processor

o Immediate Access Store (IAS): memory unit that the processor can directly access

o System Clock: a timing device connected to a processor that synchronises all components.

 Buses

o set of parallel wires that allow the transfer of data between components in a computer

system

 Data bus: bidirectional bus that carries data instructions between processor, memory, and

I/O devices.

 Address bus: unidirectional bus that carries the address of the main memory location or

input/output device about to be used, from processor to memory address register (MAR)

o Control bus

 Bidirectional

 used to transmit control signals from the control unit to ensure access/use of data & address

buses by components of the system does not lead to conflict

 Performance of Computer System Factors

o Clock Speed

 number of pulses the clock sends out in a given time interval, which determines the number

of cycles (processes) the CPU executes in a given time interval

 usually measured in Gigahertz (GHz)

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 If the clock speed is increased, then the execution time for instructions decreases. Hence,

more cycles per unit time, which increases performance.

 However, there is a limit on clock speed since the heat generated by higher clock speeds

cannot be removed fast enough, which leads to overheating.

o Bus Width

 Determines the number of bits that can be simultaneously transferred

 Refers to the number of lines in a bus

 Increasing bus width increases the number of bits transferred simultaneously, increasing

processing speed and performance.

o Cache Memory

 Commonly used instructions are stored in the cache memory area of the CPU.

 If the cache memory size is increased, more commonly executed instructions can be stored,

and the need for the CPU to wait for instructions to be loaded reduces. Hence, the CPU

executes more cycles per unit of time, thus improving performance.

o Number of Cores

 Most CPU chips are multi-core — have more than one core (essentially a processor)

 Each core simultaneously processes different instructions through multithreading, improving

computer performance.

 Ports

o Hardware which provides a physical interface between a device with CPU and a peripheral

device

o Peripheral (I/O) devices cannot be directly connected to the CPU, hence connected through

ports.

o Universal Serial Bus (USB): Can connect both input and output devices to the processor

through a USB port.

o High Definition Multimedia Interface (HDMI)

 Can only connect output devices (e.g. LCD) to the processor through a HDMI port
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 HDMI cables transmit high-bandwidth and high-resolution video & audio streams through

HDMI ports

o Video Graphics Array (VGA)

 Can only connect output devices (e.g. second monitor/display) to the processor through a

VGA port

 VGA ports allow only the transmission of video streams but not audio components

 Fetch-Execute (F-E) cycle

o Fetch stage

 PC holds the address of the next instruction to be fetched

 The address on the PC is copied to MAR

 PC is incremented

 Instruction loaded to MDR from the address held in MAR

 Instruction from MDR loaded to CIR

o Decode stage: The opcode and operand parts of instruction are identified

o Execute stage: Instructions executed by the control unit sending control signals

o Register Transfer Notation (RTN)

 MAR ← [PC]

 PC ← [PC] + 1

 MDR ← [[MAR]]

 CIR ← [MDR]

 Decode

 Execute

 Return to start

 Square brackets: value currently in that register

 Double square brackets: CPU is getting value stored at the address in the register

 Interrupts

o A signal from a program seeking the processor’s attention

o Interrupt Service Routine (ISR):

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 Handles the interrupt by controlling the processor

 Different ISRs used for different sources of interrupt

 A typical sequence of actions when an interrupt occurs:

o The processor checks the interrupt register for interrupt at the end of the F-E cycle for the

current instruction

o If the interrupt flag is set in the interrupt register, the interrupt source is detected

o If the interrupt is low priority, then an interrupt is disabled

o If interrupting is a high priority:

 All contents of registers of the running process are saved on the stack

 PC is loaded with the ISR and is executed

 Once ISR is completed, the processor restores the registers’ contents from the stack, and

the interrupted program continues its execution.

 Interrupts re-enabled and

 Return to the start of the cycle

Assembly Language
 Assembly language: low-level programming language with instructions made up of an op

code and an operand

 Machine code: code written in binary that uses the processor’s basic machine operations

 Relationship between machine and assembly language: every assembly language

instruction (source code) translates into exactly one machine code instruction (object code)

 Symbolic addressing

o Symbols used to represent operation codes

o Labels can be used for addresses

 Absolute addressing: a fixed address in memory

 Assembler

o Software that changes assembly language into machine code for the processor to

understand
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o The assembler replaces all mnemonics and labels with their respective binary values (that

are predefined before by the assembler software)

 One pass assembler

o Assembler converts mnemonic source code into machine code in one sweep of program

o Cannot handle code that involves forward referencing

 Two pass assembler: software makes 2 passes thru code

o On the first pass:

 Symbol table created to enter symbolic addresses and labels into specific addresses

 All errors are suppressed

o On the second pass:

 Jump instructions access memory addresses via table

 Whole source code translates into machine code

o Error reported if they exist

 Grouping the Processor’s Instruction Set

Op Code Operand Explanation

Addressing

LDM #n Immediate: Load n into ACC

LDD Direct: load contents at address into the ACC

Indirect: load contents of address at given address

LDI
into ACC

Indexed: load contents of given address + IR into

LDX
ACC

Data Movement

STO Store contents of ACC into address

Arithmetic
Operations
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Op Code Operand Explanation

ADD Add contents of register to ACC

INC Add 1 to contents of the register

Comparing

Compare contents of ACC with that of given

CMP
address

CMP #n Compare contents of ACC with n

Conditional Jumps

JPE Jump to address if compare TRUE

JPN Jump to address if compare FALSE

Unconditional
Jumps

JMP Jump to given address

I/O Data

IN Input any character and store ASCII value in ACC

Output character whose ASCII value is stored in

OUT
ACC

Ending

END Return Control to operating system

#denotes immediate addressing

B denotes a binary number, e.g. B01001010 & denotes a hexadecimal number, e.g.

&4A

 Modes of Addressing

o Direct Addressing: loads contents at address into ACC

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o Indirect Addressing: The address to be used is at given address. Load contents of this

second address to ACC

o Indexed addressing: form the address to be used as

+ the contents of the IR (Index Register)

o Relative addressing: next instruction to be carried out is an offset number of locations away,

relative to address of current instruction held in PC; allows for relocatable code

o Conditional jump: has a condition that will be checked (like using an IF statements)

o Unconditional jump: no condition to be followed, simply jump to the next instruction as

specified

Bit Manipulation
 Binary numbers can be multiplied or divided by shifting

 Left shift (LSL #n)

o Bits are shifted to the left to multiply

o E.g. to multiply by four, all digits shift two places to left

 Right shift (LSR #n)

o Bits are shifted to the right to divide

o E.g. to divide by four, all digits shift two places to right

 Logical shift: zeros replace the vacated bit position

 Arithmetic shift: Used to carry out multiplication and division of signed integers represented

by bits in the accumulator by ensuring that the sign-bit (usually the MSB) is the same after

the shift.

 Cyclic shift: the bit that is removed from one end by the shift is added to the other end.

 Bit Masking
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o Each bit can represent an individual flag.

o ∴ by altering the bits, flags could be operated upon.

o Bit manipulation operations:

 Masking: an operation that defines which bits you want to keep and which bits you want to

clear.

 Masking to 1: The OR operation is used with a 1.

 Masking to 0: The AND operation is used with a 0.

 Matching: an operation that allows the accumulator to compare the value it contains to the

given value in order to change the state of the status register.

 Practical applications of Bit Masking:

o Setting an individual bit position:

 Mask the content of the register with a mask pattern which has 0 in the ‘mask out’ positions

and 1 in the ‘retain’ positions.

 Set the result with the match pattern by using the AND command with a direct address.

o Testing one or more bits:

 Mask the content of the register with a mask pattern which has 0 in the ‘mask out’ positions

and 1 in the ‘retain’ positions.

 Compare the result with the match pattern by using the CMP command or by “Checking the

pattern”.

o Checking the pattern

 Use AND operation to mask bits and obtain resultant.

 Now subtract matching bit pattern from resultant.

 The final ‘non-zero’ result confirms the patterns are not the same else vice versa.