Computer Organization

and Architecture (COA)

By- DR. Shikha tayal aeron
Contents
• Introduction to Subject
• Why to study this subject?
Learning Outcomes
• Student will familiarize with the curriculum of the subject
• Student will familiarize with basic introduction of the subject
• Student will able to understand the importance of the Subject
Links of Text Books
• Text Book1
• Text Book2
• Text Book3
Computer Organization and Architecture (COA)
Computer Architecture Computer Organization

• Instruction • I/O Mechanism and interface

• Addressing Modes • Memory Organization
• ALU
• Pipeline

(Internal Design)
WHY COA??
Computer Architecture helps us
• to understand the functionalities of a system
• how exactly all the units in the system are arranged and
interconnected.
• A programmer can view architecture in terms of instructions,
addressing modes and registers.
Objectives of Studying COA
• To know the background of internal communication of computer
• To have better idea on how to write assemble language programs
• To be clear with memory management techniques
• To better with IO devices communication with processor
• To notice how to perform computer arithmetic operations
• To be clear with pipeline
Unit 1- Functional Blocks of a Computer

• CPU, Memory, Input-Output Subsystems.

• Instruction Set Architecture of a CPU – Registers, Instruction
Execution Cycle,
• RTL Representation and Interpretation of Instructions,
• Addressing Modes,
• Instruction Set.
• Case Study – Instruction Sets of Some Common CPUs, RISC and CISC
Architecture.
Components that aids the working-cycle of a computer i.e. the Input- Process-
Output Cycle are called as the functional components/ Blocks of a computer.
• Input Unit: The input unit consists of input devices that are attached to
the computer. These devices take input and convert it into binary
language that the computer understands. Some of the common input
devices are keyboard, mouse, joystick, scanner etc.

• Output Unit: The output unit consists of output devices that are
attached with the computer. It converts the binary data coming from
CPU to human understandable form. The common output devices are
monitor, printer, plotter etc.
Memory :

• Memory attached to the CPU is used for storage of data and

instructions and is called internal memory.
• The internal memory is divided into many storage locations, each
of which can store data or instructions.
• The internal memory is also called the Primary memory or
Main memory. This memory is also called as RAM, i.e., Random
Access Memory.
• Each memory location is of the same size and has an address.
Control Unit:
• The Control unit coordinates and controls the data flow in and out of
CPU.
▪controls all the operations of ALU, memory registers and also
input/output units.
▪It is also responsible for carrying out all the instructions stored in the
program.
▪It decodes the fetched instruction, interprets it and sends control signals
to input/output devices until the required operation is done properly by
ALU and memory.
CPU Registers
• Registers are very fast computer memory which are used to
execute programs and operations efficiently.
• there are several different classes of CPU registers which
works in coordination with the computer memory to run
operations efficiently.
• For even better processing, there are memories in CPU which
can get data from RAM which are about to be executed
beforehand.
 CPU Registers
• Accumulator:
This is the most frequently used register used to store data taken
from memory. It is in different numbers in different microprocessors.

• Memory Address Registers (MAR):

It holds the address of the location to be accessed from memory.
MAR and MDR (Memory Data Register) together facilitate the
communication of the CPU and the main memory.

• Memory Data Registers (MDR):

It contains data to be written into or to be read out from the
addressed location.
• Program Counter (PC):
Program Counter (PC) is used to keep the track of execution of the
program.
• It contains the memory address of the next instruction to be
fetched.
• Program Counter (PC) also functions to count the number of
instructions.
• The incrementation of PC depends on the type of architecture being
used. If we are using 32-bit architecture, the PC gets incremented by 4
every time to fetch the next instruction.

• Instruction Register (IR):

The IR holds the instruction which is just about to be executed. The
instruction from PC is fetched and stored in IR. As soon as the
instruction in placed in IR, the CPU starts executing the instruction and
the PC points to the next instruction to be executed.
• General Purpose Registers:

These are numbered as R0, R1, R2….Rn-1, and used to store temporary data during any ongoing operation. Its
content can be accessed by assembly programming. Modern CPU architectures tends to use more GPR so that
register-to-register addressing can be used more, which is comparatively faster than other addressing modes.

• Condition code register ( CCR )/ PSR):

Condition code registers contain different flags that indicate the status of any operation. for instance
lets suppose an operation caused creation of a negative result or zero, then these flags are set high
accordingly and the flags are

1. Carry C: Set to 1 if an add operation produces a carry or a subtract operation produces a borrow; otherwise
cleared to 0.
2. Overflow V: Useful only during operations on signed integers.
3. Zero Z: Set to 1 if the result is 0, otherwise cleared to 0.
4. Negate N: Meaningful only in signed number operations. Set to 1 if a negative result is produced.
5. Extend X: Functions as a carry for multiple precision arithmetic operations.
These are generally decided by ALU.
Advantages
1.Fast access: Since the registers are located inside the processor,
they can be accessed quickly without having to wait for data to
be fetched from memory.
2.Reduced memory access: The use of registers can help reduce the
number of memory accesses required, which can improve the
overall performance of the system.
3.Specialized functionality: Each register has a specific function, such
as the accumulator for arithmetic operations and the program
counter for storing the address of the next instruction. This
specialized functionality can make programming and debugging
easier.
4.Reduced complexity: By providing dedicated registers for specific
purposes, reduces the complexity of the programming and
execution process.
The Instruction Set Architecture (ISA) of a CPU is a set of rules that
defines the software interface between the hardware and the
software.

It serves as a bridge between the low-level machine code instructions

executed by the CPU and the high-level programming languages used
by software developers.

The ISA specifies-

❑ the instructions that a CPU can execute,
❑ the format of these instructions, and
❑ the way in which they manipulate data.
key components of an Instruction Set
Architecture:
1. Instructions:
• Operations: The set of operations or instructions that the CPU can
perform. This includes arithmetic operations (add, subtract, multiply,
divide), logic operations (AND, OR, XOR), data movement (load,
store), and control transfer (branch, jump) instructions.
• Instruction Format: The format in which instructions are encoded.
This includes –
the number of operands,
the size of each operand, and
the opcode that specifies the operation.
 OPERANDS
An operand is a value or a variable upon which an operation is performed.
In the context of an instruction in a computer program, an operand can take several
forms:
1.Immediate Operand: A constant value or data that is directly specified within
the instruction. For example, in the instruction "ADD R1, 5," the immediate
operand is the value 5.
2.Register Operand: The content of a register that is specified as part of the
instruction. For instance, in the instruction "ADD R1, R2," both R1 and R2 are
register operands.
3.Memory Operand: An address pointing to a location in the computer's memory
where the data is stored. The instruction might involve loading data from or
storing data to a specific memory location. For example, in the instruction "LOAD
R1, [0x1000]," the memory operand is the address 0x1000.
2. Registers:
• Data Registers: These are used to store data that the CPU is actively
working on. Common registers include –
general-purpose registers, which can be used for various purposes,
special-purpose registers, such as program counter (PC) and
instruction register (IR).

• Address Registers: If present, these registers store memory addresses.

3. Memory Addressing Modes:
• Direct Addressing: The operand is specified by an explicit memory
address.

• Register Indirect Addressing: The operand is located in a register

whose address is part of the instruction.

• Immediate Addressing: The operand is a constant value included in the

instruction.
4. Data Types:
• Integer Data Types: The size and representation of integer data (e.g.,
8-bit, 16-bit, 32-bit, 64-bit integers).

• Floating-Point Data Types: If supported, the format and operations for

floating-point numbers.
5. Control Flow:
1. Branching and Jumping: Mechanisms for altering the flow of control in a
program, including conditional branches, unconditional jumps, and subroutine
calls.

6. I/O Instructions:
1. If applicable, instructions for input/output operations.

7. Exception Handling:
1. Mechanisms for handling exceptions, interrupts, and other abnormal conditions.
 Importance Of Instruction Set
Architecture ( ISA )
Defining The Compatibility And Portability
• It ensures that software written for a particular ISA can run on any microprocessor
that implements that ISA.
• This compatibility allows software developers to write applications that can be executed
on a wide range of microprocessors without requiring significant modifications or
recompilation.

Software Development
• The ISA defines the available instructions, addressing modes, and data types that
programmers can use to write software.
• It provides a high- level abstraction of the underlying hardware, allowing developers to
focus on writing efficient and optimized code without needing to understand the
intricacies of the microprocessor’s internal design.
Performance Optimization
• The ISA influences the performance of the microprocessor. The selection and design of instructions impact the execution
speed, code density, and efficiency of the processor.
• By carefully designing the ISA, microprocessor architects can optimize instruction execution and memory access,
leading to better performance in terms of speed and power consumption.

Compiler Design
• Compilers translate high-level programming languages into machine code that can be executed by the microprocessor.
• By understanding the ISA, compiler designers can develop optimization techniques and code generation strategies
that exploit the microprocessor’s features, improving the performance of the generated code.

Hardware Design
• The ISA serves as a blueprint for microprocessor designers to implement the hardware architecture.
• Hardware designers use the ISA as a reference to ensure compatibility, develop efficient pipelining and caching
strategies, and optimize the microarchitecture for improved performance and power efficiency.
System Bus in Computer Architecture

• A bus is a set of electrical wires (lines) that connects the various

hardware components of a computer system.
• It works as a communication pathway through which information
flows from one hardware component to the other hardware
component.
What Is A System Bus?
A bus that connects major components (CPU, memory and I/O
devices) of a computer system is called as a System Bus.
Components Of A System Bus
 1) Data Bus
• Data bus is used for transmitting the data / instruction from CPU to memory/IO and
vice-versa.
• It is bi-directional.
• The width of a data bus refers to the number of bits (electrical wires) that the bus
can carry at a time. Each line carries 1 bit at a time. So, the number of lines in data bus
determine how many bits can be transferred parallelly or at one time.
• The wider the bus width, faster would be the data flow on the data bus and thus
better would be the system performance.

Examples-
• A 32-bit bus has thirty two (32) wires and thus can transmit
32 bits of data at a time.
• A 64-bit bus has sixty four (64) wires and thus can transmit
64 bits of data at a time.
2) Control Bus
• control bus is used to transfer the control and timing signals from
one component to the other component.
• The CPU uses control bus to communicate with the devices that are
connected to the computer system.
• The CPU transmits different types of control signals to the system
components.
• It is bi-directional.
• Control signals are generated in the control unit of CPU.
• Timing signals are used to synchronize the memory and I/O
operations with a CPU clock.
 Typical control signals hold by control bus
• Memory read – Data from memory address location to be placed on data bus.
• Memory write – Data from data bus to be placed on memory address location.
• I/O Read – Data from I/O address location to be placed on data bus.
• I/O Write – Data from data bus to be placed on I/O address location.

• Other control signals hold by control bus are interrupt, interrupt acknowledge,
bus request, bus grant and several others.
• The type of action taking place on the system bus is indicated by these control
signals.

Example-
• When CPU wants to read or write data, it sends the memory read or memory
write control signal on the control bus to perform the memory read or write
operation from the main memory. Similarly, when the processor wants to read
from an I/O device, it generates the I/O read signal.
3) Address Bus

• Address bus is used to carry address from CPU to memory/IO devices.

• It is used to identify the particular location in memory.
• It carries the source or destination address of data i.e. where to store or from where to
retrieve the data.
• It is uni-directional.

Example-

• When CPU wants to read or write data, it sends the memory read or memory write control
signal on the control bus to perform the memory read or write operation from the main
memory and the address of the memory location is sent on the address bus.
• If CPU wants to read data stored at the memory location (address) 4, the CPU send the
value 4 in binary on the address bus.
• The width of address bus determines the amount of physical memory
addressable by the processor.
• It determines the size of the memory that the computer can use.
• The wider is the address bus, the more memory a computer will be able to
use.
• The addressing capacity of the system can be increased by adding more
address lines.

EXAMPLE
• An address bus that consists of 16 wires can convey 216 (= 64K) different
addresses.
• An address bus that consists of 32 wires can convey 232 (= 4G) different
addresses.
Q-1 Which of the following system bus is used to designate the source or destination of
the data on the bus itself?
• Control bus
• Data bus
• Address bus

Q-2 The bus which is used to transfer data from main memory to peripheral device is-
• Data bus
• Output bus
• Control bus
• Address bus
Q3- How many memory locations a system with a 32-bit address bus can address?

• 28
• 216
• 232
• 32

Q4- How many bits can be transmitted at a time using a bus with 32 data lines?
• 8 bits
• 16 bits
• 32 bits
• 232 bits
Q5- A microprocessor has a data bus with 64 lines and an address bus with 32 lines.
The maximum number of bits that can be stored in memory is-
• 32 x 232
• 32 x 264
• 64 x 232
• 64 x 264

Q6- The address bus with a ROM of size 1024 x 8 bits is-
• 8 bits
• 10 bits
• 12 bits
• 16 bits
Q-7 The data bus width of a ROM of size 2048 x 8 bits is-
• 8
• 10
• 12
• 16
 Instruction Execution Cycle
• A program residing in the memory unit of the computer consists of a sequence of
instructions. The program is executed in the computer by going through a cycle for each
instruction.
• Each instruction cycle in turn is subdivided into a sequence of sub cycles or phases. In the basic
computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
• Upon completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next
instruction. This process continues indefinitely unless a HALT instruction is encountered.
The Instruction Execution Cycle, also known as the
machine cycle or instruction cycle, is the process by
which a computer processes a single instruction. It
consists of a sequence of steps that the central
processing unit (CPU) performs to fetch, decode,
execute, and store results for an instruction. The cycle is
repeated for each instruction in a program.
1.Fetch:
1. The CPU fetches the instruction from memory. The address of the instruction is typically
stored in the MAR and program counter (PC) contains address of next instruction to be
executed.
2. After each fetch cycle, the program counter is incremented to point to the next
instruction in memory.
2.Decode:
1. The fetched instruction is decoded to determine what operation needs to be performed
and what operands are involved.
2. The control unit extracts the opcode (operation code) from the instruction, which specifies
the operation to be performed.
3.Execute:
1. The CPU performs the operation specified by the opcode on the data operands. This may
involve arithmetic or logical operations, data transfers, or control transfers.
2. The result of the operation is stored in registers or memory.
4.Write back:
1. If the result of the execution is to be stored, it is written back to a register or memory
location.
2. The status flags in the CPU may also be updated based on the result.
• Timing signals play a crucial role in coordinating the various stages of
the instruction execution cycle within a computer's central processing
unit (CPU).
• These signals ensure that each stage occurs at the right time and in
the correct sequence.
Instruction execution cycle with associated
timing and control signals:
1. Fetch Stage:
Timing Signal: T0 and T1, Control Signal: Memory Read (MAR)
• At T0:
• The program counter (PC) holds the memory address of the FIRST instruction of
the program.
• The Memory Address Register (MAR) is loaded with the contents of the PC.
• The Memory Read (MREQ) signal is activated to request the instruction from
memory.
• At T1:
• The Instruction Register (IR) is loaded with the instruction fetched from memory.
• The PC is incremented to prepare for the next instruction.
2. Decode Stage:
Timing Signal: T2 Instruction Decode (ID)
• The instruction in the IR is decoded.
• The opcode IR (12-14) is extracted to determine the type of operation
to be performed.
• Operand addresses IR (0-11) moves to MAR
• Indirect bit IR(15) transferred to flip flop I
Execute Stage:

Timing Signal: T3 ALU (Arithmetic Logic Unit) Operation (ALUOP)

• The ALU performs the operation specified by the opcode on the
operands.
• The result is produced by the ALU.
• Data movement operations involve activating specific signals such as
Memory Write (MWR) or Register Transfer (REG).
Write Back Stage:

Timing Signal: T4 Register Write (REGW) or Memory Write (MWR)

• The result is written back to a register or memory location.
• Status flags in the CPU may be updated based on the result.
• The process is completed, and the CPU is ready for the next
instruction.
Register Transfer Language
 Register Transfer & -operations 61 Register Transfer Language

MICROOPERATIONS (1)

• The operations on the data in registers are called

microoperations.
• The functions built into registers are examples of
microoperations
– Shift
– Load
– Clear
– Increment
– …

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 Register Transfer & -operations 62 Register Transfer Language

MICROOPERATION (2)

An elementary operation performed (during

one clock pulse), on the information stored
in one or more registers

Registers ALU 1 clock cycle

(R) (f)

R  f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
Computer Organization Computer Architecture
 Register Transfer & -operations 63 Register Transfer Language

REGISTER TRANSFER LANGUAGE

• Rather than specifying a digital system in words, a specific

notation is used, register transfer language

• For any function of the computer, the register transfer

language can be used to describe the (sequence of)
microoperations

• Register transfer language

– A symbolic language
– A convenient tool for describing the internal organization of digital
computers
– Can also be used to facilitate the design process of digital systems.

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 Register Transfer & -operations 64 Register Transfer Language

DESIGNATION OF REGISTERS

• Registers are designated by capital letters, sometimes

followed by numbers (e.g., A, R13, IR)
• Often the names indicate function:
– MAR - memory address register
– PC - program counter
– IR - instruction register

• Registers and their contents can be viewed and represented in

various ways
– A register can be viewed as a single entity:

MAR

– Registers may also be represented showing the bits of data they contain

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 Register Transfer & -operations 65 Register Transfer Language

DESIGNATION OF REGISTERS

• Designation of a register
- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields

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 Register Transfer & -operations 66 Register Transfer

REGISTER TRANSFER

• Copying the contents of one register to another is a register

transfer

• A register transfer is indicated as

R2  R1

– In this case the contents of register R2 are copied (loaded) into

register R1
– A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R1 are not
altered by copying (loading) them to R2

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 Register Transfer & -operations 67 Register Transfer

REGISTER TRANSFER

• A register transfer such as

R3  R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination
register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

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 Register Transfer & -operations 68 Register Transfer

CONTROL FUNCTIONS
• Often actions need to only occur if a certain condition is true
• This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal, called
a control function
– If the signal is 1, the action takes place
• This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register R1 into

register R2”, i.e., if (P = 1) then (R2  R1)

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 Register Transfer & -operations 69 Register Transfer

HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2  R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops

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 Register Transfer & -operations 70 Register Transfer

SIMULTANEOUS OPERATIONS

• If two or more operations are to occur

simultaneously, they are separated with commas

P: R3  R5, MAR  IR

• Here, if the control function P = 1, load the contents

of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR

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 Register Transfer & -operations 71 Register Transfer

BASIC SYMBOLS FOR REGISTER TRANSFERS

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2  R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A

Computer Organization Computer Architecture

 Register Transfer & -operations 72 Bus and Memory Transfers

BUS TRANSFER IN RTL

• Depending on whether the bus is to be mentioned

explicitly or not, register transfer can be indicated as
either
R2  R1
or
BUS  R1, R2  BUS

• In the former case the bus is implicit, but in the latter, it is

explicitly indicated

Computer Organization Computer Architecture

 Register Transfer & -operations 73 Bus and Memory Transfers

MEMORY TRANSFER
• Collectively, the memory is viewed at the register level as
a device, M.
• Since it contains multiple locations, we must specify
which address in memory we will be using
• This is done by indexing memory references

• Memory is usually accessed in computer systems by

putting the desired address in a special register, the
Memory Address Register (MAR, or AR)
• When memory is accessed, the contents of the MAR get
sent to the memory unit’s address lines

M
Memory Read
AR
unit Write

Data out Data in

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 Register Transfer & -operations 74 Bus and Memory Transfers

MEMORY READ

• To read a value from a location in memory and load it into

a register, the register transfer language notation looks
like this:
R1  M[MAR]

• This causes the following to occur

– The contents of the MAR get sent to the memory address lines
– A Read (= 1) gets sent to the memory unit
– The contents of the specified address are put on the memory’s
output data lines
– These get sent over the bus to be loaded into register R1

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 Register Transfer & -operations 75 Bus and Memory Transfers

MEMORY WRITE

• To write a value from a register to a location in memory

looks like this in register transfer language:

M[MAR]  R1

• This causes the following to occur

– The contents of the MAR get sent to the memory address lines
– A Write (= 1) gets sent to the memory unit
– The values in register R1 get sent over the bus to the data input lines
of the memory
– The values get loaded into the specified address in the memory

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 Register Transfer & -operations 76 Bus and Memory Transfers

SUMMARY OF R. TRANSFER MICROOPERATIONS

A B Transfer content of reg. B into reg. A

AR  DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A  constant Transfer a binary constant into reg. A
ABUS  R1, Transfer content of R1 into bus A and, at the same time,
R2  ABUS transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR  M Memory read operation: transfers content of
memory word specified by AR into DR
M  DR Memory write operation: transfers content of
DR into memory word specified by AR

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 Register Transfer & -operations 77 Arithmetic Microoperations

MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations
- Logic microoperations
- Shift microoperations

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 Register Transfer & -operations 78 Arithmetic Microoperations

ARITHMETIC MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement

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 Register Transfer & -operations 79 Arithmetic Microoperations

BINARY ADDER / SUBTRACTOR / INCREMENTER

B3 A3 B2 A2 B1 A1 B0 A0
Binary Adder
FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

Binary Incrementer A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

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 Register Transfer & -operations 80 Arithmetic Microoperations

ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 FA D3
S0
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1

S1 S0 Cin Y Output Microoperation

0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
Computer Organization Computer Architecture
 Register Transfer & -operations 81 Logic Microoperations

LOGIC MICROOPERATIONS
• Specify binary operations on the strings of bits in registers
– Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value
• There are, in principle, 16 different logic functions that can
be defined over two binary input variables
A B F0 F1 F2 … F13 F14 F15
0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

• However, most systems only implement four of these

– AND (), OR (), XOR (), Complement/NOT
• The others can be created from combination of these

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 Register Transfer & -operations 82 Logic Microoperations

LIST OF LOGIC MICROOPERATIONS

• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
n
- n binary vars → 2 2 functions

• Truth tables for 16 functions of 2 variables and the

corresponding 16 logic micro-operations
x 0011 Boolean Micro-
Name
y 0101 Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy FAB AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F  (A  B)’ NOR
1001 F9 = (x  y)' F  (A  B)’ Exclusive-NOR
1010 F10 = y' F  B’ Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F  A’ Complement A
1101 F13 = x' + y F  A’ B
1110 F14 = (xy)' F  (A  B)’ NAND
1111 F15 = 1 F  all 1's Set to all 1's

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 Register Transfer & -operations 83 Logic Microoperations

HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS

Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F=AB OR
1 0 F=AB XOR
1 1 F = A’ Complement

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 Register Transfer & -operations 84 Logic Microoperations

APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic microoperations can be used to manipulate individual
bits or a portions of a word in a register

• Consider the data in a register A. In another register, B, is bit

data that will be used to modify the contents of A

– Selective-set AA+B
– Selective-complement AAB
– Selective-clear A  A • B’
– Mask (Delete) AA•B
– Clear AAB
– Insert A  (A • B) + C
– Compare AAB
– ...

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 Register Transfer & -operations 85 Logic Microoperations

SELECTIVE SET

• In a selective set operation, the bit pattern in B is used to set

certain bits in A

1100 At
1010 B
1110 At+1 (A  A + B)

• If a bit in B is set to 1, that same position in A gets set to 1,

otherwise that bit in A keeps its previous value

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 Register Transfer & -operations 86 Logic Microoperations

SELECTIVE COMPLEMENT

• In a selective complement operation, the bit pattern in B is

used to complement certain bits in A

1100 At
1010 B
0110 At+1 (A  A  B)

• If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it is
unchanged

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 Register Transfer & -operations 87 Logic Microoperations

SELECTIVE CLEAR

• In a selective clear operation, the bit pattern in B is used to

clear certain bits in A

1100 At
1010 B
0100 At+1 (A  A  B’)

• If a bit in B is set to 1, that same position in A gets set to 0,

otherwise it is unchanged

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 Register Transfer & -operations 88 Logic Microoperations

MASK OPERATION

• In a mask operation, the bit pattern in B is used to clear

certain bits in A

1100 At
1010 B
1000 At+1 (A  A  B)

• If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged

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 Register Transfer & -operations 89 Logic Microoperations

CLEAR OPERATION

• In a clear operation, if the bits in the same position in A and

B are the same, they are cleared in A, otherwise they are set
in A

1100 At
1010 B
0110 At+1 (A  A  B)

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 Register Transfer & -operations 90 Logic Microoperations

INSERT OPERATION
• An insert operation is used to introduce a specific bit pattern
into A register, leaving the other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired
positions
– Example
» Suppose you wanted to introduce 1010 into the low order
four bits of A: 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

» 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)

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 Register Transfer & -operations 91 Shift Microoperations

SHIFT MICROOPERATIONS
• There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• What differentiates them is the information that goes into
the serial input

• A right shift operation

Serial
input

• A left shift operation Serial

input

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 Register Transfer & -operations 92 Shift Microoperations

LOGICAL SHIFT
• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

0

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation is used

– shl for a logical shift left
– shr for a logical shift right
– Examples:
» R2  shr R2
» R3  shl R3

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 Register Transfer & -operations 93 Shift Microoperations

CIRCULAR SHIFT
• In a circular shift the serial input is the bit that is shifted out of
the other end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
» R2  cir R2
» R3  cil R3

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 Register Transfer & -operations 94 Shift Microoperations

ARITHMETIC SHIFT
• An arithmetic shift is meant for signed binary numbers
(integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep
the sign of the number the same as it performs the
multiplication or division

• A right arithmetic shift operation:

sign
bit

• A left arithmetic shift operation:

0
sign
bit

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 Register Transfer & -operations 95 Shift Microoperations

ARITHMETIC SHIFT
• An left arithmetic shift operation must be checked for the
overflow
0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2  ashr R2
» R3  ashl R3

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 Register Transfer & -operations 96 Shift Microoperations

HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS

0 for shift right (down)

Serial Select 1 for shift left (up)
input (IR)

S
MUX H0
0
1
A0

A1 S
MUX H1
0
A2 1

A3
S
MUX H2
0
1

S
MUX H3
0
1

Serial
input (IL)

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 97

Common Bus System using multiplexers

• A typical computer has many registers and we need to transfer the information
between these registers. A way to transfer the information is using the common
bus system.
• The construction of this bus system for 4 registers (4 bits) : The bus consists of
4×1 multiplexers with 4 inputs and 1 output and 4 registers with bits numbered
0 to 3. There are 2 select inputs S0 and S1 which are connected to the select
inputs of the multiplexers.
• No. of multiplexers needed
= No. of bits in each register

Computer Organization Computer Architecture

 98

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 99

Microinstruction and its format

• Microinstruction is a low-level instruction that controls the basic
operations of CPU. It's essentially a step-by-step guide for the CPU to
perform a specific function.

• Purpose:
–Microinstructions translate machine instructions (complex
instructions understood by the CPU) into even smaller, simpler
operations that the CPU's hardware can directly execute.
–They act as an intermediate layer between machine code and the
hardware circuitry, providing more granular control over the internal
operations.

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 100

FORMAT OF MICROINSTRUCTION

• A microinstruction format includes 20 bits in total. They are divided

into four elements as displayed in the figure.

• F1, F2, F3 are the micro-operation fields. They determine micro-operations for
the computer.
• CD is the condition for branching. They choose the status bit conditions.
• BR is the branch field. It determines the type of branch.
• AD is the address field. It includes the address field whose length is 7 bits.
• LINK FOR DETAIL DOCUMENT
Computer Organization Computer Architecture
• We have 7 CPU registers that their outputs are connected to
2 MUX 8 X 1 to form the 2 buses A and B.
• The A and B are inputted to ALU unit in which its operation is selected
by their select lines among different arithmetic and logic operations.
• The resulted ALU data can is directed to the input of all 7 registers
which one of them will be selected according to 3 X 8 decoder
connected to LD inputs of the register.
• For example to perform operation R1 = R2 + R3
• The control then provides
• MUXA select R2
• MUXB select R3
• OPR in ALU operation for ADD
• SELD to direct destination register R1

These four control signals are generated in control unit in start of each clock cycle
ensuring operands are selected beside correct ALU operation and result is chosen
in one clock cycle only.
Control word
Encoding of ALU Operations