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UPDATED TO 2023-2025 SYLLABUS

CAIE AS LEVEL
COMPUTER SCIENCE
SUMMARIZED NOTES ON THE THEORY SYLLABUS
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CAIE AS LEVEL COMPUTER SCIENCE
The Processor (CPU)

1. Processor Fundamentals Arithmetic and Logic Unit (ALU): part of the processor
that processes instructions which require some form of
arithmetic or logical operation
1.1. Central Processing Unit (CPU) Control Unit (CU): part of the CPU that fetches
Architecture instructions from memory, decodes them &
synchronizes operations before sending signals to the
Von Neumann model computer’s memory, ALU and I/O devices to direct how
to respond to instructions sent to the processor
Von Neumann realized data & programs are Immediate Access Store (IAS): memory unit that the
indistinguishable and can, therefore, use the same processor can directly access
memory. System Clock: a timing device connected to a processor
Von Neumann's architecture uses a single processor. that synchronises all components.
It follows a linear sequence of fetch–decode–execute
operations for the set of instructions, i.e. the program. Buses
To do this, the processor uses registers.
Set of parallel wires that allow the transfer of data
Registers between components in a computer system
Data bus: bidirectional bus that carries data
Registers: smallest unit of storage of microprocessor; instructions between processor, memory, and I/O
allows fast data transfer between other registers devices.
General Purpose registers Address bus: unidirectional bus that carries the
Used to temporarily store data values which have address of the main memory location or input/output
been read from memory or some processed result device about to be used, from processor to memory
Assembly language instructions can use it address register (MAR)
Special Purpose Registers Control bus
Some are accessible by assembly language Bidirectional
instructions used to transmit control signals from the control unit
Only holds either data or memory location, not both to ensure access/use of data & address buses by
Particular purpose registers include: components of the system does not lead to conflict
Program Counter (PC): holds the address of the
next instruction to be fetched Performance of Computer System Factors
Memory Data Register (MDR): holds data value
fetched from memory
Memory Address Register (MAR): Holds the
address of the memory cell of the program which
is to be accessed
Accumulator (ACC): holds all values that are
processed by arithmetic & logical operations.
Index Register (IX): Stores a number used to
change an address value
Current Instruction Register (CIR): Once program
instruction is fetched, it is stored in CIR and allows
the processor to decode & execute it
Status Register: holds results of comparisons to
decide later for action, intermediate and
erroneous results of arithmetic performed

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Clock Speed Hardware which provides a physical interface between a

Number of pulses the clock sends out in a given time device with CPU and a peripheral device
interval, which determines the number of cycles Peripheral (I/O) devices cannot be directly connected to
(processes) the CPU executes in a given time interval the CPU, hence connected through ports.
Usually measured in Gigahertz (GHz) Universal Serial Bus (USB): Can connect both input and
If the clock speed is increased, then the execution output devices to the processor through a USB port.
time for instructions decreases. Hence, more cycles High Definition Multimedia Interface (HDMI)
per unit time, which increases performance. Can only connect output devices (e.g. LCD) to the
However, there is a limit on clock speed since the processor through a HDMI port
heat generated by higher clock speeds cannot be HDMI cables transmit high-bandwidth and high-
removed fast enough, which leads to overheating. resolution video & audio streams through HDMI
Bus Width ports
Determines the number of bits that can be Video Graphics Array (VGA)
simultaneously transferred Can only connect output devices (e.g. second
Refers to the number of lines in a bus monitor/display) to the processor through a VGA port
Increasing bus width increases the number of bits VGA ports allow only the transmission of video
transferred simultaneously, increasing processing streams but not audio components
speed and performance.
Cache Memory Fetch-Execute (F-E) cycle
Commonly used instructions are stored in the cache Fetch stage
memory area of the CPU. PC holds the address of the next instruction to be
If the cache memory size is increased, more
fetched
commonly executed instructions can be stored, and The address on the PC is copied to MAR
the need for the CPU to wait for instructions to be PC is incremented
loaded reduces. Hence, the CPU executes more Instruction loaded to MDR from the address held in
cycles per unit of time, thus improving performance. MAR
Number of Cores
Instruction from MDR loaded to CIR
Most CPU chips are multi-core — have more than Decode stage: The opcode and operand parts of
one core (essentially a processor) instruction are identified
Each core simultaneously processes different Execute stage: Instructions executed by the control unit
instructions through multithreading, improving sending control signals
computer performance.
Register Transfer Notation (RTN)
Ports MAR ← [PC]
PC ← [PC] + 1
MDR ← [[MAR]]
CIR ← [MDR]
Decode
Execute
Return to start
Square brackets: value currently in that register
Double square brackets: CPU is getting value stored
at the address in the register

Interrupts

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A signal from a program seeking the processor’s Assembly language: low-level programming language
attention with instructions made up of an op code and an operand
Handles the interrupt by controlling the processor Machine code: code written in binary that uses the
Different ISRs used for different sources of interrupt processor’s basic machine operations
Relationship between machine and assembly language:
A typical sequence of actions when an interrupt occurs: every assembly language instruction (source code)
The processor checks the interrupt register for translates into exactly one machine code instruction
interrupt at the end of the F-E cycle for the current (object code)
instruction Symbolic addressing
If the interrupt flag is set in the interrupt register, the Symbols used to represent operation codes
interrupt source is detected Labels can be used for addresses
If the interrupt is low priority, then an interrupt is Absolute addressing: a fixed address in memory
disabled Assembler
If interrupting is a high priority: Software that changes assembly language into
All contents of registers of the running process machine code for the processor to understand
are saved on the stack The assembler replaces all mnemonics and labels
PC is loaded with the ISR and is executed with their respective binary values (that are
Once ISR is completed, the processor pops the predefined before by the assembler software)
registers’ contents from the stack, and the One pass assembler
interrupted program continues its execution. Assembler converts mnemonic source code into
Interrupts re-enabled and machine code in one sweep of program
Return to the start of the cycle Cannot handle code that involves forward
referencing
1.2. Assembly Language Two pass assembler: software makes 2 passes thru code
On the first pass:
Symbol table created to enter symbolic addresses
and labels into specific addresses
All errors are suppressed
On the second pass:
Jump instructions access memory addresses via
table
Whole source code translates into machine code
Error reported if they exist
Grouping the Processor’s Instruction Set

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Op Code Operand Explanation
Addressing Modes of Addressing
Direct Addressing: loads contents at address into ACC
LDM #n Immediate: Load n into ACC
Indirect Addressing: The address to be used is at
Direct: load contents at
LDD given address. Load contents of this second address
address into the ACC
Indirect: load contents of
to ACC
LDI address at given address into Indexed addressing: form the address to be used as
ACC + the contents of the IR (Index Register)
Indexed: load contents of given Relative addressing: next instruction to be carried out
LDX is an offset number of locations away, relative to
address + IR into ACC
Data Movement address of current instruction held in PC; allows for
Store contents of ACC into relocatable code
STO Conditional jump: has a condition that will be
address
Arithmetic checked (like using an IF statements)
Operations Unconditional jump: no condition to be followed,
ADD Add contents of register to ACC simply jump to the next instruction as specified
Add 1 to contents of the
INC
register 1.3. Bit Manipulation
Comparing
Compare contents of ACC with Binary numbers can be multiplied or divided by shifting
CMP
that of given address Left shift (LSL #n)
Compare contents of ACC with Bits are shifted to the left to multiply
CMP #n
n E.g. to multiply by four, all digits shift two places to
Conditional Jumps left
Jump to address if compare Right shift (LSR #n)
JPE
TRUE Bits are shifted to the right to divide
Jump to address if compare E.g. to divide by four, all digits shift two places to right
JPN
FALSE
Logical shift: zeros replace the vacated bit position
Unconditional Jumps Arithmetic shift: Used to carry out multiplication and
JMP Jump to given address division of signed integers represented by bits in the
I/O Data accumulator by ensuring that the sign-bit (usually the
Input any character and store MSB) is the same after the shift.
IN
ASCII value in ACC Cyclic shift: the bit that is removed from one end by the
Output character whose ASCII shift is added to the other end.
OUT
value is stored in ACC
Ending Bit Masking
Return Control to operating
END
system

#denotes immediate addressing

B denotes a binary number, e.g. B01001010 & denotes a
hexadecimal number, e.g. &4A

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Each bit can represent an individual flag.

∴ by altering the bits, flags could be operated upon.
Bit manipulation operations:
Masking: an operation that defines which bits you
want to keep and which bits you want to clear.
Masking to 1: The OR operation is used with a 1.
Masking to 0: The AND operation is used with a 0.
Matching: an operation that allows the accumulator
to compare the value it contains to the given value in
order to change the state of the status register.
Practical applications of Bit Masking:
Setting an individual bit position:
Mask the content of the register with a mask
pattern which has 0 in the ‘mask out’ positions
and 1 in the ‘retain’ positions.
Set the result with the match pattern by using the
AND command with a direct address.
Testing one or more bits:
Mask the content of the register with a mask
pattern which has 0 in the ‘mask out’ positions
and 1 in the ‘retain’ positions.
Compare the result with the match pattern by
using the CMP command or by “Checking the
pattern”.
Checking the pattern
Use AND operation to mask bits and obtain
resultant.
Now subtract matching bit pattern from resultant.
The final ‘non-zero’ result confirms the patterns
are not the same else vice versa.

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CAIE AS Level
Computer Science

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