Module-3

Basic Structure of Computers &

Machine Instructions and
Programs
 Syllabus
• Basic Structure of Computers: Functional Units,
• Basic Operational Concepts,
• Bus structure,
• Performance – Processor Clock, Basic Performance
Equation, Clock Rate, Performance Measurement.
• Machine Instructions and Programs: Memory Location
and Addresses,
• Memory Operations,
• Instruction and Instruction sequencing,
• Addressing Modes.
 Introduction
• Computer organization describes the function and design of
the various units of digital computers that store and process
information.
• It also deals with the units of the computer that receive
information from external sources and send computed results
to external destinations.
• Computer architecture encompasses the specification of an
instruction set and the hardware units that implement the
instructions.
• The list of instructions is called a computer program, and the
internal storage is called computer memory.
 Functional Units

Arithmetic
Input and
logic
Memory

Output Control

I/O Processor

Basic functional units of a computer

 Information Handled by a Computer
• Instructions/machine instructions
➢Govern the transfer of information within a
computer as well as between the computer and its
I/O devices
➢Specify the arithmetic and logic operations to be
performed
➢Program
• Data
➢Used as operands by the instructions
➢Source program
• Encoded in binary code – 0 and 1
 Memory Unit
• Store programs and data
• Two classes of storage
➢Primary storage
❖Fast
❖Programs must be stored in memory while they are being
executed
❖Large number of semiconductor storage cells
❖Processed in words
❖Address
❖RAM and memory access time
❖Memory hierarchy – cache, main memory
➢Secondary storage – larger and cheaper
 Arithmetic and Logic Unit (ALU)
• Most computer operations are executed in ALU of
the processor.
• Load the operands into memory – bring them to
the processor – perform operation in ALU – store
the result back to memory or retain in the
processor.
• Registers
• Fast control of ALU
 Control Unit
• All computer operations are controlled by the control
unit.
• The timing signals that govern the I/O transfers are also
generated by the control unit.
• Control unit is usually distributed throughout the machine
instead of standing alone.
• Operations of a computer:
➢Accept information in the form of programs and data through an
input unit and store it in the memory
➢Fetch the information stored in the memory, under program
control, into an ALU, where the information is processed
➢Output the processed information through an output unit
➢Control all activities inside the machine through a control unit
 Basic Operational Concepts
• Activity in a computer is governed by instructions.
• To perform a task, an appropriate program consisting of
a list of instructions is stored in the memory.
• Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
• Data to be used as operands are also stored in the
memory.
 A Typical Instruction (Example)
Add LOCA, R0
• Add the operand at memory location LOCA to the operand in a
register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• Instruction is fetched from the memory into the processor –
the operand at LOCA is fetched and added to the contents of
R0 – the resulting sum is stored in register R0.
Load LOCA, R1
Add R1, R0
• Whose contents will be overwritten?
 Connection Between the Processor
and the Memory

Registers
• Instruction register (IR)
• Program counter (PC)
• General-purpose register (R0 – Rn-1)
• Memory address register (MAR)
• Memory data register (MDR)
 Typical Operating Steps
• Programs reside in the memory through input devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction
 Typical Operating Steps
• Get operands for ALU
➢General-purpose register
➢Memory (address to MAR – Read – MDR to ALU)
• Perform operation in ALU
• Store the result back
➢To general-purpose register
➢To memory (address to MAR, result to MDR – Write)
• During the execution, PC is incremented to
the next instruction
 Interrupt
• Normal execution of programs may be preempted if
some device requires urgent servicing.
• The normal execution of the current program must be
interrupted – the device raises an interrupt signal.
• Interrupt-service routine
• Current system information backup and restore (PC,
general-purpose registers, control information, specific
information)
 Bus Structures
• There are many ways to connect different parts
inside a computer together.
• A group of lines that serves as a connecting path for
several devices is called a bus.
• Address/data/control

Input Output Memory Processor

Single-bus structure
 Speed Issue
• Different devices have different transfer/operate
speed.
• If the speed of bus is bounded by the slowest device
connected to it, the efficiency will be very low.
• How to solve this?
• A common approach – use buffers.
 Performance
• The most important measure of a computer is how
quickly it can execute programs.
• Three factors affect performance:
➢Hardware design
➢Instruction set
➢Compiler

Main Cache
memory memory Processor

The processor cache

Bus
 Performance
• Elapsed time and Processor time
• Processor time to execute a program depends on
the hardware involved in the execution of
individual machine instructions.
• The processor and a relatively small cache memory
can be fabricated on a single integrated circuit chip.
• Speed
• Cost
• Memory management
 Processor Clock

• Processor circuits are controlled by a timing signal

called Clock, Regular time intervals called clock
cycle.
• The execution of each instruction is divided into
several steps, each of which completes in one clock
cycle.
• Clock rate, R=1/P [P-length of one clock cycle]
• Hertz – cycles per second
 Basic Performance Equation
• T – processor time required to execute a program that has
been prepared in high-level language
• N – number of actual machine language instructions needed to
complete the execution (note: loop)
• S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
• R – clock rate
• Note: these are not independent to each other

N S
Program execution time, T =
R
 Pipeline and Superscalar Operation
• Instructions are not necessarily executed one after
another.
• The value of S doesn’t have to be the number of clock
cycles to execute one instruction.
• Pipelining – overlapping the execution of successive
instructions.
Add R1, R2, R3
• Superscalar operation – multiple instruction pipelines
are implemented in the processor.
• Goal – reduce S (could become <1!)
 Clock Rate
• Increase clock rate
➢Improve the integrated-circuit (IC) technology to make
the circuits faster
➢Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)
• Increases in R that are entirely caused by
improvements in IC technology affect all aspects of
the processor’s operation equally except the time
to access the main memory.
 CISC and RISC
• Tradeoff between N and S
• A key consideration is the use of pipelining
➢S is close to 1 even though the number of basic steps
per instruction may be considerably larger
➢It is much easier to implement efficient pipelining in
processor with simple instruction sets
• Reduced Instruction Set Computers (RISC)
• Complex Instruction Set Computers (CISC)
• Both are design principles and technique.
 Compiler
• A compiler translates a high-level language program
into a sequence of machine instructions.
• To reduce N, we need a suitable machine instruction
set and a compiler that makes good use of it.
• Goal, Optimizing compiler – reduce N×S
• A compiler may not be designed for a specific
processor; however, a high-quality compiler is usually
designed for, and with, a specific processor.
 Performance measurement
• Computer Designer, Manufacturer and Buyers will look through the
performance measure of any computer system.
• Performance measurement uses some benchmark programs.
• SPEC(System Performance Evaluation Corporation) selects & publishes the
standard programs along with their test results for different application domains
• The SPEC rating is computed as follows;

• If SPEC rating=50 means that the computer under test is 50times as fast as
reference computer.
• The test is repeated for all the programs in the SPEC suite, and the geometric
mean of the results is computed.
• Let SPECi be the rating for program i in the suite. The overall SPEC rating for
the computer is given by ;

where n=number of programs in the suite

 PROBLEMS
1. Effective value of S for RISC machine is 1.2 and for CISC
machine it is 1.5. Both machines have same clock rate R. what is
the largest allowable value for N, on the CISC machine expressed
as percentage of N value for the RISC machine? (Assume they
have same execution time)
SOLUTION:
Let TR = (NR X SR) /RR and TC = (NC X SC) /RC be execution times on
the RISC and CISC processors, respectively. Equating execution
times and clock rates, we have,
1.2 NR = 1.5 NC
Then,
NC / NR = 1.2 /1.5 = 0.8
Therefore, the largest allowable value for NC is 80% of NR.
2. A program contains 1000 instructions. Out of that 25%
instructions requires 4 clock cycles, 40% instructions requires 5
clock cycles and remaining require 3 clock cycles for execution.
Find the total time required to execute the program running in a
1 GHz machine.
SOLUTION:
N=1000
25% of N= 250 instructions require 4 clock cycles,
40% of N =400 instructions require 5 clock cycles,
35% of N=350 instructions require 3 clock cycles
so, T = (N*S)/R
= 250*4+400*5+350*3/1*109
=1000+2000+1050/1*109
= 4.05μs
 Memory Location, Addresses, and Operation
n bits
• Memory consists of many
first word
millions of storage cells,
second word
each of which can store 1 bit.
• Data is usually accessed in n-
•
bit groups. n is called word •
length. •

• Moder computer have word i th word

lengths varies from 16 to 64
bits.
•
• 8bits-byte •
•

last word

Memory words
Memory Location, Addresses, and Operation
32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses, and Operation
• To retrieve information from memory, either for one
word or one byte, addresses for each location are
needed.
• A k-bit address memory has 2k memory locations,
namely 0 to 2k-1, called memory space.
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240
Memory Location, Addresses, and Operation

• It is impractical to assign distinct addresses to

individual bit locations in the memory.
• The most practical assignment is to have successive
addresses refer to successive byte locations in the
memory – byte-addressable memory.
• Byte locations have addresses 0, 1, 2, … If word length
is 32 bits, they successive words are located at
addresses 0, 4, 8,…
 Big-Endian and Little-Endian Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of
the word.
Little-Endian: opposite ordering. lower byte addresses are used for the less
significant bytes of the word.
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Byte and word addressing

Memory Location, Addresses, and Operation

• Address ordering of bytes

• Word alignment
• Words are said to be aligned in memory if they
begin at a byte address, that is a multiple of the
num of bytes in a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….
• Access numbers, characters, and character
strings
 Memory Operation
• Load (or Read or Fetch)
➢Copy the content. The memory content doesn’t
change.
➢Address – Load
➢Registers can be used
• Store (or Write)
➢Overwrite the content in memory
➢Address and Data – Store
➢Registers can be used
Instruction and Instruction sequencing
• Any type of operations in the computer, must
have instructions capable of performing these
operations:
➢Data transfers between the memory and the
processor registers
➢Arithmetic and logic operations on data
➢Program sequencing and control
➢I/O transfers
 Register Transfer Notation
• Identify a location by a symbolic name standing for
its hardware binary address (LOC, R0,…)
• Contents of a location are denoted by placing
square brackets around the name of the location
(R1←[LOC], R3 ←[R1]+[R2])
• Register Transfer Notation (RTN)
 Assembly Language Notation
• Represent machine instructions and programs.
• Move LOC, R1 = R1←[LOC]
• Add R1,R2,R3 = R3 ←[R1]+[R2]
 CPU Organization
• Single Accumulator
• Result usually goes to the Accumulator
• Accumulator has to be saved to memory quite often
• General Register
• Registers hold operands thus reduce memory traffic
• Register bookkeeping
• Stack
• Operands and result are always in the stack
 Instruction Formats
• Three-Address Instructions
• ADD R2, R3, R1 R1 ← R2 + R3
• Two-Address Instructions
• ADD R2, R1 R1 ← R1 + R2
Operation source1, source2, destination
Operation source, destination
• One-Address Instructions
• ADD A AC ← AC + M[A]
• Zero-Address Instructions
• ADD TOS ← TOS + (TOS – 1)
• RISC Instructions
• Lots of registers. Memory is restricted to Load & Store

Instruction
Opcode Operand(s) or Address(es)
 Instruction Formats
The ordering of source and destination operands is different
In different computers.
Modern computers have number of General purpose
Registers(8 to 32).
Example: Load A
Add B
Store C
Example: Evaluate (A+B)  (C+D)
• Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1  R2
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1  R3
8. STORE X, R1 ; M[X] ← R1
• Let Ri is general purpose registers;
Load A, Ri
Store Ri, A
Add A, Ri
• Example: C=A+B
Mov A, Ri Mov A, Ri
Mov B, Rj Add B, Ri
Add Ri, Rj Mov Ri, C
Mov Rj, C
Using Registers
• Registers are faster
• Shorter instructions
• The number of registers is smaller (e.g. 32 registers need
5 bits)
• Potential speedup
• Minimize the frequency with which data is moved
back and forth between the memory and processor
registers.
 Instruction Execution and Straight-
Line Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
3-instruction - One memory operand per
i +4 Add B,R0 program
segment instruction
i +8 Move R0,C
- 32-bit word length
- Memory is byte addressable
- Full memory address can
A be directly specified in
single-word instruction

B Data for
the program Two-phase procedure
-Instruction fetch
-Instruction execute
C

A program for C  [A] + [B].

• The Program Counter(PC), which holds the
addresses of the instruction execute next.
• Straight line sequencing
• 2 phase- Instruction fetch and Instruction
execute
• PC to IR
Branching Move NUM1,R0
i
i+4 Add NUM2,R0
i+8 Add NUM3,R0

•
•
•
i + 4n - 4 Add NUM n,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUM n

A straight-line program for adding n numbers

 Move N,R1

Branching LOOP
Clear R0

Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM
Conditional branch
•
•
•
SUM
N n
NUM1
NUM2

•
•
A loop to add n numbers •
NUM n
 Condition Codes
• Condition code flags (individual bits)
• Condition code register / status register
➢N (negative)- Set to 1, if the result is negative, else 0
➢Z (zero)-Set to 1, if the result is zero, else 0
➢V (overflow)- Set to 1, if arithmetic overflow occurs,
else 0
➢C (carry)-Set to 1, if a carry out result there in
arithmetic operation
• Different instructions affect different flags
 Generating Memory Addresses
• How to specify the address of branch target?
• Can we give the memory operand address directly
in a single Add instruction in the loop?
• Use a register to hold the address of NUM1; then
increment by 4 on each pass through the loop.
 Addressing Modes
• Data Structures- Programmers use organizing the data. (list,
arrays, queues)
• Programmers use arrays, pointers, local and global variables,
constants.
• Location of an operand is specified in an instruction –
addressing modes.
Instruction
Opcode Mode ...

• Implied
• AC is implied in “ADD M[A]” in “One-Address” instr.
• TOS is implied in “ADD” in “Zero-Address” instr.
• Immediate
• The use of a constant in “MOV R1, 5”, i.e. R1 ← 5
• Register
• Indicate which register holds the operand
 Addressing Modes
• Register Indirect
• Indicate the register that holds the number of the register
that holds the operand
MOV R1, (R2) R1

• Autoincrement / Autodecrement R2 = 3
• Access & update in 1 instr.
• Direct Address R3 = 5
• Use the given address to access a memory location

Variables and constants are the simplest data types used in

programs. We allocate this in register or any memory address to
hold its value.
 Addressing Modes
• Indirect Address
• Indicate the memory location that holds the address of the
memory location that holds the data

AR = 101
Memory

100
101 0 1 0 4
102
103
104 1 1 0 A
 Addressing Modes
• Relative Address Memory
• EA = PC + Relative Addr 0
a m
1
g r
PC = 2 2
r o
P
+

100
t a
a
AR = 100
D
101
102 1 1 0 A
Could be Positive or 103
Negative 104
(2’s Complement)
 Addressing Modes
• Indexed
• EA = Index Register + Relative Addr Memory

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive or
Negative 102 1 1 0 A
(2’s Complement) 103
104
 Addressing Modes
• Base Register
• EA = Base Register + Relative Addr Memory

Could be Positive or AR = 2
Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array
 Addressing Modes

The different ways in

which the location of an
operand is specified in an
instruction are referred
to as addressing modes.
 Addressing Modes
Mov R0,R1
Mov LOC, R2
Mov #200, R0
Add (A), R0
• Write a assembly level program for A=B+6
• The instruction doesn’t provide the address of operand,
instead it provides the information from which memory
address of operand can be determined, this address we
refer as, Effective address.
• The register or memory location that contain the address
of an operand called as a Pointer.
• Indirection and use of a pointer is important in
programming.
 Indexing and Arrays
• Index mode – the effective address of the operand is
generated by adding a constant value to the contents of a
register.
• Index register
• X(Ri); EA = X + [Ri]
• The constant X may be given either as an explicit number or
as a symbolic name representing a numerical value.
• If X is shorter than a word, sign-extension is needed.
• In general, the Index mode facilitates access to an operand
whose location is defined relative to a reference point within
the data structure in which the operand appears.
• Several variations:
(Ri, Rj); EA = [Ri] + [Rj]
X(Ri, Rj); EA = X + [Ri] + [Rj]
 Indexing and Arrays

Indexed addressing used in accessing test scores in the list

 Relative Addressing
• Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
• X(PC) – note that X is a signed number
• Branch>0 LOOP
• This location is computed by specifying it as an offset
from the current value of PC.
• Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.
 Additional Modes
• Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
• (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
• Autodecrement mode: -(Ri) – decrement first

Move N,R1
Move #NUM1,R2 Initialization
Clear R0
LOOP Add (R2)+,R0
Decrement R1
Branch>0 LOOP
Move R0,SUM

The Autoincrement addressing mode used in the program