Chapter-4

Author ; Mhuammad Waseem sabri

Processor Fundamentals
Central Processing Unit Architecture

Von Neumann model

 Von Neumann realized data & programs are indistinguishable and can therefore use same

memory.

 Von Neumann architecture uses a single processor.

 It follows a linear sequence of fetch–decode–execute operations for the set of instructions i.e.

the program.

 In order to do this, the processor uses registers.

 Registers: smallest unit of storage of microprocessor; allows fast data transfer between other

registers

General Purpose registers

 Used to temporarily store data values which have been read from memory or some processed

result

 Can be used by assembly language instructions

Special Purpose Registers

 Some are accessible by assembly language instructions

 Only holds either data or memory location, not both

 Special purpose registers include:

Program Counter (PC): holds address of next instruction to be fetched

Memory Data Register (MDR): holds data value fetched from memory
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Memory Address Register (MAR): Holds address of memory cell of program which is to be

accessed

Accumulator (ACC): holds all values that are processed by arithmetic & logical operations.

Index Register (IX): Stores a number used to change an address value

Current Instruction Register (CIR): Once program instruction fetched, it is stored in CIR and

allows the processor to decode & execute it

Status Register: holds results of comparisons to decide later for action, intermediate and

erroneous results of arithmetic performed

The Processor (CPU)

Arithmetic and Logic Unit (ALU): part of processor that processes instructions which require

some form of arithmetic or logical operation

Control Unit (CU): part of CPU that fetches instructions from memory, decodes them &

synchronizes operations before sending signals to computer’s memory, ALU and I/O devices to

direct how to respond to instructions sent to processor

Immediate Access Store (IAS): memory unit that can be directly accessed by the processor

System Clock: timing device connected to processor that is needed to synchronize all

components.

Buses
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 set of parallel wires that allow the transfer data between components in a computer system

 Data bus: bidirectional bus that carries data instructions between processor, memory, and I/O

devices.

 Address bus: unidirectional bus that carries address of main memory location or input/output

device about to be used, from processor to memory address register (MAR)

 Control bus

 Bidirectional and unidirectional

 used to transmit control signals from control unit to ensure access/use of data & address buses

by components of system does not lead to conflict

 Performance of Computer System Factors

Clock Speed

 number of pulses the clock sends out in a given time interval, which determines the number of

cycles (processes) CPU executes in a given time interval

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 usually measured in Gigahertz (GHz)

 If the clock speed is increased, then execution time for instructions decreases. Hence, more

cycles per unit time, which increases performance.

 However, there is a limit on clock speed since the heat generated by higher clock speeds cannot

be removed fast enough, which leads to overheating

Bus Width

 Determines number of bits that can be simultaneously transferred

 Refers to number of lines in a bus

 Increasing bus width increases number of bits transferred at one time, hence increasing

processing speed and performance since there

Cache Memory

 Commonly used instructions are stored in the cache memory area of the CPU.

 If cache memory size is increased, more commonly executed instructions can be stored and the

need for the CPU to wait for instructions to be loaded reduces, hence CPU executes more cycles

per unit time, thus improving performance

Number of Cores

 Most CPU chips are multi-core — have more than one core (essentially a processor)

 Each core simultaneously processes different instructions through multithreading, improving

computer performance

Ports

 Hardware which provides a physical interface between a device with CPU and a peripheral

device
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 Peripheral (I/O) devices cannot be directly connected to CPU, hence connected through ports

 Universal Serial Bus (USB): Can connect both input and output devices to processor through a

USB port

 High Definition Multimedia Interface (HDMI)

 Can only connect output devices (e.g. LCD display) to the processor through a HDMI port

 HDMI cables transmit high-bandwidth and high-resolution video & audio streams through

HDMI ports

Video Graphics Array (VGA)

 Can only connect output devices (e.g. second monitor/display) to the processor through a VGA

port

 VGA ports allows only the transmission of video streams, but not audio components

Fetch-Execute (F-E) cycle

Fetch stage

 PC holds address of next instruction to be fetched

 Address in PC is copied to MAR

 PC is incremented

 Instruction loaded to MDR from address held in MAR

 Instruction from MDR loaded to CIR

 Decode stage: The opcode and operand parts of instruction are identified

 Execute stage: Instructions executed by the control unit sending control signals

 Register Transfer Notation (RTN)

 MAR ← [PC]
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 PC ← [PC] + 1

 MDR ← [[MAR]]

 CIR ← [MDR]

 Decode

 Execute

 Return to start

 Square brackets: value currently in that register

 Double square brackets: CPU must do a logical process and then copy this value

 Interrupts

 A signal from a program seeking processor’s attention

Interrupt Service Routine (ISR):

 Handles the interrupt by controlling the processor

 Different ISRs used for different sources of interrupt

 Typical sequence of actions when interrupt occurs:

 The processor checks interrupt register for interrupt at the end of the F-E cycle for the current

instruction

 If the interrupt flag is set in the interrupt register, the interrupt source is detected

 If interrupt is low priority: then interrupt is disabled

 If interrupt is high priority:

 All contents of registers of the running process are saved on the stack

 PC is loaded with the ISR, and is executed

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 Once ISR is completed, the processor restores registers’ contents from the stack, and the

interrupted program continues its execution

 Interrupts re-enabled and

 Return to start of cycle

Assembly Language

 Assembly language: low-level programming language with instructions made up of an op code

and an operand

 Machine code: code written in binary that uses the processor’s basic machine operations

 Relationship between machine and assembly language: every assembly language instruction

(source code) translates into exactly one machine code instruction (object code)

Symbolic addressing

 Symbols used to represent operation codes

 Labels can be used for addresses

 Absolute addressing: a fixed address in memory

Assembler

 Software that changes assembly language into machine code for the processor to understand

 The assembler replaces all mnemonics and labels with their respective binary values (that are

predefined before by the assembler software)

One pass assembler

 Assembler converts mnemonic source code into machine code in one sweep of program

 Cannot handle code that involves forward referencing

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Two pass assembler: software makes 2 passes thru code

 On the first pass:

 Symbol table created to enter symbolic addresses and labels into specific addresses

 All errors are suppressed

 On the second pass:

 Jump instructions access memory addresses via table

 Whole source code translates into machine code

 Error reported if they exist

 Grouping the Processor’s Instruction Set

Op Code Operand Explanation

Adressing

LDM #n Immediate: Load n into ACC

LDD Direct: load contents at address into the ACC

Indirect: load contents of address at given address

LDI
into ACC

LDX Indexed: load contents of given address + IR into ACC

Data Movement

STO Store contents of ACC into address

Arithmetic
Operations

ADD Add contents of register to ACC

INC Add 1 to contents of the register

Comparing

CMP Compare contents of ACC with that of given address

CMP #n Compare contents of ACC with n

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Op Code Operand Explanation

Conditional Jumps

JPE Jump to address if compare TRUE

JPN Jump to address if compare FALSE

Unconditional Jumps

JMP Jump to given address

I/O Data

IN Input any character and store ASCII value in ACC

OUT Output character whose ASCII value is stored in ACC

Ending

END Return Control to operating system

#denotes immediate addressing

B denotes a binary number, e.g. B01001010 & denotes a hexadecimal number, e.g. &4A

Modes of Addressing

 Direct Addressing: loads contents at address into ACC

 Indirect Addressing: The address to be used is at given address. Load contents of this second

address to ACC

 Indexed addressing: form the address to be used as

+ the contents of the IR (Index Register)

 Relative addressing: next instruction to be carried out is an offset number of locations away,

relative to address of current instruction held in PC; allows for relocatable code

 Conditional jump: has a condition that will be checked (like using an IF statements)

 Unconditional jump: no condition to be followed, simply jump to the next instruction as

specified
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Bit Manipulation

 Binary numbers can be multiplied or divided by shifting

 Left shift (LSL #n)

 Bits are shifted to the left to multiply

 E.g. to multiply by four, all digits shift two places to left

 Right shift (LSR #n)

 Bits are shifted to the right to divide

 E.g. to divide by four, all digits shift two places to right

 Logical shift: zeros replace the vacated bit position

 Arithmetic shift: Used to carry out multiplication and division of signed integers represented by

bits in the accumulator by ensuring that the sign-bit (usually the MSB) is the same after the

shift.
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 Cyclic shift: the bit that is removed from one end by the shift is added to the other end.

Bit Masking

 Each bit can represent an individual flag.

 ∴ by altering the bits, flags could be operated upon.

 Bit manipulation operations:

 Masking: an operation that defines which bits you want to keep and which bits you want to

clear.

 Masking to 1: The OR operation is used with a 1.

 Masking to 0: The OR operation is used with a 0.

 Matching: an operation that allows the accumulator to compare the value it contains to the

given value in order to change the state of the status register.

 Practical applications of Bit Masking:

 Setting an individual bit position:

 Mask the content of the register with a mask pattern which has 0 in the ‘mask out’ positions

and 1 in the ‘retain’ positions.

 Set the result with the match pattern by using the AND command with a direct address.

 Testing one or more bits:

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 Mask the content of the register with a mask pattern which has 0 in the ‘mask out’ positions

and 1 in the ‘retain’ positions.

 Compare the result with the match pattern by using the CMP command or by “Checking the

pattern”.

 Checking the pattern

 Use AND operation to mask bits and obtain resultant.

 Now subtract matching bit pattern from resultant.

 The final ‘non-zero’ result confirms the patterns are not the same else vice versa.