EDT – Embedded Deterministic Test:
EDT stands for Embedded Deterministic Test.
Based on standard scan with traditional deterministic ATPG uses fault
models to obtain test coverage.
EDT Terminology:
EDT Pins:
1. edt_channel_in
2. edt_clock
3. edt_update
4. edt_bypass
5. scan_enable
6. edt_channel_out
Fig: Sharing EDT Pins
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EDT Signal Behaviour:
Note:
During capture scan_enable and edt_update can have any value.
During capture edt_clock must be OFF.
Pattern Generation Process:
Fig: Testkompress Pattern Generation Process
EDT Architecture:
The main blocks in EDT architecture are:
1. Decompressor
2. Compactor
3. Bypass (Optional)
Fig: EDT Block Diagram
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Fig: EDT Architecture
1. Decompressor:
Feeds a large number of scan chains in your core design from a
small number of scan channels.
The decompressor resides between the channel inputs and the
scan channel inputs of the core.
Data and Control Signals:
1. edt_update: Resets or updates 2 sets of registers- Ring
generator in decompressor and mask hold in compactor.
2. edt_clock
3. Scan channel inputs and scan chain outputs
Fig: Block Diagram of Decompressor
The decompressor consists of 2 major blocks:
a) Ring generator (LFSR):
The external inputs feeding the ring generator are commonly
referred as EDT channels. The outputs of the ring generator
flops will connect to scan chain inputs through a phase shifter
consisting of XOR gates.
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b) Phase Shifter:
Eliminates linear dependencies. Creation of the compressed
pattern from the original ATPG test pattern consists of solving
a set of linear equations based on the ring generator
polynomial and the phase shifter connections.
Fig: Decompressor Internal Diagram
2. Compactor:
Fig: Compactor
Compactor block is composed of XOR tree-based spatial
compactors {[reduces the number of output pins compared to
input pins] which consists of group of XOR trees. It allows
multiple scan chains to be observed at the same time on a
given scan output channel} and selective masking logic.
Allows multiple scan chain to be observed at same time on a
given channel.
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Compact test responses from scan chains in your core design
into small number of scan output channels as they are shifted
out.
The compactor contains 3 logic blocks:
1. An XOR tree - to combine the scan chain output
2. Mask gates – to block values on given scan chain
3. Mask control logic – to determine which chains get blocked
3. Bypass Logic (Optional):
By default, EDT logic includes logic that bypasses the compression logic
to provide direct access to uncompressed scan chains in the design core.
edt_bypass = 0 EDT mode
edt_bypass = 1 Bypass mode
EDT Inputs: Scan Inserted Netlist
EDT Outputs: EDT inserted netlist, test proc file and ATPG setup files for both
EDT logic and Bypass logic.
Compression Ratio:
Ratio of total number of internal chains to the total number of channels
𝑇𝑜𝑡𝑎𝑙 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝐼𝑛𝑡𝑒𝑟𝑛𝑎𝑙 𝐶ℎ𝑎𝑖𝑛𝑠
𝐶𝑜𝑚𝑝𝑟𝑒𝑠𝑠𝑖𝑜𝑛 𝑅𝑎𝑡𝑖𝑜 =
𝑇𝑜𝑡𝑎𝑙 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝐶ℎ𝑎𝑛𝑛𝑒𝑙𝑠
Test Data Volume:
𝑇𝑒𝑠𝑡 𝐷𝑎𝑡𝑎 𝑉𝑜𝑙𝑢𝑚𝑒
= 𝐿𝑒𝑛𝑔ℎ𝑡 𝑜𝑓 𝑡ℎ𝑒 𝑙𝑜𝑛𝑔𝑒𝑠𝑡 𝑐ℎ𝑎𝑖𝑛
∗ 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑐𝑎𝑛 𝑐ℎ𝑎𝑛𝑛𝑒𝑙𝑠 ∗ 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑝𝑎𝑡𝑡𝑒𝑟𝑛𝑠
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Test Cycles:
𝑇𝑒𝑠𝑡 𝐶𝑦𝑐𝑙𝑒𝑠 = 𝐿𝑒𝑛𝑔ℎ𝑡 𝑜𝑓 𝑙𝑜𝑛𝑔𝑒𝑠𝑡 𝑠𝑐𝑎𝑛 𝑐ℎ𝑎𝑖𝑛 ∗ 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑃𝑎𝑡𝑡𝑒𝑟𝑛𝑠
Scan Chain Masking and Fault Aliasing:
1. X-Blocking:
An X in one scan cell will block the observation of corresponding
cells in other scan chain associated with the same scan channel.
Fig: X-Blocking
Scan Chain Masking Solution:
A masking mechanism allows automatic selection of individual scan
chains, so that X sources from other scan chains won’t block the
observation.
Masking is done only, when necessary, on a pattern basis.
Fig: Masking Solution
2. Fault Aliasing:
A fault is aliased only if it is observed by an even number of scan
cells that are in same time slot, in chains that are compacted into one
channel.
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Fig: Fault Aliasing
Scan Chain Masking Solution:
All aliased faults will be masked and detected automatically by
masked patterns
An aliased fault will not be classified as detected for an unmasked
pattern.
Fig: Masking Solution
Advantages of EDT:
1. EDT supports many more scan chains i.e. No need to have a scan channel
for every scan chain
2. EDT test patterns are compressed which leads to better memory utilization
on tester.
3. EDT allows users to use shorted scan chains which leads to fewer shift
cycles.
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Fig: Example of EDT
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