CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES

University of Ioannina

Embedded Core
Testing
(ΙΕΕΕ 1500 Std. – SECT)

Dept. of Computer Science and Engineering

Y. Tsiatouhas

CMOS Integrated Circuit Design Techniques

Overview
1. Basic SECT architecture

2. The Wrapper Interface Port (WIP)

3. SECT registers

4. Instruction set

5. Parallel test access mechanism

VLSI Systems
and Computer Architecture Lab

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 2

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 System‐‐on
System on‐‐Chip (SoC
(SoC))
Chip
Cores

RAM A main design paradigm in modern

AG
JTA
CMOS technologies is the development

Flash
DSP
of Systems‐on‐a‐Chip (SoCs) where
reusable cores (digital, analog,
Clock BUS memory) are embedded in a chip.
RISC
GSM Tm RISC
Int. Radio The used core designs are characterized
as:
Interr. Audio • Soft (RTL code).
C
Contr. BUS Perif. Int. • Firm
Fi (netlist).
( tli t)
• Hard (layout).
RAM URTS Data Int.
EBI

Cores
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 3

Design Paradigms
System on Board System on Chip
Componeents
Components Prrovider

Provideer
(Coress)

Design and test Design and test

development development
(ICs)

Manufacturing

Test
Systtem Integrator
System Integraator

Design and test Design and test

development development

Manufacturing Manufacturing

Test Test

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 Automatic Test Equipment Support
ATE
Source Test Access Mechanism (TAM)
Chip

RAM Automatic Test Equipment:

Equipment Hardware

AG
JTA
equipment for the testing and diagnosis

Flash
DSP
of integrated circuits under the control
of proper software. An ΑΤΕ provides test
BUS data (test source) and monitors the test
Clock
RISC RISC responses (response sink)
Core Int. Radio
GSM Tm
Under Test
Test Access Mechanism:
Mechanism Circuitry
Interr. Audio embedded in the chip to support the
US

t
transfer
f off test
t t data
d t between
b t th ATE
the
BU

C
Contr. Perif. Int.
and the chip.
RAM URTS Data Int.
EBI

ATE Test Access Mechanism (TAM)

Sink
Embedded Core Testing (ΙΕΕΕ 1500 ‐ SECT std) 5

Automatic Test Equipment + BIST

ATE
Source Test Access Mechanism (TAM)
Chip

RAM Built‐In Self Test (BIST) circuits can be

AG
JTA

exploited for embedded test data

Flash

DSP
BIST
Source
generation and test response
monitoring. Thus, the ΑΤΕ complexity is
BUS drastically reduced and the same
Clock
RISC RISC stands for the required bandwidth to
Core Int. Radio
GSM Tm transfer test data in/out the chip.
Under Test
The ΑΤΕ activates the BIST circuitry and
Interr. Audio receives the final test decision.
US
BU

C
Contr. BIST Perif. Int.
Sink

RAM URTS Data Int.

EBI

ATE Test Access Mechanism (TAM)

Sink
Embedded Core Testing (ΙΕΕΕ 1500 ‐ SECT std) 6

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 Basic IEEE 1500 Architecture (Ι)
Wrapper TAM‐In TAM‐Out
Boundary (WPI[0:r]) (WPO[0:m]) The IEEE 1500 Embedded Core Testing
Register
Wrapper standard supports the testing process
(WBR) of embedded cores in a chip,
according to a common DFT and test
application methodology.
Wrapper
Wrapper
Bypass
Register
Core Cells It consists of a test wrapper around a
core and provides the following
(WBY)
facilities:
Wrapper • A Wrapper Interface Port ‐ WIP
Serial WSI with 6 inputs for control signals
Input plus 1 serial test data input
p p and 1
…

WSO
serial test data output.
Wrapper
Wrapper Serial
• A set of registers.
Instruction Output
Register WIP[0:5]
Wrapper
(WIR)
Interface
Port

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 7

Basic IEEE 1500 Architecture (ΙΙ)

TAM‐In TAM‐Out
Optional Testing
(WPI[0:r]) Ports
(WPO[0:m]) In the normal mode of operation the IEEE
1500 std. circuitry is “transparent”.

Core There are three modes of operation:

• Normal Operation: where the
wrapper is transparent.
• Core Internal Testing: where the
WSI internal core logic is under test.
test
• Core External Testing: where the
…

WSO
interconnects between the cores and
the glue logic are tested.
All protocol signals
WIP[0:5] (WPI, WPO, WSI, WSO, WIP)
are managed either by the BIST or the ATE

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 Wrapper Registers

PI PO

Core The IEEE 1500 protocol

WBR

WBR
... ... supports the following

R
CDRs
registers:
Scan Chain 0
Scan Chain 1
WMUX‐1
• Wrapper Bypass Register
WPI WPO
WDRs (WBY).
• Wrapper Instruction Register
WBY
(WIR).
... WMUX‐2
• Wrapper Boundary register
Decode Logic 0
WSO (WBR)
(WBR).
WSI ... WIR Circuitry
1
WIR • Various Data Registers
SelectWIR (WDR/CDR).
WRCK SelectWIR
WRSTN ShiftWR
UpdateWR
Wrapper CaptureWR

WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 9

Wrapper Interface Port – WIP (I)

WRSTN

WIP
Update WR
Shift WR
Capture WR
Core
Controls
& Clocks Select WIR
WRCK
Wrapper

• SelectWIR (Select Wrapper Instruction Register):

Register) Signal which controls the
operation of the WIP port. When active (high) the WIR register is connected
between the WSI and WSO pins else another register (WBY, WBR, WDR,
CDR …) is connected according to the instruction in the WIR register.

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 Wrapper Interface Port – WIP (II)

• ShiftWR (Wrapper Shift): Enable signal for the shift operations on the WIR
register (when SelectWIR=high) or another register (when SelectWIR=low)
according to the instruction in the WIR register.
register
• CaptureWR (Wrapper Capture): Enable signal for the parallel load of data in
the WIR register (when SelectWIR=high) or another register (when
SelectWIR=low) according to the instruction in the WIR register.
• UpdateWR (Wrapper Update): Enable signal for the update of the WIR
register (when SelectWIR=high) or another register (when SelectWIR=low)
according to the instruction in the WIR register.
• WRCK (Wrapper Clock): Clock signal for the operation of the WIR and WBY
registers or other registers of the wrapper (e.g. WBR) or even the core.
• WRSTN (Wrapper Reset): Asynchronous reset signal (active‐low) of the WIR
register or other registers of the wrapper.

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 11

Wrapper Registers’ Architecture

WPI Core WPO
1500 SIL

CDR z
… …
WBR_WSO
WBR WMUX‐2
WMUX‐1

DR_WSO
n1

0 WSO
WDR s 1

WBY_WSO
WBY
WDR_Cntrl

WBR_Cntrl
WBY_Cntrl
Core_Cntrl

CDR_Cntrl

DR_Select[0:log2n]

WSI WIR_WSO
WIR Circuitry
Select_WIR

WIP[0:5]
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 Wrapper Bypass Register – WBY

• The Wrapper Bypass Register – WBY is an one stage register. When this register
is enabled, the signal at the WSI input port bypasses every other register and
directly feeds the WSO output port.

WBY_Cntrl
Serial Shift WBY_WSO
WSI Stage
FF

WBY

WRCK

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 13

Wrapper Instruction Register – WIR

• The Wrapper Instruction Register – WIR is a serial/parallel input and output
register. It consists of two stages: a flip‐flop based serial shift stage and a latch
based update/decode stage. Every flip‐flop drives a latch. The latch retains
the current instruction when the register is fed with new data (instructions).
(instructions)

Optional Parallel Capture Inputs (WPI of TAM)

Serial Shift
Stage
CaptureWR
WSI S[k] S[1] S[0] WIR_WSO
ShiftWR
...
SelectWIR ... WRSTN
Update and Decode
UpdateWR WRCK
WDR_Cntrl

WBR_Cntrl

WBY_Cntrl
Core_Cntrl

CDR_Cntrl

DR_Select[0:log2n]
k3

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 WIR Timing Diagrams
WIR Shift and Update Operations

WRCK

SelectWIR

ShiftWR
Data Shift
UpdateWR

WIR Shift Register

WIR Update Register

Instruction Register Update

Instruction Decoding

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 15

Wrapper Boundary Register – WBR

• The Wrapper Boundary Register ‐ WBR lies at the core boundary, between the
input‐output pins and the internal core logic. It consists of the Wrapper
Boundary Cells ‐ WBC and contributes to the testing of the internal core logic
as wellll as the
h interconnects
i off the
h core with
i h other
h cores in
i the
h chip.
hi

sc wci

from chip WBC

0
to core
MUX

scan‐in
M

0
From previous WBC
MUX

or WSI 1
1 FF
clk scan‐out
To next WBC
wrapper input cell or WBR_WSO

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 Wrapper Boundary Register – WBR
The multiplexers of the WBR cells are controlled by the sc (scan) signal, which is
also used to control the core’s scan chains, and the wci (wco) signal for the input
cell (output cell). The value of the wci (wco) signal is defined by the decoding of
the instruction inside the WIR. In addition, the clock clk signal of the core is used
to drive the flip‐flop of the cell.

sc wco

from core WBC

0
to chip

MUX
scan‐in

M
0
From previous WBC
MUX

or WSI 1
1 FF
clk scan‐out
To next WBC
wrapper output cell or WBR_WSO

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 17

IEEE 1500 std. Instructions

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 18

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 The Core

Scan Chain 0
si[0:1] so[0:1]
Scan Chain 1

d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk

sc clk

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 19

IEEE 1500 Wrapper Compliant Core

m5 m9
Scan Chain 0
WPI[0:2] Scan Chain 1
m4 WPO[0:2]
m10
d[0] d[0]
m3 m6

d[1] d[1]
Core q[0] q[0]
d[2] d[2]
m2 m7
q[1] q[1]

d[3] d[3]
d[4] d[4] m8
m1 q[2] q[2]
sc clk
clk m11
sc WBY m12
WSI WIR WSO
Wrapper
WIP[0:5]

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 The WBYPASS Instruction

The mandatory WBYPASS instruction provides two non‐conflicting modes of

operation:
p the normal mode and the bypass
yp mode.
This instruction configures the WBCs for the normal mode of operation and in
parallel connects the WBY register between the WSI and WSO ports so that
during test operations the core is bypassed to provide fast test data access to
other cores in the chip.

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 21

Normal Mode of Operation – WBYPASS

Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 Serial Bypass – WBYPASS

Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 23

The WCORETESTS Instruction

The WCORETESTS instruction is utilized for the serial internal core testing.
This instruction connects the WBR register and the internal core scan chains to a
unified scan chain between the WSI and WSO ports.
Test data, from the test control unit (BIST or ΑΤΕ), are scanned‐in to the wrapper
input boundary cells of the WBR and the scan chains and they are applied to the
core’s logic. Next, the core’s responses are captured at the scan chains and the
wrapper output boundary cells of the WBR and they are scanned‐out to the test
control unit (BIST or ATE) for processing.

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 Serial InTest – WCORETESTS (Ι)
Scan‐‐in phase
Scan
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 25

Serial InTest – WCORETESTS (ΙI

(ΙI)
Test application
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 Serial InTest – WCORETESTS (ΙII
(ΙII))
Response Capture
& Scan‐
Scan‐out phase
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 27

The WCORETESTWS Instruction

The WCORETESTWS instruction is almost identical to the WCORETESTS

instruction. The difference is that the core scan chains are not utilized and onlyy
the WBR is exploited for the scan operations.

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 The WEXTESTS Instruction

The mandatory WEXTESTS instruction is utilized during the serial external testing
of the core interconnects with other cores in the chip.
p
This instruction provides controllability and observability over the glue logic
surrounding the core.
The instruction exclusively connects the WBR between the WSI and WSO ports.
The wrapper output boundary cells of the WBR are exploited to provide test
data, while the wrapper input boundary cells of the WBR are used to capture the
test responses. The test data are serially transferred between the test controller
(BIST or ΑΤΕ) and the WBR.

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 29

Serial ExTest – WEXTESTS (Ι)

Scan‐‐in phase
Scan
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 Serial ExTest – WEXTESTS (ΙI
(ΙI)
Test application
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 31

Serial ExTest – WEXTESTS (ΙII

(ΙII))
Response Capture
& Scan‐
Scan‐out phase
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 The WCORETEST Instruction

The WCORETEST instruction is utilized for the parallel internal core testing.
This instruction exploits the parallel (user defined) ΤΑΜ to scan‐in/out in parallel
test data
d to/from
/f the
h WBR and d the
h scan chains.
h i
The instruction connects the WBR between a dedicated input of the WPI port
and a dedicated output of the WPO port. Similarly, connects the scan chain (if it
is required) between dedicated inputs of the WPI port and dedicated outputs of
the WPO port.
The test data are concurrently scanned‐in from the test controller (BIST or ΑΤΕ)
to the wrapper input boundary cells of the WBR and the scan chains and they
are applied to the core logic. Next, the test responses are captured at the scan
chains and the wrapper output boundary cells of the WBR and then concurrently
scanned‐out to the test controller (BIST or ATE) for processing.

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 33

Parallel InTest – WCORETEST (Ι)

Scan‐‐in phase
Scan
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 Parallel InTest – WCORETEST (Ι
(ΙII)
Test application
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 35

Parallel InTest – WCORETEST (Ι

(ΙII
II))
Response Capture
& Scan‐
Scan‐out phase
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 The WEXTESTP Instruction

The WEXTESTP instruction is utilized for the parallel external testing of the core
interconnects with other cores in the chip. p
The instruction provides controllability and observability of the glue logic
surrounding the core.
The test data are scanned‐in in parallel from the test controller (BIST or ΑΤΕ) to
the wrapper output boundary cells of the WBR. The wrapper input boundary
cells of the WBR are used to capture the test responses which are scanned‐out
in parallel to the test controller (BIST or ΑΤΕ) for processing.

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 37

Parallel ExTest – WEXTESTP (Ι)

Test application
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

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 Parallel ExTest – WEXTESTP (Ι
(ΙII)
Response Capture
Scan Chain 0
WPI[0:2] Scan Chain 1
WPO[0:2]
d[0] d[0]

d[1] d[1]
Core q[0] q[0]
d[2] d[2]

q[1] q[1]

d[3] d[3]
d[4] d[4]
q[2] q[2]
sc clk
clk
sc WBY
WSI WIR WSO
Wrapper
WIP[0:5]

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 39

Instructions and MUX Settings

Pattern loaded WIR decoder signals to control

in the WIR the multiplexers

X = don’t care value

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 Parallel TAM Configurations
SoC SoC SoC
N WPI1
N1 WPI1 WPO1 N1
Core 1 Core 1 Core 1

WPO1
PI1
WP

WPO1

N N WPI2 N2 WPI2 N2
Core 2 Core 2 Core 2
WPO2
WPO2
WPI2

WPO2

N3 WPI3 WPO3 N3
Core 3
WPI3 Core 3 Core 3
WPO3
WPI3

WPO3
N
Multiplexed Daisychain Distributed

Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 41

IEEE 1500 Chip Architecture

from Source to Sink

User Defined Parallel TAM
WPI1 WPO1 WPIN WPON

IEEE 1500 Wrapper IEEE 1500 Wrapper

Functional Functional Functional Functional

Inputs 1 Outputs 1 Inputs N Outputs N
Core 1 Core N
...
WSI1 WSO1 ... WSIN WSON
WIR WIR

WIP[0:5]

JTAG & Test Controller

Serial TAM Serial TAM
SoC TMS
TDI TCK TRSTN TDO

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 References
• IEEE 1500 Standard for Embedded Core Test (http://grouper.ieee.org/groups/1500/).
• “Testing Embedded Core‐Based System Chips,” Y. Zorian, E.J. Marinissen and S. Dey, IEEE
Computer, June 1999.
• “Towards a Standard for Embedded Core Test,” E.J. Marinissen, Y. Zorian, R. Kapur, T.
Taylor and L. Whetsel, IEEE Int. Test Conference (ITC), Sept. 1999.
• “On Using IEEE P1500 SECT for Test Plug‐n‐Play,” E.J. Marinissen, R. Kapur and Y. Zorian,
IEEE Int. Test Conference (ITC), Oct. 2000.
• “System Chip Test: How will it Impact your Design?,” Y. Zorian and E.J. Marinissen, ACM
Design Automation Conference (DAC), 2000.
• “ETM10 Incorporates Hardware Segment of IEEE P1500,” T. McLaurin and S. Ghosh, IEEE
Design and
d Test off Computers, pp. 8‐13, May‐June 2002.
• “On IEEE P1500’s Standard for Embedded Core Test,” E.J. Marinissen, R. Kapur, M.
Lousberg, T. McLaurin, M. Ricchetti and Y. Zorian, Journal of Electronic Testing: Theory
and Applications (JETTA), vol. 18, pp. 365‐383, 2002.

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