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DFT Interview Questions 2

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Ranjit Kumar Rawani
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89 views

DFT Interview Questions 2

Uploaded by

Ranjit Kumar Rawani
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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6) Explain the structure of OCC?

Ans--> OCC uses internal PLL clock for generating clock pulses for test. During the OCC Stuck at
Testing ensures only one clock pulse is generated in the capture phase. Similarly, during at-
speed testing, the OCC ensures two clock pulses are generated in the capture phase, having a
frequency equal to frequency of the functional clock.
Therefore, all the test clocks in a scan friendly design is routed through an OCC, which controls
the clock operation in scan mode (both in stuck-at and at-speed testing) and bypasses the
functional clock in functional mode. OCC is capable of enabling Fast clock or Slow clock based on
Stuck at or At-speed requirement.
7) Is it possible to get more than two pulses? Max how many we can get? How to get three
pulses in ATPG through OCC? what change you will do to get three pulses? *
Ans-->YES. This is known as Fast Sequential ATPG. Maximum no. of pulses of OCC shift register is
6/8 or may be more also Based on OCC register Programming in the design.
8) what is fast sequential ATPG?
Ans--> getting more than two at speed pulses during capture (typical usage is ram sequential
ATPG). Using this at speed Coverage improvement can be done.
9) what is sequential depth in ATPG?
Ans -->Sequential Depth is the number of logic levels to detect the fault (0 -->1) at particular
node. Eg;- For LOC-2,LOS-1
10) What is the ATPG flow from tool point of view?
Ans-->1) Before Executing ATPG Flow, there is a need to modify or remove some Logic which
can't be understood by the ATPG Tool. For Example, Analog Modules, Power Cells, Sleep Cells
etc excluding Memories and Black Boxes.
2)Read ATPG Model/Libraries (Tetramax or Mentor), Scan Inserted netlist (*.v,*v.gz,*.gv).
3)By Using run_build, Tool will be in Build Mode where the flattening of the design. In this
process, tool can be able to find if some of the Modules are missing.
4)Define the Missing Modules by Adding Pin Constraints(add_pi_constraints).
5)Run DRCs by Run_drc, if design has no DRC voilations, it will go to Analysis Mode and
generates SPF/Test Proc File.
6)In Set_system_mode Analysis, Test Proc contains the settings required for ATPG. In Test_setup
file, all the Load_unload, Shift Procedures defined by specifying the Scan groups, Shift Cycles,
Time period etc.
7)Add Faults by using add_faults.
8)Run ATPG tool by run_atpg.
9)Write the patterns (Serial, Parallel,Chain) generated by ATPG Tool by write _patterns.
11) what is there in spf(tetramax) /test_protocol file (tessent)
Ans--> all the scan shift /load unload procedures are defined/scan structure - clock grouping *

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