Detailed explanation of common commands of

Tessent tool.
## 1. `read_design` command
1. **Function**
- This command is used to read the design file into the
Tessent environment. The design file can be in Verilog , VHDL
and other formats, which is the basis for subsequent DFT
operations.
2. **Syntax format and parameters**
- Basic format: `read_design [options] <design_file>`
- Common parameters:
- `-format <file_format>`: Specify the design file format ,
such as `-format verilog` for Verilog file format, `-format vhdl`
for VHDL file format.
- `-top <top_module_name>`: Specify the top-level module
name in the design, for example `-top my_top_module`. This
helps Tessent determine the hierarchical structure of the
design.

## 2. `write_design` command
1. **Function**
- Contrary to `read_design`, it writes the design processed by
Tessent to a file, which can be used to save files with DFT
structures (such as designs after scan chain insertion).
2. **Syntax format and parameters**
- Basic format: `write_design [options] <output_file>`
- Common parameters:
- `-format <file_format>`: Specifies the output file format,
such as `-format verilog` or `-format vhdl`.
- `-hierarchy <hierarchy_option>`: Specifies the hierarchy
representation in the output file, such as `-hierarchy flat` (flat
hierarchy) or `-hierarchy preserve` (retain the original
hierarchy).

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## 3. `set_fault_model` command
1. **Function**
- Set the fault model, which is an important prerequisite for
ATPG operation. Common fault models include stuck-at fault,
etc.
2. **Syntax format and parameters**
- Basic format: `set_fault_model [options]
<fault_model_type>`
- Common parameters:
- `-type <fault_type>`: For the stuck fault model, you can
further specify `-type stuck-at-0` (stuck at 0 fault) or `-type
stuck-at-1` (stuck at 1 fault), etc.
- `-coverage <coverage_requirement>`: Set the fault
coverage requirement, such as `-coverage 90` means that the
fault coverage is required to reach 90%.

## 4. `scan_insertion` command
1. **Function**
- Insert a scan chain into the design, convert ordinary triggers
into scan triggers and connect them into a scan chain, so as to
better control and observe the internal state in the test mode.
2. **Syntax format and parameters**
- Basic format: `scan_insertion [options]`
- Common parameters:
- `-design <design_name>`: Specify the design name to be
scan-inserted, such as `-design my_chip`.
- `-chain_length <length>`: Set the length of the scan chain,
for example `-chain_length 100`.
- `-scan_style <style>`: Specify the scan style, such as `-
scan_style mux - d` (multiplexed scan style).
- `-clock <clock_name>`: Determine the clock signal used by
the scan chain, such as `-clock test_clk`.

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## 5. `atpg` command
1. **Function**
- Automatic test pattern generation command, which
automatically generates test vectors based on the design
structure and the selected fault model to detect faults in the
design.
2. **Syntax format and parameters**
- Basic format: `atpg [options]`
- Common parameters:
- `-design <design_name>`: Specify the design name to be
ATPG operated, such as `-design my_design`.
- `-fault_model <model>`: Specify the fault model, such as `-
fault_model stuck` (fixed fault model).
- `-atpg_mode <mode>`: Determine the ATPG mode, such as
`-atpg_mode full` (full mode).
- `-max_patterns <number>`: Set the maximum number of
test patterns (test vectors), such as `-max_patterns 500`.

## 6. `simulate` command
1. **Function**
- Perform simulation test on the design. You can use the
generated test vectors to simulate the design to verify whether
the behavior of the design under the test conditions meets
expectations.
2. **Syntax format and parameters**
- Basic format: `simulate [options]`
- Common parameters:
- `-design <design_name>`: Specify the name of the design to
be tested, such as `-design my_circuit`.
- `-test_vector <vector_file>`: Specify the test vector file,
such as `-test_vector my_test_vector.tv`.
- `-simulator <simulator_name>`: If there are multiple
simulators to choose from, you can specify them through this
parameter, such as `-simulator QuestaSim`.

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 - `-output <output_file>`: Specify the output file of the
simulation results, such as `-output simulation_results.log`.

## VII. `add_pattern` command

1. **Function**
- Used to manually add test patterns (test vectors) to the test
set, which can supplement the automatically generated test
vector set.
2. **Syntax format and parameters**
- Basic format: `add_pattern [options] <input_pattern>`
- Common parameters:
- `-name <pattern_name>`: Name the added test pattern,
such as `-name special_case_pattern`.
- `-description <pattern_description>`: Provide a description
of the test pattern, such as `-description "This pattern is for
testing a corner case"`.

## 8. `report_fault_coverage` command
1. **Function**
- Generate a report on fault coverage, showing the proportion
of faults that can be detected by the current test set, which is
an important indicator for evaluating the effectiveness of the
test.
2. **Syntax format and parameters**
- Basic format: `report_fault_coverage [options]`
- Common parameters:
- `-detail <detail_level>`: Specifies the level of detail of the
report, such as `-detail high` (provides more detailed
information, including fault coverage of each module, etc.) or `-
detail low` (only provides overall fault coverage information).
- `-output <report_file>`: Specifies the file to which the
report will be output, such as `-output
fault_coverage_report.txt`.

## IX. `set_test_mode` command

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1. **Function**
- Set the test mode to determine the working mode of the
design during the test, such as normal test mode or special
debug test mode, etc.
2. **Syntax format and parameters**
- Basic format: `set_test_mode [options] <test_mode>`
- Common parameters:
- `-enable <feature>`: Enable specific test functions, such as
`-enable scan - test` (enable scan test function).

## 10. `set_clock` command

1. **Function**
- Used to set clock-related parameters, including the
definition of clock signals, clock domains, etc., which is very
important for scan chain operations and clock control during
testing.
2. **Syntax format and parameters**
- Basic format: `set_clock [options] <clock_spec>`
- Common parameters:
- `-name <clock_name>`: Specify the clock name, such as `-
name clk`.
- `-period <clock_period>`: Set the clock period, such as `-
period 10` (the unit depends on the design, which may be
nanoseconds, etc.).
- `-duty_cycle <duty_cycle_percentage>`: Set the duty cycle
of the clock, such as `-duty_cycle 50` (indicating a 50% duty
cycle).

## 11. `set_reset` command

1. **Function**
- Define the parameters related to the reset signal, such as
the name of the reset signal, the reset type (synchronous reset
or asynchronous reset), etc., which is critical for the reset
operation during the initialization and test process of the
design.

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2. **Syntax format and parameters**
- Basic format: `set_reset [options] <reset_spec>`
- Common parameters:
- `-name <reset_name>`: Specify the reset signal name, such
as `-name rst`.
- `-type <reset_type>`: Specify the reset type, such as `-type
async` (asynchronous reset) or `-type sync` (synchronous reset).

## 12. `set_io` command

1. **Function**
- Set the relevant properties of the input and output (IO) port,
including the direction of the IO (input, output or bidirectional),
electrical characteristics, etc.
2. **Syntax format and parameters**
- Basic format: `set_io [options] <io_spec>`
- Common parameters:
- `-name <io_name>`: Specify the name of the IO port, such
as `-name data_in`.
- `-direction <io_direction>`: Specify the IO direction, such as
`-direction input` (input port), `-direction output` (output port)
or `-direction inout` (bidirectional port).
- `-voltage <voltage_level>`: Specify the voltage level of the
IO port, such as `-voltage 3.3` (indicates 3.3V).

## 13. `set_power` command

1. **Function**
- Used to set power-related parameters, such as power
domain, power voltage, etc., which is important for power
consumption analysis of the design and power management
during testing.
2. **Syntax format and parameters**
- Basic format: `set_power [options] <power_spec>`
- Common parameters:
- `-domain <power_domain>`: Specify the power domain
name, such as `-domain core_power`.

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 - `-voltage <voltage_level>`: Set the power voltage, such as `-
voltage 1.8` (indicates 1.8V).

## 14. `set_operating_conditions` command

1. **Function**
- Set the operating conditions of the design, including
temperature range, process corner, etc. These conditions will
affect the performance and test results of the design.
2. **Syntax format and parameters**
- Basic format: `set_operating_conditions [options]
<operating_conditions>`
- Common parameters:
- `-temperature <temp_range>`: Specify the temperature
range, such as `-temperature - 40:125` (indicates the
temperature range of - 40°C to 125°C).
- `-process_corner <corner>`: Specify the process corner,
such as `-process_corner slow` (slow process corner) or `-
process_corner fast` (fast process corner).

## 15. `set_timing` command

1. **Function**
- Used to set the timing constraints of the design, including
the delay from clock to output, the setup and hold time from
input to clock, etc., to ensure that the design meets the timing
requirements.
2. **Syntax format and parameters**
- Basic format: `set_timing [options] <timing_spec>`
- Common parameters:
- `-clock_to_output <delay>`: Set the delay from clock to
output, such as `-clock_to_output 5` (the unit depends on the
design, it may be nanoseconds, etc.).
- `-input_to_clock_setup <setup_time>`: Set the setup time
from input to clock, such as `-input_to_clock_setup 3`.
- `-input_to_clock_hold <hold_time>`: Set the hold time
from input to clock, such as `-input_to_clock_hold 1`.

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## 16. `set_design_rule` command
1. **Function**
- Define design rules, such as minimum line width, minimum
spacing, etc. These rules help ensure the manufacturability and
reliability of the design during physical implementation.
2. **Syntax format and parameters**
- Basic format: `set_design_rule [options]
<design_rule_spec>`
- Common parameters:
- `-min_width <width>`: Specify the minimum line width,
such as `-min_width 0.18` (the unit depends on the design,
which may be microns, etc.).
- `-min_spacing <spacing>`: Set the minimum spacing, such
as `-min_spacing 0.2`.

## 17. `set_dft_rule` command

1. **Function**
- Set DFT-related rules, such as the maximum length limit of
the scan chain, the density requirements of the test points, etc.,
to ensure that the DFT structure meets the design and test
requirements.
2. **Syntax format and parameters**
- Basic format: `set_dft_rule [options] <dft_rule_spec>`
- Common parameters:
- `-scan_chain_max_length <length>`: Set the maximum
length of the scan chain, such as `-scan_chain_max_length 200`.
- `-test_point_density <density>`: Set the density
requirements of the test points, such as `-test_point_density
0.1` (indicates 10% test point density).

## 18. `set_debug_mode` command

1. **Function**

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 - Enable or set debug mode. In debug mode, you can get
more information about the internal state of the design, which
is helpful for fault diagnosis and debugging.
2. **Syntax format and parameters**
- Basic format: `set_debug_mode [options] <debug_mode>`
- Common parameters:
- `-enable <debug_feature>`: Enable specific debug features,
such as `-enable scan - debug` (enable scan debug function).

## 19. `set_verification_mode` command

1. **Function**
- Set the verification mode and determine the verification
strategy and method used in the verification process, such as
formal verification, functional verification, etc.
2. **Syntax format and parameters**
- Basic format: `set_verification_mode [options]
<verification_mode>`
- Common parameters:
- `-type <verification_type>`: Specify the verification type,
such as `-type formal` (formal verification) or `-type functional`
(functional verification).

## 20. `set_optimization_mode` command

1. **Function**
- Determine the optimization mode, which is used to optimize
the design during the design process, such as area optimization,
power optimization, etc.
2. **Syntax format and parameters**
- Basic format: `set_optimization_mode [options]
<optimization_mode>`
- Common parameters:
- `-type <optimization_type>`: Specify the optimization type,
such as `-type area` (area optimization) or `-type power` (power
optimization).

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 - `-priority <priority_level>`: Set the optimization priority,
such as `-priority high` (high priority) or `-priority low` (low
priority).

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