MPU and Memory
: Data
Memory
PIC18F
Programming Model
Divided into two groups 1- (ALU) and Registers
2 (SFRs)take From Data (File) Memory
ALU: consist of 1- 16-bit Instructions Decoder
2- 8-bit Data Table Latch
3- STATUS: Flag Register 5 individual bits called flags
[Link] (W): Working Register 8-bit
Accumulator
b. Product: -16-bit Product of 8-bit by 8-bit
Multiply
N
(Negative Flag) Set when bit B7 is one as the
result of an arithmetic/logic operation
OV (Overflow Flag) Set when result of an
operation of signed numbers goes beyond 7-bits
Z (Zero Flag)Set when result of an operation is
zero
DC (Digit Carry Flag) (Half Carry) Set when carry
generated from Bit3 to Bit4 in an arithmetic
operation
C (Carry Flag) Set when an addition generates a
carry (out)
Registers
1. (PC) 21-bit ,
2. Table Pointer 21-bit register used as a pointer
to copy bytes
3. Stack Pointer (SP)-5-bit register used to point
to the stack
4. Stack:- 31 registers used for temporary
storage of memory addresses during execution
of a subroutines
5. BSR: Bank Select Register (0H to FH)-4-bit
Register Provides upper 4-bits of 12-bit
address of Data Memory
6. FSR: File Select Registers
FSR0, FSR1, and FSR2
FSR: composed of two 8-bit registers
FSRH and FSRL
2- Used as pointers for Data Memory
Holds 12-bit address of data register
SFRs: Table 3-1
Data registers associated with I/O ports, support
devices, and processes of data transfer
I/O Ports (A to E)
Interrupts
EEPROM
Serial I/O
Timers
Capture/Compare/PWM (CCP)
Analog-to-Digital (A/D) Converter
PIC18 Instruction Set
Divided into seven groups
1. Move (Data Copy) and Load
2. Arithmetic
3. Logic
4. Program Redirection (Branch/Jump)
5. Bit Manipulation
6. Table Read/Write
7. Machine Control
Addressing Modes
It is a Method of specifying of an operand
1-Immediate (Literal) addressing
The operand is a number that follows the
opcode
2- Direct addressing
The address of the operand is a part of the
instruction
3-Indirect addressing
An address is specified in a register
(pointer) and the MPU looks up the address in
that register
Move and Load Instructions
Note:- Each instruction has two parts: Opcode and Operand
When instructions copy data from one register to another, the
source is not modified In general, these instructions do not
affect flags Except CLRF and MOVF
Arithmetic Instructions
NOTE:- Arithmetic instructions Can perform
operations on W and 8-bit literals
Save the result in W
Can perform operations an W and F
Save the result in W or F
In general, affect all flags
Logic Instructions
Note:- Logic instructions Can perform operations on
W and 8-bit literals Save the result in W
Can perform operations an W and F,Save the result
in W or F, In general, affect only two flags: N and Z
Branch Instructions
Branch Example
Addr Label Opc Operand Comment
ess ode
000020 START: MOVLW BYTE1 ;Load BYTE1 into W
000022 MOVWF REG0 ;Save into REG0
000024 MOVLW BYTE2 ;Load BYTE2 into W
000026 MOVWF REG1 ;Save into REG1
000028 ADDWF REG0,W ;Add REG0 to REG1
00002A BNC SAVE ;Branch if no carry
00002C MOVLW 0x00 ;Clear W
00002E SAVE: MOVWF REG2 ;Save Result
000030 SLEEP
Call and Return Instructions
Note:- Eight conditional relative branch instructions
Based on four flags
Range is -128 ≤ n ≤ +127 (words)
Unconditional relative branch instruction
Range is -1024 ≤ nn ≤ +1023 (words)
If the operand is positive, the jump is forward
If negative, the jump is backward
Bit Manipulation Instructions
Note:- [Link] bit in a File (data) register,
Set, reset, or complemented
2,-There are two types of rotate instructions
8-bit and 9-bit (include C)
3.- Any file (data) register can be rotated left
or right Saved in W or F
Test and Skip Instructions
Increment/Decrement and Skip
Next Instruction
Note:-Any File (data) register or single bit in a File
(data) register can be tested for 0
A File (data) register can be compared with W
for equality, greater than, and less than
A File (data) register can be incremented or
decremented and tested for 0
If a condition is met, the next instruction is
skipped (no flags are affected)
Table Read/Write Instructions
Machine Control Instructions
Instruction Format
Instruction Format
Illustration: Addition
Address Hex Opcode Operand Comments
002020 0E37 MOVLW 0x37 ;Load first byte in W
0022 6E00 MOVWF REG0 ;Save first byte in
REG0
0024 0E92 MOVLW 0x92 ;Load second byte
in W
0026 6E01 MOVWF REG1 ;Save second byte
in REG1
0028 2400 ADDWF REG0,W ;Add bytes and
save sum in W
002A 6E02 MOVWF REG2 ;Save sum in
REG2
002C 0003 SLEEP ;Power Down
Bus Contents
Execution of the instruction: MOVLW 0x37
Pipeline Fetch and Execution
