PIC18F Programming Model and Instruction Set

ELEC 330 Digital Systems Engineering Dr. Ron Hayne

Images Courtesy of Ramesh Gaonkar and Delmar Learning

Review: MPU and Memory

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Review: Data Memory

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PIC18F Programming Model

The representation of the internal architecture of a microprocessor, necessary to write assembly language programs Divided into two groups

Arithmetic Logic Unit (ALU) and Registers

From Microprocessor Unit (MPU) From Data (File) Memory

Special Function Registers (SFRs)

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PIC18F Programming Model

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ALU
Instruction Decoder

16-bit Instructions
8-bit Data 5 individual bits called flags

Table Latch

STATUS: Flag Register

WREG (W): Working Register

8-bit Accumulator
16-bit Product of 8-bit by 8-bit Multiply
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Product

Flags in Status Register

N (Negative Flag)

Set when bit B7 is one as the result of an arithmetic/logic operation

Set when result of an operation of signed numbers goes beyond 7-bits

OV (Overflow Flag)

Z (Zero Flag)

Set when result of an operation is zero

Set when carry generated from Bit3 to Bit4 in an arithmetic operation Set when an addition generates a carry (out)
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DC (Digit Carry Flag) (Half Carry)

C (Carry Flag)

Registers
Program Counter (PC) 21-bit register functions as a pointer to Program Memory during program execution Table Pointer 21-bit register used as a pointer to copy bytes between Program Memory and data registers Stack Pointer (SP) 5-bit register used to point to the stack Stack 31 registers used for temporary storage of memory addresses during execution of a subroutines
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Registers
BSR: Bank Select Register (0H to FH)

4-bit Register

Provides upper 4-bits of 12-bit address of Data Memory

FSR: File Select Registers

FSR0, FSR1, and FSR2 FSR: composed of two 8-bit registers

FSRH and FSRL

Used as pointers for Data Memory

Holds 12-bit address of data register

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Special Function Registers

SFRs: Table 3-1

Data registers associated with I/O ports, support devices, and processes of data transfer
I/O Ports (A to E) Interrupts EEPROM Serial I/O Timers Capture/Compare/PWM (CCP) Analog-to-Digital (A/D) Converter

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PIC18 Instruction Set

Includes 77 instructions

73 one word (16-bit) long 4 two words (32-bit) long

Divided into seven groups

Move (Data Copy) and Load Arithmetic Logic Program Redirection (Branch/Jump) Bit Manipulation Table Read/Write Machine Control

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Addressing Modes
Method of specifying of an operand

Immediate (Literal) addressing

The operand is a number that follows the opcode

Direct addressing

The address of the operand is a part of the instruction

An address is specified in a register (pointer) and the MPU looks up the address in that register

Indirect addressing

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Move and Load Instructions

MOVLW MOVLW MOVWF 8-bit 0xF2 F,a ;Load an 8-bit Literal into WREG ;Load F2H into W ;Copy WREG into File (Data) Reg. ;If a = 0, F is in Access Bank ;If a = 1, Bank is specified by BSR ;Copy W into F Reg25H ;Alternate format ;Copy from one File Reg. to ;another File Reg. ;Copy F Reg20H into Reg30H
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MOVWF MOVWF MOVFF MOVFF

0x25,0 0x25 fs,fd 0x20,0x30

Move and Load Instructions

MOVF F,d,a ;Copy F into itself or W ;If d = 0 (or W), destination is W ;If d = 1 (or F), destination is F ;Affects N & Z flags ;Copy F Reg25H into W ;Alternate format ;Clear F Reg. ;Sets Z flag ;Clear Reg25H ;Sets all bits to 1 in F Reg.
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MOVF MOVF CLRF CLRF SETF

0x25,0,0 0x25,W F,a 0x25 F,a

Points to Remember
Each instruction has two parts

Opcode and Operand

When instructions copy data from one register to another, the source is not modified In general, these instructions do not affect flags

Except CLRF and MOVF

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Arithmetic Instructions
ADDLW ADDLW ADDWF 8-bit 0x32 F,d,a ;Add 8-bit number to W & set flags ;Add 32H to W ;Add W to F & set flags ;Save result in W if d = 0 (or W) ;Save result in F if d = 1 (or F) ;Add W to REG20H and ;save result in W ;Alternate format ;Add W to REG20H and ;save result in REG20H ;Alternate format
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ADDWF ADDWF ADDWF ADDWF

0x20,0 0x20,W 0x20,1 0x20,F

Arithmetic Instructions
ADDWFC SUBLW SUBWF SUBWFB INCF DECF NEGF F,d,a 8-bit F,d,a F,d,a F,d,a F,d,a F,a ;Add W to F with carry ;and save result in W or F ;Subtract W from literal ;Subtract W from F ;Subtract W from F with borrow ;Increment F ;Decrement F ;Take 2s Complement of F

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Arithmetic Instructions
MULLW MULWF DAW 8-bit F,a ;Multiply 8-bit Literal and W ;Save result in PRODH:PRODL ;Multiply W and F ;Save result in PRODH:PRODL ;Decimal adjust W for BCD ;Addition

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Points to Remember
Arithmetic instructions

Can perform operations on W and 8-bit literals

Save the result in W

Can perform operations an W and F

Save the result in W or F

In general, affect all flags

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Logic Instructions
COMF ANDLW ANDWF F,d,a 8-bit F,d,a ;Complement (NOT) F ;and save result in W or F ;AND Literal with W ;AND W with F and ;save result in W or F ;Inclusive OR Literal with W ;Inclusive OR W with F ;and save result in W or F ;OR W with REG12H and ;save result in REG12H ;Exclusive OR Literal with W ;Exclusive OR W w/ F ;and save result in W or F
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IORLW IORWF
IORWF XORLW XORWF

8-bit F,d,a
0x12,F 8-bit F,d,a

Points to Remember
Logic instructions

Can perform operations on W and 8-bit literals

Save the result in W

Can perform operations an W and F

Save the result in W or F

In general, affect only two flags: N and Z

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Branch Instructions
BC BC BC BNC BZ BNZ BN BNN BOV BNOV BRA ;Branch if C flag = 1, + or 64 Words ;to PC+2+2n 5 ;Branch on Carry to PC+2+10 Label ;Alternate: Branch to Label n ;Branch if C flag = 0 n ;Branch if Z flag = 1 n ;Branch if Z flag = 0 n ;Branch if N flag = 1 n ;Branch if N flag = 0 n ;Branch if OV flag = 1 n ;Branch if OV flag = 0 nn ;Branch always, + or 512 Words n
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Branch Example
Address Label 000020 000022 000024 000026 000028 00002A 00002C Opcode MOVWF MOVLW MOVWF ADDWF BNC MOVLW Operand BYTE1 REG0 BYTE2 REG1 REG0,W SAVE 0x00 Comment ;Load BYTE1 into W ;Save into REG0 ;Load BYTE2 into W ;Save into REG1 ;Add REG0 to REG1 ;Branch if no carry ;Clear W START: MOVLW

00002E
000030

SAVE:

MOVWF
SLEEP

REG2

;Save Result

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Call and Return Instructions

RCALL CALL nn 20-bit,s ;Relative Call subroutine ;within + or 512 words ;Call subroutine ;If s = 1, save W, STATUS, BSR ;Return subroutine ;If s = 1, retrieve W, STATUS, BSR ;Return from interrupt ;If s = 1, retrieve W, STATUS, BSR

RETURN s RETFIE s

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Points to Remember
Eight conditional relative branch instructions

Based on four flags Range is 64 words

Range is 512 words

Unconditional relative branch instruction

If the operand is positive, the jump is forward If negative, the jump is backward

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Bit Manipulation Instructions

BCF BCF BSF BTG RLCF RLNCF F,b,a ;Clear bit b of F, b = 0 to 7 0x2,7 ;Clear bit 7 of Reg2 F,b,a ;Set bit b of F, b = 0 to 7 F,b,a ;Toggle bit b of F, b = 0 to 7 F,d,a ;Rotate bits left in F through ;carry and save in W or F F,d,a ;Rotate bits left in F ;and save in W or F F,d,a ;Rotate bits right in F through ;carry and save in W or F F,d,a ;Rotate bits right in F ;and save in W or F
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RRCF RRNCF

Points to Remember
Any bit in a File (data) register

Set, reset, or complemented

8-bit and 9-bit (include C) Any file (data) register can be rotated left or right

There are two types of rotate instructions

Saved in W or F

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Test and Skip Instructions

BTFSC BTFSC BTFSS CPFSEQ CPFSGT CPFSLT TSTFSZ F,b,a ;Test bit b in F and skip the ;next instruction if bit is cleared (bit=0) 0x2,7 ;Test bit B7 in REG2 ;if B7=0 then skip next instruction F,b,a ;Test bit b in F and skip the ;next instruction if bit is set (bit=1) F,a ;Compare F with W, skip if F = W F,a ;Compare F with W, skip if F > W F,a ;Compare F with W, skip if F < W F,a ;Test F, skip if F = 0

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Increment/Decrement and Skip Next Instruction

DECFSZ F,d,a ;Decrement F and skip the ;next instruction if F = 0 DECFSNZ F,d,a ;Decrement F and skip the ;next instruction if F 0 INCFSZ F,d,a ;Increment F and skip the ;next instruction if F = 0 INCFSNZ F,d,a ;Increment F and skip the ;next instruction if F 0

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Points to Remember
Any File (data) register or single bit in a File (data) register can be tested for 0 A File (data) register can be compared with W for equality, greater than, and less than A File (data) register can be incremented or decremented and tested for 0 If a condition is met, the next instruction is skipped (no flags are affected)
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Table Read/Write Instructions

TBLRD* ;Read Program Memory pointed by TBLPTR ;into TABLAT TBLRD*+ ;Read Program Memory pointed by TBLPTR ;into TABLAT and increment TBLPTR TBLRD*- ;Read Program Memory pointed by TBLPTR ;into TABLAT and decrement TBLPTR TBLRD+* ;Increment TBLPTR and Read Program ;Memory pointed by TBLPTR into TABLAT

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Table Read/Write Instructions

TBLWT* ;Write TABLAT into Program Memory pointed ;by TBLPTR TBLWT*+ ;Write TABLAT into Program Memory pointed ;by TBLPTR and increment TBLPTR TBLWT*- ;Write TABLAT into Program Memory pointed ;by TBLPTR and decrement TBLPTR TBLWT+* ;Increment TBLPTR and Write TABLAT into ;Program Memory pointed by TBLPTR

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Machine Control Instructions

CLRWDT RESET SLEEP NOP ;Clear Watchdog Timer ;Reset all registers and flags ;Go into standby mode ;No operation

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Instruction Format
The PIC18F instruction format divided into four groups

Byte-Oriented operations Bit-Oriented operations Literal operations Branch operations

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Instruction Format
Byte-oriented instruction ADDWF F, d, a
ADDWF 0x1,F ;Add W to REG1, save in REG1

Bit-oriented instruction BCF F, b, a

BCF 0x15,7 ;Clear bit7 in REG15H

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Instruction Format
Literal instruction MOVLW k
MOVLW 0x7F ;Load 7FH into W

Branch instruction BC n
BC 0x15 ;Branch if carry +15H words

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Illustration: Addition
Problem Statement

Load two bytes (37H and 92H) in registers REG0 and REG1 Add the bytes and store the sum in REG2
Opcode MOVLW MOVWF Operand 0x37 REG0 Comments ;Load first byte in W ;Save first byte in REG0

Address Hex 0020 0022 0E37 6E00

0024
0026 0028 002A 002C

0E92
6E01 2400 6E02 0003

MOVLW
MOVWF ADDWF MOVWF SLEEP

0x92
REG1 REG0,W REG2

;Load second byte in W

;Save second byte in REG1 ;Add bytes and save sum in W ;Save sum in REG2 ;Power Down

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Bus Contents
Execution of the instruction: MOVLW 0x37

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Pipeline Fetch and Execution

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