Computer Architecture

The Processor: Datapath

2
Datapath

Applications
Software Programming Languages,
Operating Compilers,Operating
System Systems,
Software Engineering
Compiler Firmware
Instruction Set Architecture
Processor Memory organization I/O system
PART 2
Hardware

Datapath & Control

Digital Design PART 1

Circuit Design
Electrical and /or
Layout Electronic Engineering
Road Map: Part II
Performance

◼ Processor Datapath
Assembly Language
❑ Generic Execution Stages
Processor: ❑ MIPS Execution Stages
Datapath
❑ Constructing Datapath
Processor:
Control

Pipelining

Cache

Processor: Datapath
4
Building a Processor: Datapath & Control
➢ Two major components for a processor:

➢ Datapath
• Collection of components that process data
• Performs the arithmetic, logical and memory operations

➢ Control
• Tells the datapath, memory, and I/O devices what to do
according to program instructions
5
MIPS Processor: Implementation
➢ Simplest possible implementation of a subset of the
core MIPS ISA:
• Arithmetic and Logical operations
▪ add, sub, and, or, addi, andi, ori, slt
• Memory data transfer instructions
▪ lw, sw
• Control flow (Branches)
▪ beq, bne

➢ Shift instructions (sll, srl) and J-type instructions

(j) will not be discussed:
• Left as exercises
6
Recap: Instruction Execution Cycle
➢ Fetch
Instruction
Fetch
• Get instruction from memory
• Address is in Program Counter (PC) Register
Instruction
➢ Decode
Next Instruction

Decode
• Identify which operation is required
Operand
Fetch ➢ Operand Fetch
• Get operand(s) needed for operation
Execute
➢ Execute
Result • Perform the required operation
Write
➢ Result Write (WriteBack)
• Store the result of the operation
7
5-STAGE MIPS EXECUTION

add $3, $1, $2 lw $3, 20( $1 ) beq $1, $2, label

Fetch Read inst. at [PC] Read inst. at [PC] Read inst. at [PC]

Decode &
o Read [$1] as opr1 o Read [$1] as opr1 o Read [$1] as opr1
Operand
o Read [$2] as opr2 o Use 20 as opr2 o Read [$2] as opr2
Fetch
Taken = (opr1 == opr2 )?
ALU Result = opr1 + opr2 MemAddr = opr1 + opr2
Target = PC + Label*
Memory Use MemAddr to read from
Access memory
Result if (Taken)
Result stored in $3 Memory data stored in $3
Write PC = Target

◼ opr = Operand
◼ MemAddr = Memory Address
◼ * Target = PC + 4 + (imm x 4)
8
Let's Build a MIPS Processor
➢ What we are going to do:
• Look at each stage closely, figure out the requirements and processes
• Sketch a high level block diagram, then zoom in for each elements
• With the simple starting design, check whether different type of
instructions can be handled:
▪ Add modifications when needed

➔ Study the design from the viewpoint of a designer, instead of a

"tourist”
9
Fetch Stage: Requirements
➢ Instruction Fetch Stage:
1. Use the Program Counter (PC) to fetch the instruction from memory
▪ PC is implemented as a special register in the processor

2. Increment the PC by 4 to get the address of the next instruction:

▪ How do we know the next instruction is at PC+4?
▪ Note the exception when branch / jump instruction is executed

➢ Output to the next stage (Decode):

• The instruction to be executed
10
Fetch Stage: Block Diagram

A simple
adder
Add
4

PC Read address

Decode Stage
Instruction
Instruction

Instruction
memory

A register
Memory which
stores program
instructions
11
Element: Instruction Memory
➢ Storage element for the instructions
Instruction Address
• Sequential circuit
• Has an internal state that stores information Instruction

• Clock signal is assumed and not shown

Instruction
➢ Supply instructions given the address Memory

• Given instruction address M as input, the memory outputs Memory

the content at address M ………..
2048 add $3, $1, $2
2052 sll $4, $3, 2
• Conceptual diagram of the memory layout is given on the 2056 andi $1, $4, 0xF

…… ………..
right ➔
12
Element: Adder
➢ Combinational logic to implement the
addition of two numbers
A
➢ Inputs: A+B
Add Sum
• Two 32-bit numbers A, B
➢ Output: B
• Sum of the input numbers, A + B

➢ Just a 32-bit version of the adder discussed

in first part of the course
13
The Idea of Clocking
➢ It seems that we are reading and updating the PC at the
same time:
• How can it works properly?
➢ Clock operation:
• PC is read during the clock period and it is updated with PC+4 at
the next rising clock edge

Add
4
Time
PC Read
In address Clk
Instruction
PC 100 104 108 112
Instruction
memory
In 104 108 112 116
14
Decode Stage: Requirement
➢ Instruction Decode Stage:
• Gather data from the instruction fields:
1. Read the opcode to determine instruction type and field lengths
2. Read data from all necessary registers
▪ Can be two (e.g. add), one (e.g. addi) or zero (e.g. j)

➢ Input from previous stage (Fetch):

• Instruction to be executed

➢ Output to the next stage (Execute):

• Operation and the necessary operands
15
Decode Stage: Block Diagram
Register
Number
Data
5 Read Read
register 1
data 1

Execute Stage
Fetch Stage

5 Read
Inst. register 2 Register
File Operands
5 Write
register
Read
data 2

Collection of
registers, known as
register file
16
Element: Register File
➢ A collection of 32 registers:
• Each 32-bit wide and can be read / written by specifying register number
• Read at most two registers per instruction
• Write at most one register per instruction
➢ RegWrite is a control signal to indicate:
• Writing of register
• 1(True) = Write, 0 (False) = No Write

5 Read Read
register 1 data 1
Register 5 Read
Number register 2 Register Data
File
5 Write
register
Read
data 2
Write
Data
data

RegWrite
17
Decode Stage: R-Type Instruction
add $8, $9, $10
opcode
000000
31:26
25:21

01001

Inst [25:21]
5 Read content of
rs

Read
register 1 data 1
register $9
5 Read
Register
20:16

01010

register 2
rt

File
5 Write
register content of
Read
15:11

01000

data 2
Write register $10
rd

data
shamt
00000
10:6

RegWrite
Result to be
stored Notation:
100000
funct
5:0

(produced by later Inst [Y:X]

stage) = bits X to Y in Instruction
18
Decode Stage: I-Type Instruction
addi $21, $22, -50
opcode
001000
31:26
25:21

10110

Inst [25:21]
5 Read Content of
rs

Read
register 1 data 1
register $22
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
Read
data 2
1111 1111 1100 1110

Write
data
Immediate
15:0

RegWrite

Problems:
- Destination $21 is in the "wrong position"
- Read Data 2 is an immediate value, not from register
19

Decode Stage: Choice in Destination

addi $21, $22, -50
opcode
001000
31:26
25:21

10110

Inst [25:21]
5 Read
rs

Read
register 1 data 1
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
M Read
data 2
1111 1111 1100 1110

U Write
data
Inst [15:11] X
Immediate
15:0

RegDst
Solution (Wr. Reg. No.):
RegDst: Use a multiplexer to choose the
A control signal to choose correct write register number
either Inst[20:16] or Inst[15:11]
as the write register number
based on instruction type
20
Recap: Multiplexer
➢ Function:
• Selects one input from multiple input lines Control
m

➢ Inputs: in0
. M
• n lines of same width . U out
. X
inn-1

➢ Control:
• m bits where n = 2m Control=0 → select in0
Control=3 → select in3
➢ Output:
• Select ith input line if control=i
21
Decode Stage: Choice in Data 2
opcode addi $21, $22, -50
001000
31:26
25:21

10110

Inst [25:21]
5 Read
rs

Read
register 1 data 1
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
M Read
data 2 M
1111 1111 1100 1110

U Write
Inst [15:11] data U
X
Immediate

X
RegWrite
15:0

RegDst
ALUSrc ALUSrc:
Inst [15:0] 16 Sign 32
A control signal
Extend
to choose either
"Read data 2" or
Solution (Rd. Data 2): the sign extended
Use a multiplexer to choose the correct operand 2. Inst[15:0] as the
Sign extend the 16-bit immediate value to 32-bit second operand
22
Decode Stage: Load Word Instruction
➢ Try it out: "lw $21, -50($22)"
• Do we need any modification?
opcode
100011
31:26
25:21

10110

Inst [25:21]
5 Read
rs

Read
register 1 data 1
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
M Read
data 2 M
1111 1111 1100 1110

U Write
Inst [15:11] data U
X
Immediate

X
RegWrite
15:0

RegDst
Inst [15:0] Sign 32
ALUSrc
16
Extend
23
Decode Stage: Branch Instruction
➢ Example: "beq $9, $0, 3"
• Need to calculate branch outcome and target at the same time!
opcode • We will tackle this problem in the ALU Stage
000100
31:26
25:21

01001

Inst [25:21]
5 Read
rs

Read
register 1 data 1
5 Read
20:16

00000

register 2 Register
rt

5 Write File
register
M Read
data 2 M
0000 0000 0000 0011

U Write
Inst [15:11] data U
X
Immediate

X
RegWrite
15:0

RegDst
Inst [15:0] Sign 32
ALUSrc
16
Extend
24
Decode Stage: Summary

Inst [25:21]
5 Read Read
register 1 data 1
Operand 1
5 Read
register 2

5 Write
Registers
Inst[31:0] M register
Read

U Write
data 2 M
Inst [15:11]
X
data U Operand 2
X
RegWrite
RegDst
Inst [15:0] Sign 32
ALUSrc
16
Extend
25
ALU Stage: Requirement
➢ Instruction ALU Stage:
• ALU = Arithmetic-Logic Unit
• Perform the real work for most instructions here
▪ Arithmetic (e.g. add, sub), Shifting (e.g. sll), Logical (e.g. and, or)
▪ Memory operation (e.g. lw, sw): Address calculation
▪ Branch operation (e.g. bne, beq): Perform register comparison and
target address calculation
➢ Input from previous stage (Decode):
• Operation and Operand(s)
➢ Output to the next stage (Memory):
• Calculation result
26
ALU Stage: Block Diagram

Memory Stage
Decode Stage
ALU
result
Operands ALU

Logic to perform
arithmetic and
logical operations
Element: Arithmetic Logical Unit
4
ALUcontrol
ALU (Arithmetic-logical unit) A
(A op B) == 0?
Combinational logic to implement arithmetic and isZero?
logical operations ALU
ALU
result
Inputs: B A op B
Two 32-bit numbers

ALUcontrol Function
Control: 0000 AND
4-bit to decide the particular operation 0001 OR
0010 add

Outputs: 0110 subtract

Result of arithmetic/logical operation 0111 slt

A 1-bit signal to indicate whether result is zero 1100 NOR

27
28
ALU Stage: Non-Branch Instructions
➢ We can handle non-branch instructions easily:
add $8, $9, $10
opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21]
5 Read
rs

Read 4
register 1 data 1
5 Read
isZero?
20:16

01010

register 2
rt

Register ALU
5 Write File ALU
register result
M Read
15:11

01000

U Write
data 2 M
rd

Inst [15:11] data U

X
X
shamt
00000

RegWrite
10:6

RegDst ALUSrc
Inst [15:0] 16 Sign 32 ALUcontrol:
100000
funct

Extend
5:0

Set using opcode + funct

field (more in next lecture)
29
ALU Stage: Branch Instructions
➢ Branch instruction is harder as we need to perform two
calculations:

➢ Example: "beq $9, $0, 3"

1. Branch Outcome:
▪ Use ALU unit to compare the register
▪ The 1-bit "isZero?" signal is enough to handle equal / not equal check

2. Branch Target Address:

▪ Introduce additional logic to calculate the address
▪ Need PC (from Fetch Stage)
▪ Need Offset (from Decode Stage)
30 Complete ALU Stage

E.g. "beq $9, $0, 3"

PC Add
4
M
U
Add X
Left Shift PCSrc:
2-bit Control Signal
opcode
000100

PCSrc
31:26

to select
between
ALUcontrol (PC+4) or
25:21

01001

Inst [25:21] Branch Target

5 Read
rs

Read 4
register 1 data 1
5 Read
Register isZero?
20:16

00000

register 2
rt

File ALU
5 Write ALU
register result
M Read
0000 0000 0000 0011

U Write
data 2 M
Inst [15:11] data U
X
Immediate

X
RegWrite
15:0

RegDst
Inst [15:0] Sign 32
ALUSrc
16
Extend
31
Memory Stage: Requirement
➢ Memory Access Stage:
• Only the load and store instructions need to perform operation
in this stage:
▪ Use memory address calculated by ALU Stage
▪ Read from or write to data memory
• All other instructions remain idle
▪ Result from ALU Stage will pass through to be used in Result Store stage if
applicable
➢ Input from previous stage (ALU):
• Computation result to be used as memory address (if
applicable)
➢ Output to the next stage (Result Write):
• Result to be stored (if applicable)
32
Memory Stage: Block Diagram
MemWrite

Result Store Stage

Address
ALU Stage

Read
Result Data
Write
Data
Data
Memory

MemRead

Memory which stores

data values
Element: Data Memory
Storage element for the data of a program
MemWrite

Inputs: Address

Memory Address Read

Data
Write
Data to be written (Write Data) for store instructions Data
Data
Control: Memory

Read and Write controls; only one can be asserted at any

point of time MemRead

Output:
Data read from memory (Read Data) for load instructions

33
34
Memory Stage: Load Instructions
➢ Only relevant parts of Decode & ALU Stage are shown
opcode
000100
100011
lw $21, -50($22)
31:26

ALUcontrol
25:21

01001
10110

Inst [25:21] 4
5
rs

RR1 RD1
5
RR2 MemWrite
20:16

00000
10101
rt

Registers ALU
5 WR ALU
M Address
result
RD2
0000 1111
1111

U M Data
WD
Inst [15:11]
X U Memory
0000 1100
Immediate

X Read
RegWrite
15:0

Data
Write
0000 1110

RegDst Data
ALUSrc
Inst [15:0] 16 Sign 32
MemRead
0011

Extend
35
Memory Stage: Store Instructions
➢ Need Read Data 2 (Decode) as the Write Data
sw $21, -50($22)
opcode
000100
101011
31:26

ALUcontrol
25:21

01001
10110

Inst [25:21] 4
5
rs

RR1 RD1

5
RR2 MemWrite
20:16

00000
10101

Registers ALU
rt

5 WR ALU
M Address
result
RD2 M
0000 1111
1111

U Data
WD
Inst [15:11] U Memory
X
0000 1100

X
Immediate

Read
RegWrite
15:0

Data
Write
0000 1110

RegDst Data
Inst [15:0] 16 Sign 32
MemRead
0011

Extend
36

Memory Stage: Non-Memory Instructions

➢ Add a multiplexer to choose the result to be stored
opcode add $8, $9, $10
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21] 4
5
rs

RR1 RD1

5 MemWrite
RR2
20:16

01010

Registers ALU
rt

5 WR
ALU
Address
M RD2
result
15:11

01000

U M Data
rd

WD
U Memory
X
Inst [15:11] X Read
shamt
00000

RegWrite
10:6

Data M
Write
RegDst Data U
Inst [15:0] 16 Sign 32 X
100000
funct

Extend
5:0

MemToReg:
A control signal to indicate
whether result came from
memory or ALU unit
37
Result Write Stage: Requirement
➢ Register Write Stage:
• Most instructions write the result of some
computation into a register
▪ Examples: arithmetic, logical, shifts, loads, set-less-than
▪ Need destination register number and computation result
• Exceptions are stores, branches, jumps:
▪ There are no result to be written
➔These instructions remain idle in this stage

➢ Input from previous stage (Memory):

• Computation result either from memory or ALU
38
Result Write Stage: Block Diagram
5 Read Read
register 1

Memory Stage
data 1
5 Read
register 2

5 Write Registers
register
Read
data 2
Result Write
data

➢ Result Write stage has no additional element:

• Basically just route the correct result into register file
• The Write Register number is generated way back in
the Decode Stage
39
Result Write Stage: Routing
add $8, $9, $10
opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21] 4
5
rs

RR1 RD1
5 MemWrite
RR2
20:16

01010
rt

Registers ALU
5 WR ALU
M Address
result
15:11

01000

RD2 M
U Data
rd

WD MemToReg
X U Memory
Inst [15:11]
X Read
shamt
00000
10:6

RegWrite Data M
Write
Data U
Inst [15:0] Sign X
100000
funct

Extend
5:0
40
The Complete Datapath!
➢ We have just finished "designing" the datapath for a
subset of MIPS instructions:
• Shifting and Jumping are not supported

➢ Check your understanding:

• Take the complete datapath and play the role of
controller:
▪ See how supported instructions are executed
▪ Figure out the correct control signals for the datapath elements

➢ Coming up next: Control (Lecture #13)

41
Instruction
Memory

Complete Datapath
PC Add
4
M
Instruction
U
Add X
Left Shift
Address
2-bit

PCSrc
opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21] 4
5
rs

RR1 RD1
5 is0?
RR2 MemWrite
20:16

01010
rt

Registers ALU
5 ALUSrc
WR ALU
M Address
result
15:11

01000

RD2 M
U
rd

WD Data
Inst [15:11]
X U Memory
X Read
shamt
00000

RegWrite
10:6

RegDst Data M
Write
Data U
Inst [15:0] Sign X
100000
funct

Extend
5:0

MemRead
42

End
43
MIPS Generic Instruction Executions
➢ Show the actual steps for 3 representative MIPS instructions
➢ Fetch and Decode stages not shown:
• The standard steps are performed

add $3, $1, $2 lw $3, 20( $1 ) beq $1, $2, label

Fetch &
Decode
standard standard standard

Operand o Read [$1] as opr1 o Read [$1] as opr1 o Read [$1] as opr1
Fetch o Read [$2] as opr2 o Use 20 as opr2 o Read [$2] as opr2
o MemAddr = opr1 + opr2
Taken = (opr1 == opr2 )?
Execute Result = opr1 + opr2 o Use MemAddr to read
Target = PC + Label*
from memory
Result if (Taken)
Result stored in $3 Memory data stored in $3
Write PC = Target

◼ opr = Operand ◼ * = simplification, not exact

◼ MemAddr = Memory Address