ASSEMBLY LANGUAGE

TYPES OF PROGRAMMING
LANGUAGE
• Low level language
• Mid level language
• High level language
 Advantages of high level Advantages of low level
over low level language over high level language
• Easy to learn • Compact code
• Predefined functions • Speed
• Portability • flexible
Assembly language is
specific to one
ASSEMBLING PROGRAMS
microcontroller

Converts the source code

into object code

The linker will combine the

object code of your
program with any other
required object code to
produce executable code

Loader will load the

executable code into
memory, for execution
 BASIC OPERATIONAL CONCEPT
• Ex.
• ADD R0, LOCA
• The given instruction requires the performance of several steps:
1. The instruction must be transferred or fetched from the MM into the CPU.
2. The operand at LOCA must be fetched and added to the contents of R0.
3. The resultant sum is stored in register R0.
In order to fetch/read an instruction or data from main memory:
1. The CPU first sends the address of the memory location to be read.
2. The CPU then issues or sends the read signal to the memory.
3. The word is then read out of memory and is loaded into a CPU internal register.
• In order to store/write data into main memory:
1. The CPU first sends the address of the memory location to be written.
2. The CPU then sends the write signal together with the data or word to be written
to memory.
 CONNECTION BETWEEN THE
PROCESSOR AND THE MAIN MEMORY
 OPERATING STEPS
1. PC is set to point to the first instruction of the program (the operating system
loads the memory address of the first instruction).
2. The contents of the PC are transferred to the MAR (which are automatically
transmitted to the MM) and a Read signal is sent to the MM.
3. The addressed word is read out of MM and loaded into the MDR.
4. The contents of MDR are transferred to the IR. The instruction is ready to be
decoded and executed.
5. During execution, the contents of the PC are incremented or updated to
point to the next instruction.
• If result is to be stored in MM:
1. The result is sent to the MDR.
2. The address of the location where the result is to be stored is sent to the MAR
and a write cycle is initiated.
 BUS STRUCTURE
• Main groupings of line:
1. Data bus
2. Address bus
3. Control bus
 MAIN MEMORY OPERATIONS
• Read or Fetch - This transfers the contents of a specific MM location to the
CPU. The word in the MM remains unchanged.
Read/Fetch Cycle:
1. CPU sends address of the desired location.
2. MM reads the data stored at that address and sends it to the CPU.
• Write or Store - This transfers a word of information from the CPU to a specific
MM location. This destroys the former contents of that location.
Write/Store Cycle:
1. CPU sends address of the desired location to the MM, together with the data to
be stored into that location.
2. Data is written at desired location
 INSTRUCTIONS AND INSTRUCTION
SEQUENCING
Types of Instructions:
1. Data transfers between MM and CPU registers.
2. Arithmetic and logic operations on data.
3. Program sequencing and control.
4. I/O operations or transfers.
 PROGRAMMING MODEL
Register Structure of the 8086/8088
 STATUS REGISTER OR PROCESSOR
STATUS WORD
• PSW is divided into two flag:
1. conditional flags -they reflect the result of the previous operation involving the ALU
2. control flags -they control the execution of special functions

CONDITIONAL FLAGS
1. Carry Flag
2. Auxiliary Flag
3. Sign Flag
4. Parity Flag
5. Zero Flag
6. Overflow Flag
 TYPES 14

• Conditional flags
• Control flags
 CONDITIONAL FLAGS
• CARRY FLAG - An addition causes this flag to be set to 1 if there is a carry out
of the MSB, and a subtraction causes it to be set to 1 if a borrow is needed.
EXAMPLE:
BAH + 09H
BAH
= 1011 10102
+ 09H
0000 10012
C3H
1100 0011

CF = 0
 CONDITIONAL FLAG
Auxiliary Flag - This flag is used exclusively for BCD arithmetic. It is set to 1 if
there is a carry out of bit 3 (b3) during an addition or a borrow by bit 3 during
a subtraction.

Ex. MOV AL, 25H AL <-25H 0010 0101

ADD AL, 50H AL <- AL +5H 0101 0000

0111 0101

CF = 0 AF = 0
 CONDITIONAL FLAG
Sign Flag - This is equal to the MSB of the result of the previous operation. 0 if
positive, 1 if negative.

Ex. 1010 0110 A6H

+0111 0101 +75H
10001 1011 11BH

CF = 1 AF = 0 SF =0
 CONDITIONAL FLAG
• Parity Flag - This is set to 1 if the low-order 8 bits of the result of the previous
operation contain an even number of 1s. Otherwise, it is reset to 0.
• Example
69H + F8H
CF = 1 SF = 0 (+)
69H 0110 1001
+F8H 1111 1000 AF = 1 PF = 0 (odd)
161H 10110 0001
 CONDITIONAL FLAG
Zero Flag - This is set to 1 if the result of the previous operation is zero and 0 if
the result is nonzero.

Example:

8AH – 97H CF = 1 SF = 1 ZF = 0
AF = 0 PF = 1
8AH 1000 1010
-97H - 1001 0111
FF3H 11111 0011
 CONDITIONAL FLAG
Overflow Flag - This is set to 1 if an overflow occurs, i.e., a result is out of range.
More specifically, for addition this flag is set to 1 when there is a carry into the
MSB and no carry out of the MSB or vice-versa. For subtraction, it is set to 1,
when the MSB needs a borrow and there is no borrow from the MSB, or vice-
versa.
B7 B6

Example: 1
01
78H 0111 1000 CF = 0 PF = 0 ZF = 0
01
+ 56H 0101 0110 AF = 0 OF = 1 10
SF = 1
CEH 1100 1110
 EXAMPLE
Given ABH + 9AH; derive the values of the conditional flags

ABH 1010 1011 CF= 1 ZF= 0 PF= 0

+ 9AH 1001 1010 AF= 1 SF= 0 OF= 1
145H 10100 0101
 EXAMPLE
GIVEN THE FF:
D8H – 4BH
COMPUTE FOR THE VALUES OF THE CONDITIONAL FLAGS

1101 1000 D8H CF=0 SF=1 ZF=0

-0100 1011 - 4BH
8DH AF=1 PF=1 OF=0
1000 1101
 YOUR TURN:
Determine the values of the conditional flags:
1. 110100012 – 100100112
2. A7H + 78H
3. 1567H + 2456H
 CONTROL FLAGS
1. Direction flag - This flag is used by string manipulation instructions. If clear,
the string is processed from its beginning with the first element having the
lowest address. Otherwise, the string is processed from the high address
towards the low address.
2. Interrupt Enable Flag - If set, a certain type of interrupt (a maskable
interrupt) can be recognized by the CPU; otherwise, these interrupts are
ignored.
3. Trap Flag- If set, the 8086/8088 will enter into a single-step mode. In this
mode, the CPU executes one instruction at a time.
 25

MEMORY SEGMENTATION
 In memory, data is stored as bytes.
 Each byte has a specific address.
 Intel 8086 has 20 lines address bus.
 With 20 address lines, the memory that can be addressed is 220 bytes.
 220 = 1,048,576 bytes (1 MB).
 8086 can access memory with address ranging from 00000 H to FFFFF H.
 26

MEMORY SEGMENTATION
• In 8086, memory has four different types of segments.
• These are:
• Code Segment
• Data Segment
• Stack Segment
• Extra Segment
 27

SEGMENT REGISTERS
 Each of these segments are addressed by an address stored in
corresponding segment register.
 These registers are 16-bit in size.
 Each register stores the base address (starting address) of the
corresponding segment.
 Because the segment registers cannot store 20 bits, they only store the
upper 16 bits.
 28

SEGMENT REGISTERS
 How is a 20-bit address obtained if there are only 16-bit registers?
 The 20-bit address of a byte is called its Physical Address.
 But, it is specified as a Logical Address.
 Logical address is in the form of:
Base Address : Offset

 Offset is the displacement of the memory location from the starting

location of the segment.
 29

EXAMPLE
• The value of Data Segment Register (DS) is 2222 H.
• To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSB of the
address.
• After appending, the starting address of the Data Segment becomes
22220H.
 30

EXAMPLE (CONTD.)
• If the data at any location has a logical address specified as:
2222 H : 0016 H

• Then, the number 0016 H is the offset.

• 2222 H is the value of DS.
 31

EXAMPLE (CONTD.)
• To calculate the effective address of the memory, BIU uses the following
formula:
 Effective Address = Starting Address of Segment + Offset

• To find the starting address of the segment, BIU appends the contents of
Segment Register with 0H.
• Then, it adds offset to it.
 32

EXAMPLE (CONTD.)
• Therefore:
• EA = 22220 H
+ 0016 H
------------
22236 H
 33

MAX. SIZE OF SEGMENT

• All offsets are limited to 16-bits.
• It means that the maximum size possible for segment is 216 = 65,535 bytes (64
KB).
• The offset of the first location within the segment is 0000 H.
• The offset of the last location in the segment is FFFF H.
 34

WHERE TO LOOK FOR THE OFFSET

Segment Offset Registers Function
CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Address in the stack
ES BX, DI, SI Address of destination data
(for string operations)
 35

QUESTION
 The contents of the following registers are:
 CS = 1111 H
 DS = 3333 H
 SS = 2526 H
 IP = 1232 H
 SP = 1100 H
 DI = 0020 H
 Calculate the corresponding physical addresses for the address bytes in CS, DS
and SS.
 36

1. CS = 1111 H
SOLUTION
 The base address of the code segment is 11110 H.
 Effective address of memory is given by 11110H + 1232H =
12342H.
2. DS = 3333 H
 The base address of the data segment is 33330 H.
 Effective address of memory is given by 33330H + 0020H =
33350H.
3. SS = 2526 H
 The base address of the stack segment is 25260 H.
 Effective address of memory is given by 25260H + 1100H =
26360H.
 GENERATING MEMORY ADDRESS
• Physical Address = Segment address + offset address
Segment Register/ offset Physical Address
DS (data segment) AX, BX, CX,DX, =(DS*10H)+register/OFFSET
displacement, DI, SI
SS(stack segment) BP, SP =(SS*10H) + BP/SP
CS(code segment) IP = (CS*10H) + IP
ES (extra segment) DI = (ES*10H) + DI
 EXAMPLE
1. Given the following, compute for the Physical address.
DS = 1234H AX=0500H
Solution:
PA = (DS*10H) + 0500H
= 12340H + 0500H
= 12840H
2. Given SS= 3B0AH; SP = 08ABH
Solution:
PA =(SS*10H) + SP
= 3B0A0H
08ABH
3B94BH ->[LB]
3B94CH ->[HB]
 EXAMPLE
Given: ES = 1768H, DI = 0809H, compute for the physical address.
PA = (ES *10H) +DI
= 17680H
+ 00809H
17E89H
LB -> [17E89H]
HB->[17E8AH]
 THE STACK
PUSH POP
Bottom of the Stack = SS x 10H + FFFFH Bottom of the Stack = SS x 10H + FFFFH
SS range = SS ~BOS SS range = SS ~BOS
Top of the Stack = SS x 10H + SP Top of the Stack = SS x 10H + SP
LB ->[TOS-2] LB<-[TOS]
HB ->[TOS-1] HB<-[TOS+1]
NEW TOS = TOS -2 NEW SP= [SP+2]
NEW SP = SP-2 NEW TOS = [TOS+2]
 EXAMPLE
PUSH BX
Assume: BX = 4567H SS= 2765H SP = 3574H
Determine the address of the ff: BOS, TOS, SS range, New SP, BL and BH
location
TOS = (SS *10H) + SP
Solution: = 27650H
HB ->[TOS-1]
BOS = (SS*10H)+FFFFH + 03574H
BH = 45H ->[2ABC3H]
= 27650H 2ABC4H
+ 0FFFFH New SP = [SP-2]
LB ->[TOS-2] = [3572H]
3764FH BL = 67H ->[2ABC2H]
SS Range: 2765H ~ 3764FH New TOS = [TOS-2]
= [2ABC2H]
 THE STACK
• POP CX
• Assume CX = 3467H, SS= 567BH SP=0078H
Compute for the ff: BOS, TOS, SS RANGE, NEW SP, LB AND HB ADDRESS

Solution: TOS = (SS *10H) + SP

= 567B0H HB ->[TOS+1]
+ 00078H BH = 34H ->[56829H]
BOS = (SS * 10H) + FFFFH 56828H
= 567B0H
LB ->[TOS] New SP = [SP+2]
+ 0FFFFh = [007AH]
BL = 67H ->[56828H]
667AFH
SS Range: 567BH ~ 667AFH New SP = [TOS+2]
= [5682AH]
 ADDRESING MODES
• Addressing modes refer to the way in which an operand is specified

Data Addressing Mode Example NOTATION/ PHYSICAL ADDRESS

Register Addressing MOV AX, BX AX <-BX
Immediate Addressing MOV AL,13H AL<-13H
Direct Addressing MOV AX, ALPHA AX<-[(DS*10H) +ALPHA]
MOV CL, [3000H] CL<-[(DS*10H) +3000H]
Register Indirect Addressing MOV AX,[BX] AX<-[(DS*10H)+BX]
MOV BX, [BP] BX <-[(SS*10H) +SP]
Register Relative Addressing or MOV AX, [BX+2500H] AX<-[(DS*10H)+BX+2500H]
Base Addressing
MOV AL, [BX] +BETA AL<-[(DS*10H)+BX+BETA]
 ADDRESSING MODES

Data Addressing Mode Example NOTATION/ PHYSICAL ADDRESS

Base-plus-index addressing MOV AX,[BX + SI] AX<-[DS*10H+BX+SI]
MOV [BX+SI], SP [(DS*10H)+BX+SI]<-SP
Base relative-plus-index MOV AX, [BX + SI + 0100H] AX<[(DS*10H)+BX+SI+0100H]
addressing
MOV AL, ALPHA[BX+DI] AL<[(DS*10H)+ALPHA+BX+DI]
 EXAMPLE
Identify the type of addressing mode used and the address of the lower and higher byte.
ASSUME:
ALPHA = 2345H BETA = 1234H LIST = 5A78H BP = 4567H
DS = 6A45H SS = 5674H AX = 7865H SI = 4567H
BX = 458AH CX = 7865H SP = 0075H DI =6789H
INSTRUCTION ADDRESSING MODE NOTATION PHYSICAL ADDRESS/VALUE

MOV AL, BL REGISTER ADDRESSING AL<-BL AL <-8AH

MOV [BX+SI], AX BASE-PLUS-INDEX [(DS*10H)+BX+SI)<-AX [(6A450H+458AH+4567H]<-AL
[72F41H]<-AL ; [72F42H]<-AH

MOV AX, BETA

AX<-[DS*10H+BETA] AL<-[6A450H+1234H]
DIRECT ADDRESSING AL<-[6B684H]; AH<-[6B685H]

MOV AX, LIST[DI + 0789H] AL<-

BASE-RELATIVE-PLUS-INDEX AX<-
[6A450H+5A78H+6789H+0789H]
[(DS*10H)+LIST+DI+0789H] AL<- [76DDAH]; AH<-[76DDBH]
MOV [BP + 1008H], CL [56740+4567H+1008H]<-CL
REGISTER RELATIVE [(SS*10H)+BP+1008H]<-CL [5BCAFH]<-CL