Previous year questions
1. Draw the logic diagram of AND gate using NOR gate
2. Give the truth table of XNOR gate
3. What are universal Gates
4. Explain the design of full adder using logic diagram and truth table
5. What is demultiplexer ?design 1 to 4 demultiplexer
6. Explain How full adder circuit can be converted to a full subtractor with the addition of one inverter
circuit?
7. Explain look a head carry adder
8. Implementation of 16 to 1 multiplexer using 8 to 1 and 2 to 1 much
9Explain BCD to Seven segment Decoder
[Link] of 3 to 8 decoder using 2 to 4 decoders
[Link] a logic diagram of 2 to 4 decoder using I)NOR Gates only II) NAND gates only
MODULE 1 Digital logic
Introduction to Digital Logic
Digital logic is the foundation, not only
of computing but also many other
electronic devices and control systems
found in almost every part of modern
life.
This module introduces the basics of
digital logic and shows how the whole of
digital electronics depends on just seven
types of logic gates, connected together
with a minimum of additional
components. Combinations of logic
gates then form circuits that can perform
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specific tasks within larger circuits or
systems. The process of producing
complex circuits using combinations of
basic devices is Combinational Logic.
Logic Gates
Logic gates
Digital systems are said to be constructed
by using logic gates. These gates are the
AND, OR, NOT, NAND, NOR, EXOR and
EXNOR gates. The basic operations are
described below with the aid of truth
tables.
AND gate
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The AND gate is an electronic circuit that
gives a high output (1) only if all its inputs
are high. A dot (.) is used to show the AND
operation i.e. A.B. Bear in mind that this
dot is sometimes omitted i.e. AB
OR gate
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The OR gate is an electronic circuit that
gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show
the OR operation.
NOT gate
The NOT
gate is an electronic circuit that produces
an inverted version of the input at its
output. It is also known as an inverter. If
the input variable is A, the inverted output
is known as NOT A.
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NAND gate
This is a NOT-AND gate which is
equal to an AND gate followed
by a NOT gate. The outputs of
all NAND gates are high if any of the inputs
are low. The symbol is an AND gate with a
small circle on the output. The small circle
represents inversion.
NOR gate
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This is a NOT-OR gate which is equal to an
OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of
the inputs are high.
The symbol is an OR gate with a small circle
on the output. The small circle represents
inversion.
EXOR gate
The 'Exclusive-
OR' gate is a circuit which will give a high
output if either, but not both, of its two
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inputs are high. An encircled plus sign () is
used to show the EOR operation.
EXNOR gate
The 'Exclusive-NOR' gate circuit does the
opposite to the EOR gate. It will give a low
output if either, but not both, of its two
inputs are high. The symbol is an EXOR gate
with a small circle on the output. The small
circle represents inversion.
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The NAND and NOR gates are called
universal gates since with either one the
AND and OR functions and NOT can be
generated.
NAND and NOR gates are widely known to
be universal logic gates, meaning that any
other logic gate be made from NAND or
NOR gates.
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Combinational Circuits
The combinational logic circuits are the
circuits that contain different types of logic
gates. Simply, a circuit in which different
types of logic gates are combined is known
as a combinational logic circuit. The output
of the combinational circuit is determined
from the present combination of inputs,
regardless of the previous input.
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Half Adder
Half adder is a combinational logic circuit
with two inputs and two outputs. The half
adder circuit is designed to add two single
bit binary number A and B. It is the basic
building block for addition of two single bit
numbers. This circuit has two outputs carry
and sum.
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Block Diagram of Full Adder
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Full adder is developed to overcome the
drawback of Half Adder circuit. It can add
two one-bit numbers A and B, and carry c.
The full adder is a three input and two
output combinational circuit.
Implementation of full adder using half
adder
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Half Subtractors
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Half subtractor is a combination circuit with
two inputs and two outputs (difference and
borrow). It produces the difference
between the two binary bits at the input
and also produces an output (Borrow) to
indicate if a 1 has been borrowed. In the
subtraction (A-B), A is called as Minuend bit
and B is called as Subtrahend bit.
Full Subtractors
The disadvantage of a half subtractor is
overcome by full subtractor. The full
subtractor is a combinational circuit with
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three inputs A,B,C and two output D and C'.
A is the 'minuend', B is 'subtrahend', C is the
'borrow' produced by the previous stage, D
is the difference output and C' is the borrow
output.
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Implementation of full subtractor using half subtractor
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Explain How full adder circuit can be converted to a full
subtractor with the addition of one inverter circuit?
N-Bit Parallel Adder
The Full Adder is capable of adding only two single digit
binary number along with a carry input. But in practical we
need to add binary numbers which are much longer than just
one bit. To add two n-bit binary numbers we need to use the
n-bit parallel adder. It uses a number of full adders in
cascade. The carry output of the previous full adder is
connected to carry input of the next full adder.
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4 Bit Parallel Adder
In the block diagram, A0 and B0 represent the LSB of the four
bit words A and B. Hence Full Adder-0 is the lowest stage.
Hence its Cin has been permanently made 0. The rest of the
connections are exactly same as those of n-bit parallel adder
is shown in fig. The four bit parallel adder is a very common
logic circuit.
Ripple carry adder circuit.
Multiple full adder circuits can be cascaded in parallel to add
an N-bit number. For an N- bit parallel adder, there must be N
number of full adder circuits. A ripple carry adder is a logic
circuit in which the carry-out of each full adder is the carry in
of the succeeding next most significant full adder. It is called a
ripple carry adder because each carry bit gets rippled into the
next stage.
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In a ripple carry adder the sum and carry
out bits of any half adder stage is not valid
until the carry in of that stage
[Link] delays inside the logic
circuitry is the reason behind this.
Propagation delay is time elapsed
between the application of an input and
occurance of the corresponding output.
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Carry Look-Ahead Adder
Motivation behind Carry Look-Ahead
Adder :
In ripple carry adders, for each adder
block, the two bits that are to be added
are available instantly. However, each
adder block waits for the carry to arrive
from its previous block. So, it is not
possible to generate the sum and carry of
any block until the input carry is known.
The block waits for the block
to produce its carry. So there will be a
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considerable time delay which is carry
propagation delay.
A carry look-ahead adder reduces the
propagation delay by introducing more
complex hardware.
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Decoder
Decoder is a combinational circuit that
has ‘n’ input lines and maximum of
2noutput lines. One of these outputs will
be active High based on the combination
of inputs present, when the decoder is
enabled. That means decoder detects a
particular code.
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2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 &
A0 and four outputs Y3, Y2, Y1 & Y0.
The block diagram of 2 to 4 decoder is
shown in the following figure.
One of these four outputs will be ‘1’ for
each combination of inputs when enable,
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E is ‘1’. The Truth table of 2 to 4 decoder
is shown below.
Enable Inputs Outputs
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
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1 1 0 0 1 0 0
1 1 1 1 0 0 0
From Truth table, we can write
the Boolean functions for each output
as
Y3=E.A1.A0Y3=E.A1.A0
Y2=E.A1.A0′Y2=E.A1.A0′
Y1=E.A1′.A0Y1=E.A1′.A0
Y0=E.A1′.A0′Y0=E.A1′.A0′
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Each output is having one product term.
So, there are four product terms in total.
We can implement these four product
terms by using four AND gates having
three inputs each & two inverters.
The circuit diagram of 2 to 4 decoder is
shown in the following figure.
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3 to 8 Decoder.
• A 3 to 8 decoder has three inputs
(A,B,C) and eight outputs (DO to D7).
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• Based on the 3 inputs one of the eight
outputs is selected.
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4 To 16 Decoder
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Encoder
An Encoder is a combinational circuit
that performs the reverse operation of
Decoder. It has maximum of 2n input lines
and ‘n’ output lines. It will produce a
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binary code equivalent to the input,
which is active High. Therefore, the
encoder encodes 2n input lines with ‘n’
bits.
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4 to 2 Encoder has four inputs Y3, Y2, Y1
& Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the
following figure.
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Boolean Expression
A1=Y3+Y2
A0=Y3+Y1
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8 to 3 ENCODER
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16 To 4 ENCODER
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BCD to decimal decoder
What is BCD?
Binary Coded Decimal, or BCD, is another
process for converting decimal numbers
into their binary equivalents.
It is a form of binary encoding where each
digit in a decimal number is represented
in the form of bits.
This encoding can be done in either 4-bit
or 8-bit (usually 4-bit is preferred).
It is a fast and efficient system that
converts the decimal numbers into binary
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numbers as compared to the existing
binary system.
BCD to decimal decoder converts each
BCD code into one of 10 possible decimal
digit [Link] BCD to decimal
decoder should have four inputs to accept
the code digit and ten outputs 1 for 10
decimal digits.
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BCD to Seven Segment Decoder
BCD to seven segment decoder is a
circuit used to convert the input BCD
into a form suitable for the display. It has
four input lines (A, B, C and D) and 7
output lines (a, b, c, d, e, f and g) as
shown in Figure
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Implementation of Higher-order
Decoders using lower order decoder
In this section, let us implement 3 to 8
decoder using 2 to 4 decoders. We
know that 2 to 4 Decoder has two inputs,
A1 & A0 and four outputs, Y3 to Y0.
Whereas, 3 to 8 Decoder has three inputs
A2, A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order
decoders required for implementing
higher order decoder using the following
[Link]
coders=m2/m1
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Where, m1 is the number of outputs of
lower order decoder.m2 is the number of
outputs of higher order decoder.
Here, m1 = 4 and m2 = 8. Substitute,
these two values in the above formula.
Requirednumberof2to4decoders=8/4=2
Therefore, we require two 2 to 4
decoders for implementing one 3 to 8
decoder.
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Draw a logic diagram of 2 to 4 decoder using I)NOR
Gates only II) NAND gates only
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Multiplexer(MUX)
A Multiplexer (MUX) can be described as
a combinational circuit that receives
binary information from one of the 2^n
input data lines and directs it to a single
output line.
The selection of a particular input data
line for the output is decided on the basis
of selection lines.
The multiplexer is often called as data
selector since it selects only one of many
data inputs.
• 2n input lines
• One output line
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• n Selection lines
Some of the mostly used multiplexers
include 2-to-1, 4-to-1, 8-to-1 and 16-to-1
multiplexers.
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77th
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Demultiplexer
A demultiplexer (or demux) is a
device that takes a single input line and
routes it to one of several digital output
lines. A demultiplexer of 2n outputs has n
select lines, which are used to select
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which output line to send the input. A
demultiplexer is also called a data
distributor.
Types of Demultiplexers
•1 to 2
•1To 4
•1 to 8
•1 to 16
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Implementation of Higher
order MUX using lower order
MUX
4 : 1 MUX using 2 : 1 MUX
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How do you design a 16-to-1 multiplexer using two 8:1 multiplexer
and one 2:1 multiplexer? (Important)
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