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Introduction To Computer Part 2

Part 2

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Introduction To Computer Part 2

Part 2

Uploaded by

ajabkasi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to computer

Part 2

Dr. Ajab Khan Kasi


Algorithm
 An algorithm is a step by step method of solving a problem. It is commonly used
for data processing, calculation and other related computer and mathematical
operations. An algorithm is also used to manipulate data in various ways, such as
inserting a new data item, searching for a particular item or sorting an item.

The word algorithm itself is derived from the


9th-century Persian mathematician
Muḥammad ibn Mūsā al-Khwārizmī, Latinized
Algoritmi.
Addition and subtraction Algorithm
Half adder and full adder
Full Adder
4 Bit binary adder subtractor
In Digital Circuits, A Binary Adder-Subtractor is one which is capable of both addition and subtraction of binary numbers in one
circuit itself. The operation being performed depends upon the binary value and the control signal . It is one of the components of
the ALU (Arithmetic Logic Unit).
Lets consider two 4-bit binary numbers A and B as inputs to the Digital Circuit for the operation with digits
A0 A1 A2 A3 for A
B0 B1 B2 B3 for B
The circuit consists of 4 full adders since we are performing operation on 4-bit numbers. There is a control line K that holds a binary
value of either 0 or 1 which determines that the operation being carried out is addition or subtraction.

As shown in the figure, the first full adder has control line directly as its input(input carry Cin), The input A0 (The least significant bit
of A) is directly input in the full adder. The third input is the exor of B0 and K. The two outputs produced are Sum/Difference (S0)
and Carry (C0).
4 Bit binary adder subtractor
If the value of K (Control line) is 1, the output of B0(exor)K=B0′(Complement B0). Thus the operation would be
A+(B0′). Now 2’s complement subtraction for two numbers A and B is given by A+B’. This suggests that when K=1,
the operation being performed on the four bit numbers is subtraction.

Similarly If the Value of K=0, B0 (exor) K=B0. The operation is A+B which is simple binary addition.This suggests
that When K=0, the operation being performed on the four bit numbers is addition.

Then C0 is serially passed to the second full adder as one of it’s outputs. The sum/difference S0 is recorded as the
least significant bit of the sum/difference. A1, A2, A3 are direct inputs to the second, third and fourth full adders.
Then the third input is the B1, B2, B3 EXORed with K to the second, third and fourth full adder respectively.The
carry C1, C2 are serially passed to the successive full adder as one of the inputs. C3 becomes the total carry to the
sum/difference. S1, S2, S3 are recorded to form the result with S0.
4 Bit binary adder subtractor
Example:
Lets take two 3 bit numbers A=010 and B=011 and input them in the full adder with both values
of control lines.
For K=0:
B0(exor)K=B0 and C0=K=0
Thus from first full adder
= A0+B0
= 0+1
= 1,
S0=1
C1=0
Similarly,
S1=0 with C2=1
S2=1 and C2=0
Thus,
A = 010 =2
B = 011 = 3
Sum = 0101 = 5

For K=1
B0(exor)K=B0' and C0=k=1

Thus
S0=1 and C1=0
Similarly
S1=1 and C2=0
S2=1 and c3=0

Thus,
A = 010 = 2
B = 011 = 3
Sum(Difference) = 1111 = -1
Addition and subtraction
Addition and subtraction Algorithm
The flowchart is shown in Figure . The two signs A, and B, are compared by an exclusive-OR gate. If the

output of the gate is 0 the signs are identical; If it is 1, the signs are different. For an add operation,

identical signs dictate that the magnitudes be added. For a subtract operation, different signs dictate

that the magnitudes be added.The magnitudes are added with a microoperation EA= A + B, where EA

is a register that combines E and A. The carry in E after the addition constitutes an overflow if it is

equal to 1. The value of E is transferred into the add-overflow flip-flop AVF.The two magnitudes are

subtracted if the signs are different for an add operation or identical for a subtract operation. The

magnitudes are subtracted by adding A to the 2's complemented B. No overflow can occur if the

numbers are subtracted so AVF is cleared to 0. 1 in E indicates that A >= B and the number in A is the

correct result. If this numbs is zero, the sign A must be made positive to avoid a negative zero. 0 in E

indicates that A < B. For this case it is necessary to take the 2's complement of the value in A. The

operation can be done with one microoperation A =A' +1.


Addition and subtraction Algorithm
However, we assume that the A register has circuits for microoperations
complement
and increment, so the 2's complement is obtained from these two microoperations.
In other paths of the flowchart, the sign of the result is the same as the sign of A. so
no
change in A is required. However, when A < B, the sign of the result is the
complement of the original sign of A. It is then necessary to complement A, to obtain
the correct sign.
The final result is found in register A and its sign in As. The value in AVF provides an
overflow indication. The final value of E is immaterial.
Figure shows a block diagram of the hardware for implementing the addition and
subtraction operations.
It consists of registers A and B and sign flip-flops As and Bs.
Subtraction is done by adding A to the 2's complement of B.
The output carry is transferred to flip-flop E , where it can be checked to determine
the relative magnitudes of two numbers.
The add-overflow flip-flop AVF holds the overflow bit when A and B are added.
The A register provides other microoperations that may be needed when we specify
the sequence of steps in the algorithm
Addition and subtraction

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