Computer Organization & Architecture

Jesla Joseph
School of Computer Science and
Applications
 • Combinational Logic
Digital • Sequential Logic
Electroni •
Basic Structure of
cs
Computer

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 Digital
Electroni •Combinational
cs
Logic
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DIGITAL ELECTRONICS
Combinational circuits
• A combinational logic circuit is a circuit whose outputs only depend on the
current state of its inputs. In mathematical terms, the each output is a
function of the inputs. These functions can be described using logic
expressions, but is most often (at least initially) using truth tables.
• Logic gates are the simplest combinational circuits.
• When all the devices in a circuit are connected by series connections, then
the circuit is referred to as a series circuit.
• When all the devices in a circuit are connected by parallel connections,
then the circuit is referred to as a parallel circuit.
• A third type of circuit involves the dual use of series and parallel
connections in a circuit; such circuits are referred to as compound circuits
or combination circuits.

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characteristics
• The output of combinational circuit at any
instant of time, depends only on the levels
present at input terminals.
• The combinational circuit do not use any
memory.
• The previous state of input does not have any
effect on the present state of the circuit.
• A combinational circuit can have an n number
of inputs and m number of outputs.

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Block diagram
• A combinational circuit performs a specific
information-processing operation fully
specified logically by a set of Boolean
functions.
• The basic components of a combinational
circuit are: input variables, logic gates, and
output variables.
• The 'n' input variables come from an external
source whereas the 'm' output variables go to
an external destination. In many applications,
the source or destination are storage registers.

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• Combinational logic circuits can be very simple or very complicated
and any combinational circuit can be implemented with only NAND
and NOR gates as these are classed as “universal” gates.
• The three main ways of specifying the function of a combinational
logic circuit are:
• 1. Boolean Algebra – This forms the algebraic expression showing the
operation of the logic circuit for each input variable either True or
False that results in a logic “1” output.
• 2. Truth Table – A truth table defines the function of a logic gate by
providing a concise list that shows all the output states in tabular
form for each possible combination of input variable that the gate
could encounter.
• 3. Logic Diagram – This is a graphical representation of a logic circuit
that shows the wiring and connections of each individual logic gate,
represented by a specific graphical symbol, that implements the logic
circuit.
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• and all three of these logic circuit
representations are shown below.

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DESIGN PROCEDURE OF A COMBINATIONAL
CIRCUIT
• The design procedure of a combinational circuit involves the
following steps:
• The problem is stated.
• The total number of available input variables and required output
variables is determined.
• The input and output variables are allocated with letter symbols.
• The exact truth table that defines the required relationships between
inputs and outputs is derived.
• The simplified Boolean function is obtained from each output.
• The logic diagram is drawn.
• The combinational circuit that performs the addition of two bits is
called a half adder and the one that performs the addition of
three bits (two significant bits and a previous carry) is a full
adder.
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• As combinational logic circuits are made up
from individual logic gates only, they can also
be considered as “decision making circuits”
and combinational logic is about combining
logic gates together to process two or more
signals in order to produce at least one output
signal according to the logical function of each
logic gate. Common combinational circuits
made up from individual logic gates that carry
out a desired application include Multiplexers,
De-multiplexers, Encoders, Decoders, Full and
Half Adders etc.

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ADDERS-SUBSTRACTORS
Binary adders
• A basic Binary Adder circuit can be made from
standard AND and Ex-OR gates allowing us to
“add” together two single bit binary
numbers, A and B.
• The addition of these two digits produces an
output called the SUM of the addition and a
second output called the CARRY or Carry-out,
( COUT ) bit according to the rules for binary
addition. One of the main uses for the Binary
Adder is in arithmetic and counting circuits.
Consider the simple addition of the two denary
(base 10) numbers below.

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Binary Addition
• Binary Addition follows these same basic
rules as for the denary addition above except
in binary there are only two digits with the
largest digit being “1”. So when adding binary
numbers, a carry out is generated when the
“SUM” equals or is greater than two (1+1) and
this becomes a “CARRY” bit for any
subsequent addition being passed over to the
next column for addition and so on.

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• When the two single bits, A and B are added together, the addition of “0
+ 0”, “0 + 1” and “1 + 0” results in either a “0” or a “1” until you get to
the final column of “1 + 1” then the sum is equal to “2”. But the number
two does not exists in binary however, 2 in binary is equal to 10, in
other words a zero for the sum plus an extra carry bit.
• Then the operation of a simple adder requires two data inputs producing
two outputs, the Sum (S) of the equation and a Carry (C) bit .

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ADDERS-SUBSTRACTORS
Half adders

• Half adder is a combinational logic circuit with

two inputs and two outputs. The half adder
circuit is designed to add two single bit binary
number A and B. It is the basic building block
for addition of two single bit numbers. This
circuit has two outputs carry and sum.

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• The adding of binary numbers is exactly the
same idea as that for adding together decimal
numbers but this time a carry is only
generated when the result in any column is
greater or equal to “2”, the base number of
binary. In other words 1 + 1 creates a carry.
• an Exclusive-OR gate only produces an output
“1” when either input is at logic “1”, but not
both the same as for the binary addition of the
previous two bits. However in order to perform
the addition of two numbers, microprocessors
and electronic calculators require the extra
carry bit to correctly calculate the equations
so we need to rewrite the previous summation
to include two-bits of output data as shown
below.

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• From the above equations we now know that
an Exclusive-OR gate will only produce an
output “1” when “EITHER” input is at logic “1”,
so we need an additional output to produce
the carry bit when “BOTH” inputs A and B are
at logic “1”. One digital gate that fits the bill
perfectly producing an output “1” when both
of its inputs A and B are “1” (HIGH) is the
standard AND Gate.
• By combining the Exclusive-OR gate with
the AND gate results in a simple digital binary
adder circuit known commonly as the “Half
Adder” circuit.

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HALF ADDER CIRCUIT

• A half adder is a logical circuit that performs

an addition operation on two binary digits. The
half adder produces a sum and a carry value
which are both binary digits.

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• From the truth table of the half adder we can see that the SUM (S) output
is the result of the Exclusive-OR gate and the Carry-out (Cout) is the result
of the AND gate. Then the Boolean expression for a half adder is as
follows.

• For the SUM bit: SUM = A XOR B = A ⊕ B

• For the CARRY bit: CARRY = A AND B = A.B

One major disadvantage of the Half Adder circuit when used as a binary
adder, is that there is no provision for a “Carry-in” from the previous circuit
when adding together multiple data bits.
suppose we want to add together two 8-bit bytes of data, any resulting
carry bit would need to be able to “ripple” or move across the bit patterns
starting from the least significant bit (LSB). The most complicated operation
the half adder can do is “1 + 1” but as the half adder has no carry input the
resultant added value would be incorrect. One simple way to overcome this
problem is to use a Full Adder type binary adder circuit. 19
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HALF ADDER UNSING NOR GATE

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 A FULL ADDER CIRCUIT
• The main difference between the Full Adder and the previous Half Adder is
that a full adder has three inputs. The same two single bit data inputs A and
B as before plus an additional Carry-in (C-in) input to receive the carry from
a previous stage as shown below.
• Then the full adder is a logical circuit that performs an addition operation on
three binary digits and just like the half adder, it also generates a carry out
to the next addition column. Then a Carry-in is a possible carry from a less
significant digit, while a Carry-out represents a carry to a more significant
digit.
• In many ways, the full adder can be thought of as two half adders
connected together, with the first half adder passing its carry to the second
half adder as shown.

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• As the full adder circuit above is basically two
half adders connected together, the truth
table for the full adder includes an additional
column to take into account the Carry-in, CIN
input as well as the summed output, S and
the Carry-out, COUT bit.
Then the Boolean expression for a full adder is as
follows.

For the SUM (S) bit:

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

For the CARRY-OUT (Cout) bit:

CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A 23

⊕ B)
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INVERTER GATE

• Using the truth table and the above K-Map, the

Boolean Expression of Sum (S) output of a Full
Adder can be derived as:

• S = A'B'CIN + A'BC'IN + AB'C'IN + ABCIN

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• The K-Map for Carry output (COUT) of a Full
Adder is shown below:

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• The simplified Boolean equation for COUT is:

• COUT = A B + A CIN + B CIN

• From the above Boolean Expression, we can

say that the Carry Output of a Full Adder can
be implemented using three 2-Input AND
Gates and one 3-Input OR Gate. The following
image shows the logic diagram of the Carry
output (COUT) of a Full Adder.

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IMPLEMENTATION OF FULL ADDER USING HALF
ADDER
• A full adder can be formed by logically
connecting two half adders. The following is a
block diagram that shows the implementation
of a full adder using two half adders.

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• We know the equations for S and COUT of a Full Adder from earlier
calculations as:
• S = A'B'CIN + A'BC'IN + A B'C'IN + ABCIN
• COUT = A B + A CIN + B CIN
• We can rewrite the equation for Sum as follows:
• S = = A'B'CIN + A'BC'IN + A B'C'IN + ABCIN
• = CIN (A' B' + A B) + CIN (A' B + A B')
• =CIN (A Ex-NOR B) + CIN (A Ex-OR B)
• = CIN (A ⊕ B)' + CIN (A ⊕ B)
• Therefore, S = CIN ⊕ (A ⊕ B)

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• Similarly, we can rewrite COUT as follows:
• COUT = A B + A CIN + B CIN
• = A B + A CIN + B CIN (A + A')
• = A B + A CIN + A B CIN + A' B CIN
• = A B (1 + CIN)+ A CIN + A' B CIN
• = A B + A CIN + A' B CIN
• = A B + A CIN (B + B') + A' B CIN
• = A B + A B CIN + A B' CIN + A' B CIN
• = A B (1 + CIN )+ CIN (A' B + A B')
• = A B + CIN (A' B + A B')
• = A B + CIN (A Ex-OR B)
• Therefore, COUT = A B + CIN (A ⊕ B)

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• Based on the above two equations, the full
adder circuit can be implemented using two
half adders and an OR gate. The
implementation of full adder using two half
adders is show below.

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BLOCK DIAGRAM OF FULL ADDER

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 FULL ADDER USING NAND
GATE
• As mentioned earlier, a NAND gate is one of the universal gates and can
be used to implement any logic design. The circuit of full adder using
only NAND gates is shown below.

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 Half Adder Full Adder
Half Adder (HA) is a combinational Full Adder (FA) is a combinational
logic circuit and this circuit is used to circuit and this circuit is used to add
add two one-bit digits. three one bit digits.
In HA, once the carry is generated In FA, once the carry is generated from
from the previous addition cannot be the earlier addition, then it can be
added to the next step. added to the next step.
Half adder includes two logic gates like Full adder includes two EX-OR gates,
AND gate and EX-OR gate. two OR gates, and two AND gates.
The input bits in the half adder are two The input bits in the full adder are
like A, B. three like A, B & C-in
Half adder sum and carry equation is Full adder logic expression is
S = a⊕b ; C = a*b S = a ⊕ b⊕Cin; Cout = (a*b) + (Cin*(a⊕b)).
HA is used in computers, calculators,
FA is used in digital processors,
devices used for digital measuring,
multiple bit addition, etc.
etc. 38
KEY DIFFERENCE BETWEEN HALF ADDER AND FULL ADDER
• Half adder generates sum & carry by adding two binary inputs
whereas the full adder is used to generate sum & carry by adding
three binary inputs. Both the half adder and full adder hardware
architecture is not the same.
• The main feature that differentiates HA & FA is that in HA there is no
such deal to consider the last addition carry like its input. But, a FA
locates a particular input column like Cin to consider the last addition’s
carry bit.
• The two adders will show a difference based on the components used
in the circuit for its construction. The half adders (HA’s) are designed
with the combination of two logic gates like AND & EX-OR whereas the
FA is designed with the combination of three AND, two XOR & one OR
gates.
• Basically, HA’s operate on 2-two inputs of 1-bit, whereas the FA’s
operate on three inputs of 1-bit. Half adder is used in different
electronic devices for evaluating the addition whereas the full adder is
used in digital processors for the addition of a long bit. 39

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ADVANTAGES OF HALF ADDER AND FULL ADDER
• The foremost purpose of a half adder is to add two single-bit numbers
• Full adders hold the ability to add a carry bit which is the resulting from
the previous addition
• With full adder, crucial circuits such as adder, multiplexer, and many others
can be implemented
• The full adder circuits consume minimal power
• The advantages of a full adder over a half adder are, a full adder is used to
overcome the drawback of a half adder because; half adder is mainly used
to add two 1-bit numbers. Half adders don’t add the carry bit, so to
overcome this full adder is employed. In Full adder, the addition of three
bits can be done and generates two outputs.
• Designing of adders is simple and it is a basic building block so that one-bit
addition can be easily understood.
• This adder can be converted to half subtractor by adding an inverter.
• By using a full adder, high output can be obtained. 40
• High speed
DISADVANTAGES

• In addition, half adder cannot use before carrying, so it is not

applicable for cascading the addition of multi-bit.
• To overcome this drawback, FA is necessary to add three 1 bit.
• Once the FA is used in the form of a chain like a RA (Ripple
Adder), then the drive capability of output can be decreased.

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APPLICATIONS
• The binary bits addition can be done by half adder using ALU within the
computer because it uses adder.
• Half adder combination can be used for designing a full adder circuit.
• Half adders are used in the calculators and to measure the addresses as
well as tables
• These circuits are used to handle different applications within digital
circuits. In the future, it plays a key role in digital electronics.
• A FA circuit is used as an element in many large circuits such as Ripple
Carry Adder. This adder adds the number of bits simultaneously.
• FAs are used in Arithmetic Logic Unit (ALU)
• FAs are used in graphics-related applications like GPU (Graphics
Processing Unit)
• These are used in the multiplication circuit to execute Carryout
Multiplication.
• In a computer, to generate the memory address & to build the program 42
counterpoint toward subsequent instruction, the Arithmetic Logic Unit is
CONSTRUCTION OF HALF
SUBSTRACTOR
• In the block diagram, we have seen that it contains two inputs and two
outputs. The carry and sum are the output states of the half subtractor.
The half subtractor is designed with the help of the following logic
gates:

• 2-input AND gate.

• 2-input Exclusive-OR Gate or Ex-OR Gate
• NOT or inverter Gate

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 2-INPUT EXCLUSIVE-OR GATE OR EX-OR
GATE
• The Diff bit is generated with the help of the Exclusive-
OR or Ex-OR gate.
• The above is the symbol of the EX-OR gate. In the above
diagram, 'A' and 'B' are the inputs, and 'Diff' is the final
outcome after performing the XOR operation of both
numbers.
• The truth table of the EX-OR gate is as follows:
• From the above table, it is clear that the XOR gate gives
the result 1 when both of the inputs are different. When
both of the inputs are the same, the XOR gives the result
0. To learn more about the XOR gate,

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AND GATE
• The XOR gate is unable to generate the carry bit. For this
purpose, we use another gate called AND gate. The AND
gate is not enough to give the correct result of 'Borrow'. We
will use the NOT gate with the 'AND' gate to get the correct
result.
• The above is the symbol of the AND gate. In the above
diagram, 'A' and 'B' are the inputs, and 'OUT' is the final
outcome after performing AND operation of both numbers.

• There is the following truth table of AND gate:

• From the above table, it is clear that the AND gate gives the
result 1 when both of the inputs are 1. When both of the
inputs are different and 0, the AND gates gives the result 0.

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NOT GATE
• The NOT gate is used to get the inverse output.
We can combine the 'AND' and 'NOT' gates in
order to get the combinational gate 'NAND'. By
inverting the input 'A' using 'NOT' gate and then
use the output of the 'NOT' gate as the input of
the 'AND' gate, we can get the 'Borrow' bit.

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 HALF SUBSTRACTOR
• the Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT'
gates and provide the Diff and Borrow.
• The Boolean expression of the Half Adder circuit is given below:

• Diff= A XOR B (A⊕B)

• Borrow= not-A AND B (A'.B)

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IMPLEMENTATION OF HALF SUBSTRACTOR USING NAND
GATE

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IMPLEMENTATION OF HALF SUBTRACTOR USING NOR GATE

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FULL SUBSTRACTOR

• The Half Subtractor is used to subtract only two numbers. To

overcome this problem, a full subtractor was designed. The full
subtractor is used to subtract three 1-bit numbers A, B, and C,
which are minuend, subtrahend, and borrow, respectively. The full
subtractor has three input states and two output states i.e., diff
and borrow.

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XOR GATE CIRCUIT
DIAGRAM
• The SOP form can be obtained with the help of K-map as:
• Diff=xy' z'+x' y' z+xyz+x'yz'

• Borrow=x' z+x' y+yz

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LOGICAL EXPRESSION FOR DIFFERENCE
LOGICAL EXPRESSION FOR
BORROW
• D = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin
Bout = A’B’Cin + A’BCin’ + A’BCin + ABCin
• = Cin(A’B’ + AB) + Cin’(AB’ + A’B) = A’B’Cin +A’BCin’ + A’BCin + A’BCin + A’BCin
+ ABCin
• = Cin( A XNOR B) + Cin’(A XOR B) = A’Cin(B + B’) + A’B(Cin + Cin’) + BCin(A +
A’)
• = Cin (A XOR B)’ + Cin’(A XOR B) = A’Cin + A’B + BCin
• = Cin XOR (A XOR B)
OR
• = (A XOR B) XORCin
Bout = A’B’Cin + A’BCin’ + A’BCin + ABCin
= Cin(AB + A’B’) + A’B(Cin + Cin’)
= Cin( A XNOR B) + A’B
= Cin (A XOR B)’ + A’B

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CONSTRUCTION OF FULL SUBTRACTOR
CIRCUIT:

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• The above block diagram describes the construction of the Full
subtractor circuit. In the above circuit, there are two half
adder circuits that are combined using the OR gate. The first
half subtractor has two single-bit binary inputs A and B. As we
know that, the half subtractor produces two outputs, i.e., 'Diff'
and 'Borrow'. The 'Diff' output of the first subtractor will be
the first input of the second half subtractor, and the 'Borrow'
output of the first subtractor will be the second input of the
second half subtractor. The second half subtractor will again
provide 'Diff' and 'Borrow'. The final outcome of the Full
subtractor circuit is the 'Diff' bit. In order to find the final
output of the 'Borrow', we provide the 'Borrow' of the first and
the second subtractor into the OR gate. The outcome of the OR
gate will be the final carry 'Borrow' of full subtractor circuit.

• The MSB is represented by the final 'Borrow' bit.

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• The full subtractor logic circuit can be constructed using the
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• The actual logic circuit of the full subtractor is shown in the above
diagram. The full subtractor circuit construction can also be
represented in a Boolean expression.

• Diff:
• Perform the XOR operation of input A and B.
• Perform the XOR operation of the outcome with 'Borrow'. So, the
difference is (A XOR B) XOR 'Borrowin' which is also represented as:
• (A ⊕ B) ⊕ 'Borrowin'
• Borrow:
• Perform the 'AND' operation of the inverted input A and B.
• Perform the 'XOR' operation of input A and B.
• Perform the 'OR' operations of both the outputs that come from the
previous two steps. So the 'Borrow' can be represented as:
• A'.B + (A ⊕ B)'
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 SEQUENTIAL CIRCUITS
• The sequential circuit is a special type of circuit that has a series of inputs and
outputs. The outputs of the sequential circuits depend on both the combination of
present inputs and previous outputs. The previous output is treated as the present
state. So, the sequential circuit contains the combinational circuit and its memory
storage elements. A sequential circuit doesn't need to always contain a combinational
circuit. So, the sequential circuit can contain only the memory element.

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 DESIGN PROCEDURE OF SEQUENTIAL LOGIC CIRCUITS
• This procedure involves the following steps
• First, derive the state diagram
• Take as the state table or an equivalence representation, such as a state
diagram.
• The number of states may be reduced by the state reduction technique
• Verify the number of flip-flops needed
• Choose the type of flip-flops to be used
• Derive excitation equations
• Using the map or some other simplification method, derive the output
function and the flip-flop input functions.
• Draw a logic diagram or a list of Boolean functions from which a logic
diagram can be obtained.
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DIFFERENCE BETWEEN COMBINATIONAL AND SEQUENTIAL CIRCUIT
Combinational Circuits Sequential Circuits

1) The outputs of the combinational circuit The outputs of the sequential circuits depend on
depend only on the present inputs. both present inputs and present state(previous
output).

2) The feedback path is not present in the The feedback path is present in the sequential
combinational circuit. circuits.

3) In combinational circuits, memory In the sequential circuit, memory elements play

elements are not required. an important role and require.

4) The clock signal is not required for The clock signal is required for sequential
combinational circuits. circuits.

5) The combinational circuit is simple to It is not simple to design a sequential circuit.

design.

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TYPES OF SEQUENTIAL CIRCUITS

• Event-Driven
• Clock Driven
• Pulse Driven

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• Event-Driven: – Asynchronous circuits that can change the state immediately
when enabled. Asynchronous (fundamental mode) sequential circuit: The
behavior is dependent on the arrangement of the input signal that changes
continuously over time, and the output can be a change at any time (clockless).

• Clock Driven: Synchronous circuits that are synchronized to a specific clock

signal. Synchronous (latch mode) sequential circuit: The behavior can be defined
from the knowledge of circuits that achieve synchronization by using a timing
signal called the clock.

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• Pulse Driven: This is a mixture of the two that
responds to the triggering pulses.

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CLOCK SIGNAL AND TRIGGERING
Clock signal
• Clock signal is a periodic signal and its ON time and OFF time need not
be the same. We can represent the clock signal as a square wave, when
both its ON time and OFF time are same.
• clock signal is shown in the following figure.
• The reciprocal of the time period of clock signal is known as the
frequency of the clock signal. All sequential circuits are operated with
clock signal. So, the frequency at which the sequential circuits can be
operated accordingly the clock signal frequency has to be chosen.

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TRIGGERING
Types of triggering
• Level triggering
• The logic High and logic Low are the two levels in
the clock signal. In level triggering, when the
clock pulse is at a particular level, only then the
circuit is activated. There are the following types
of level triggering:
• Edge triggering
• In clock signal of edge triggering, two types of
transitions occur, i.e., transition either from Logic
Low to Logic High or Logic High to Logic Low.

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POSITIVE LEVEL TRIGGERING

Positive level triggering

In a positive level triggering, the signal with Logic High
occurs. So, in this triggering, the circuit is operated with
such type of clock signal. Below is the diagram of
positive level triggering:

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 NEGATIVE LEVEL TRIGGERING

.
In negative level triggering, the signal with Logic Low
occurs. So, in this triggering, the circuit is operated with such type
of clock signal. Below is the diagram of Negative level triggering:

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 EDGE TRIGGERING

There are two types of transitions that occur in clock

signal. That means, the clock signal transitions
either from Logic Low to Logic High or Logic High to
Logic Low.

Following are the two types of edge triggering

based on the transitions of clock signal.

Positive edge triggering

Negative edge triggering

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• If the sequential circuit is operated with the
clock signal that is transitioning from Logic
Low to Logic High, then that type of triggering
is known as Positive edge triggering. It is also
called as rising edge triggering. It is shown in
the following figure.

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• If the sequential circuit is operated with the clock signal that is
transitioning from Logic High to Logic Low, then that type of
triggering is known as Negative edge triggering. It is also called as
falling edge triggering. It is shown in the following figure

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LATCHES
• Latches are basic storage
elements that operate with
signal levels (rather than
signal transitions).
• Latches controlled by a clock
transition are flip-flops.
• Latches are level-sensitive
devices.
• Latches are useful for the
design of the asynchronous
sequential circuit.

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• it is also known as a bistable-multivibrator.
• Because it has two stable states namely active high as well as active low.
• It works like a storage device by holding the data through a feedback lane.
• It stores 1-bit of data as long as the apparatus is activated.
• Once enable is declared then instantly latch can change the stored data.
• It constantly trials the inputs once enable signal is activated.
• The working of these circuits can be done in 2-states based on the enable
signal being high or else low.
• When the latch circuit is the in an active high state, then both the i/ps are low.
• Similarly, when the latch circuit is then an active low state, then both the i/ps
are high.
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SR LATCH

• SR (Set-Reset) Latch – SR
Latch is a circuit with:
(i) 2 cross-coupled NOR gate
or 2 cross-coupled NAND
gate.
(ii) 2 input S for SET and R for
RESET.
(iii) 2 output Q, Q’.
•Q Q’ STATE
•1 0 Set
•0 1 Reset
• Under normal conditions, both
the input remains 0.
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• Case-1: S’=R’=1 (S=R=0) –
• If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
• If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.

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• Case-2: S’=0, R’=1 (S=1, R=0) –
• As S’=0, the output of 1st NAND
gate, Q = 1(SET state). In 2nd
NAND gate, as Q and R’ inputs are
1, Q’=0.
S R Q Q'

0 0 latch Latch

0 1 0 1

1 0 1 0

1 1 0 0

78
• Case-3: S’= 1, R’= 0 (S=0,
R=1) –
• As R’=0, the output of 2nd
NAND gate, Q’ = 1. In 1st
NAND gate, as Q and S’ inputs
are 1, Q=0(RESET state).
• Case-4: S’= R’= 0 (S=R=1) –
• When S=R=1, both Q and Q’
becomes 1 which is not
allowed. So, the input
condition is prohibited.

79
GATED SR LATCH
• A Gated SR Latch is a
special type of SR
Latch having three inputs,
i.e., Set, Reset, and Enable.
The enable input must be
active for the SET and RESET
inputs to be
effective.The ENABLE input of
gated SR Latch enables the
operation of the SET and
RESET
inputs.This ENABLE input
connects with a switch. The
Set-Reset inputs are enabled
when this switch is on.
Otherwise, all the changes are
ignored in the set and reset 80
inputs. Below are the circuit
81
J K LATCH

• The invalid state issue of two

high inputs, S and R together,
makes the device less useful.
• The JK latch is often said to be
a theoretical device. It is
almost never built, and we
were unable to find a
commercially made IC that
was a JK Jlatch K Q
Comme
next
nt
No
0 0 Q
change
0 1 0 Reset
1 0 1 Set
1 1 Q’ Toggle 82
D LATCH
• The D arrangement is realistically
simpler than the JK arrangement. It
is an SR arrangement with the
addition of an inverter, and only one
external input besides the clock or
enable, in the case of the flip flop. In
the latch circuit, the SR flip flop can
be seen clearly, with the addition of
an inverter. Whenever there is a
high on D, it is passed straight
through to S, and inverted to be a
low on R. This provides the S and R
inputs, but only as long as there is a
high on D. As soon as there is a low
on D, the outputs toggle back. That
doesn't sound very useful, and it
isn't. 83
ADVANTAGES OF LATCHES

• The designing of latches is very flexible when we compare with

FFs (flip-flops)
• The latches utilize less power.
• The performance of latch in the design of the high-speed circuit is
quick because these are asynchronous within the design and
there is no need of CLK signal.
• The shape of the latch is very small and occupies less area
• If the operation of latch based circuit is not finished in a set time,
they borrow the necessary time from other to complete the
operation
• Latches give aggressive clocking when contrasted with
flip-flop circuits.
84
DISADVANTAGES OF
LATCHES
• There will be a chance of affecting
the race condition, so these are
less expected.
• When a latch is level sensitive,
then there is a chance of meta-
stability.
• Analyzing the circuit is difficult due
to the property of level sensitive.
• The circuit can be tested by using
an extra CAD program

85
APPLICATIONS OF LATCHES

• Generally, latches are used to keep the conditions

of the bits to encode binary numbers
• Latches are single bit storage elements which are
widely used in computing as well as data storage.
• Latches are used in the circuits like power gating
& clock as a storage device.
• D latches are applicable for asynchronous
systems like input or output ports.
• Data latches are used in synchronous two-phase
systems for reducing the transit count.

86
Parameter Flip-Flop Latch
Basic Principle Flip-flop utilizes an edge Latch follows a level triggering
triggering approach. approach.
Clock Signal The clock signal is present. The clock signal is absent.
Designed Using You can design it using You can design it using Logic
Latches along with a clock. gates.
Sensitivity Flip-flop is sensitive to the Latches are sensitive to the
applied input and the clock applied input signal- only when
signal. enabled.
Operating It has a slow operating speed. It has a comparatively fast
Speed operating speed.
Classification You can classify a flip-flop into A user cannot classify the Latch
a synchronous or this way.
asynchronous flip-flop.
Working Flip-Flops work using the Latches operate only using
binary input and the clock binary inputs.
signal. 87
Power It requires more power. It requires comparatively less
Requirement power.
Analysis of It is quite easy to perform Analyzing the circuit is quite
Circuit circuit analysis. complex.
Type of Flip-flop performs Latch performs Asynchronous
Operation Synchronous operations. operations.
Performed
Robustness Flip-flops are comparatively Latches are comparatively less
more robust. robust.
Dependency The operation relies on the The operation depends on the
of Operation present and past input bits present and past input along
along with the past output with the past output binary
and clock pulses. values.
Usage as a A flip-flop is capable of A latch cannot serve as a
Register working as a register as it register as the register requires
contains clock signals in its further advanced electronic
input. circuits (EC). Time also plays an
88
essential role here.
Area It requires more area. It requires comparatively less
Required area.
Uses They constitute the building Users can utilize these for
blocks of many sequential designing sequential circuits. But
circuits such as counters. they are still not generally
preferred.
Input and A flip-flop checks the inputs. The latch responds to the
Output It only changes the output at changes in inputs continuously
times defined by any control as soon as it checks the inputs.
signal like the clock signal.
Synchronicity A flip-flop is synchronous. It A latch is asynchronous. It does
works based on the clock not work based on the time
signal. signal.
Faults Flip-Flops stay protected The latches are responsive to
against any fault. any occurring faults on the
enable pin.
Types J-K, S-R, D, and T Flip-flops. J-K, S-R, D, and T Latches. 89
BASICS OF FILP FLOPS
• A circuit that has two stable states is treated as a flip flop. These
stable states are used to store binary data that can be changed by
applying varying inputs. The flip flops are the fundamental building
blocks of the digital system. Flip flops and latches are examples of
data storage elements. In the sequential logical circuit, the flip flop
is the basic storage element. The latches and flip flops are the basic
storage elements but different in working.
• There are two types of memory elements based on the type of
triggering that is suitable to operate it.
• Latches
• Flip-flops
• Latches operate with enable signal, which is level sensitive.
Whereas, flip-flops are edge sensitive.
90
FLIP FLOP
• A Flip Flop is a memory element that is capable of storing one bit
of information. A flip flop has two outputs as shown

• A flip flop can maintain a binary state for an unlimited period of

time as long as:
• Power is supplied to the circuit.
• Or until it is directed by an input signal to switch states.

• A flip flop is also called as Bistable Multivibrator because it

has two stable states either 0 or 1.
SR FLIP FLOP

There are 4 basic types of flip flops:

SR FLIP FLOP

A flip flop, on the other hand, is synchronous and is also known as

gated or clocked SR latch.
SR FLIP FLOP

There are majorly 4 types of flip flops, with the most common one
being SR flip flop. This simple flip flop circuit has a set input (S) and a
reset input (R). In this circuit when you Set “S” as active the output
“Q” would be high and “Q‘‘” will be low.
THE TRUTH TABLE OF SR FLIP FLOP
THE TRUTH TABLE OF SR FLIP FLOP
CHARACTERISTIC EQUATION
JK FLIP-FLOP

• Due to the undefined state in the SR flip flop, another flip flop is
required in electronics.
• The JK flip flop is an improvement on the SR flip flop where S=R=1
is not a problem.
• The input condition of J=K=1, gives an output inverting the output
state.
• However, the outputs are the same when one tests the circuit
practically.
• If J and K data input are different (i.e. high and low) then the
output Q takes the value of J at the next clock edge.
JK FLIP-FLOP
JK FLIP-FLOP
CHARACTERISTIC EQUATION
JK FLIP-FLOP
JK FLIP-FLOP

For JK flip-flop if J, K and Clock are equal to 1 the state of flip-

flop keeps on toggling which leads to uncertainty in
determining the output of the flip-flop. This problem is called
Race around the condition
D FLIP FLOP

• D flip flop is a better alternative that is very popular with digital electronics.
• They are commonly used for counters and shift-registers and input synchronisation.
D FLIP FLOP
• In a D flip flop, the output can be only changed at the clock edge,
and if the input changes at other times, the output will be
unaffected.
• The change of state of the output is dependent on the rising edge
of the clock. The output (Q) is same as the input and can only
change at the rising edge of the clock.
T FLIP FLOP

• A T flip flop is like JK flip-flop. These are basically a single input

version of JK flip flop.
• T stands for Toggle
• These flip-flops are called T flip-flops because of their ability to
complement its state (i.e.) Toggle, hence the name Toggle flip-flop.
T FLIP FLOP
T FLIP FLOP
T flip-flop
Single input
When T = 1, at clock edge, T FF changes state. If T = 0, no state
changes.

T Q Q+
0 0 0 Q+ = T’Q + TQ’ = T xor Q
0 1 1
1 0 1
1 1 0
DIFFERENCES BETWEEN LATCHES AND FLIP-
FLOPS

Latches Flip-flops
• Level triggered • Edge triggered
• Asynchronous device • Synchronous device
• Doesn’t contain clock signal • Contains a clock signal
• It will change its state as long as • It will change its state only
it is enabled during a given clock cycle
• Consumes less power • Consumes more power
• Faster • Slower
• Examples: D-Latch, T-Latch • Examples: D-Flip flop, T-Flop flop
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