Table of Contents

EXPERIMENT 1: CMOS INVERTER............................................................................................................ 3

TASK_A: ............................................................................................................................................... 3
Task_B: ................................................................................................................................................ 5
Task_C: ................................................................................................................................................ 6
Task_D: ................................................................................................................................................ 7
Practice Questions: ................................................................................................................................. 8
What is noise margin of a CMOS inverter? ......................................................................................... 8
Explain sizing of an inverter? .............................................................................................................. 9
Draw and explain the transfer curve of an inverter?.......................................................................... 9
EXPERIMENT 2: Layout Design .............................................................................................................. 10
Pre and Post Layout Simulation ........................................................................................................ 10
Practice Questions: ............................................................................................................................... 12
Give five important design technique to follow when doing a layout design of digital circuit? ...... 12
What do you mean by FEOL and BEOL process? .............................................................................. 12
What should be the n-diffusion and p-diffusion layer in lambda rule? ................................................ 13
Experiment_3: ....................................................................................................................................... 14
Multi-stage Inverter with a FAN-OUT-1 : .......................................................................................... 15
Practice Questions: ............................................................................................................................... 17
What is propagation delay? .............................................................................................................. 17
What happens to delay if load capacitance is increased? ................................................................ 17
Why is rise time greater than fall time? ........................................................................................... 18
Experiment_04 ...................................................................................................................................... 19
TASK_A: ............................................................................................................................................. 19
Part_02:............................................................................................................................................. 21
Practice Questions: ............................................................................................................................... 23
What is the difference between D latch and D flip-flop? ................................................................. 23
Write down the characteristic equation of D flip-flop? .................................................................... 24
Describe the operation of a negative edge triggered D flip-flop? .................................................... 24
EXPERIMENT 1: CMOS INVERTER
TASK_A: Draw the schematic of a CMOS inverter. Obtain its DC transfer
characteristics and Transient response for nominal conditions.
Schematic Circuit:

Figure 1: Schematic of the Inverter

Test Bench

Figure 2: Test bench of the Circuit

DC transfer characteristics

Figure 3: DC transfer characteristics of the inverter

Transient Simulations

Figure 4: Transient Simulations of the Inverter

Task_B: Do the parametric analysis for different W/L ratios of the inverter circuit.
[Hint: Vary wp from 2 μm to 10 μm in step size of 1 μm]

Figure 5: DC transfer characteristics of the inverter with different values of the width of the transistors

Sizing of PMOS (Wp)

V mid (mV)
(um)
2u 777.85
3u 853.2
4u 860.5
5u 888.4
6u 908.3
7u 919.2
8u 940
9u 953
10u 973
Task_C: Do the parametric analysis for different temperature conditions. Take the
temperature values as -40˚C, 27˚C, and 100˚C.
Plot the DC transfer characteristics: and tabulate transition voltages for nominally
sized inverter.

Figure 6: DC transfer characteristics of the inverter at different Temperature i.e -40,27 and 100 ˚C

Figure 7: Parametric Simulations

Task_D: Plot the DC transfer characteristics and tabulate transition voltages for
nominally sized inverter.

Figure 8: Transient simulations of the Inverter

Rise and fall time at different temperature

 Temperature Value (˚C) Fall time (ns) Rise Time (ns)
100 4.86 5.44
27 4.47 5.16
-40 4.17 4.9

Figure 9: Rise and fall time w.r.t temperature

Practice Questions:

What is noise margin of a CMOS inverter?

Noise margin is the amount of noise that a CMOS circuit could withstand without
compromising the operation of circuit. Noise margin does makes sure that any signal
which is logic ‘1’ with finite noise added to it, is still recognized as logic ‘1’ and not
logic ‘0’. It is basically the difference between signal value and the noise value. Refer
to the diagram below.

Mathematically, noise margin can be expressed as:

𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿
 𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻
VIL is the maximum input voltage for a logic low at the output.
VOL is the minimum output voltage for a logic low.
VOH is the minimum output voltage for a logic high.
VIH is the minimum input voltage for a logic high at the output.

Explain sizing of an inverter?

The mobility of the NMOS is double of the PMOS that’s why the size of the PMOS is
double of the NMOS.
𝑊 1𝑢𝑚
𝑁𝑀𝑂𝑆 𝑆𝑖𝑧𝑒 = =
𝐿 180𝑛𝑚
𝑊 2𝑢𝑚
𝑃𝑀𝑂𝑆 𝑆𝑖𝑧𝑒 = =
𝐿 180𝑛𝑚

Draw and explain the transfer curve of an inverter?

The transfer curve of an inverter represents its input-output relationship. It typically

shows how the output voltage changes with variations in the input voltage. In an ideal
inverter, the transfer curve is a step function, where the output is high (e.g., 5V) when
the input is low (e.g., 0V), and vice versa.
In practice, due to factors like threshold voltage and switching times, the curve is more
gradual. At low inputs, the output rises slowly until it reaches a threshold, beyond which
it rapidly switches to the opposite state. This transition region is where the inverter's
response is non-linear, affecting its performance in digital circuits.

Figure 10: Transfer curve of an inverter

EXPERIMENT 2: Layout Design
Layout Design

Figure 11: Layout of the Inverter

Pre and Post Layout Simulation

Simulation Fall time (ns) Rise time (ns)

Pre layout simulations 4.475 5.16
Post layout simulations 4.63 5.3
 Figure 12: Pre-layout simulations

Figure 13: Post layout simulations of the Inverter

Practice Questions:

Give five important design technique to follow when doing a layout design
of digital circuit?

Placement Optimization: Arrange components strategically to minimize signal path

lengths, reduce noise coupling, and optimize area utilization. Group related functional
blocks for efficient routing.
Routing Efficiency: Use systematic routing techniques like Manhattan or grid-based
routing to minimize wire length, reduce parasitic effects, and ensure signal integrity.
Avoid crossing signal lines to minimize crosstalk.
Power Distribution: Design a robust power distribution network to provide stable
and uniform supply voltages to all components. Use decoupling capacitors near power
pins to suppress noise and ensure proper functionality.
Signal Integrity: Implement techniques such as shielding sensitive signals, using
differential signaling for high-speed data, and avoiding long parallel traces to
minimize signal distortion, reflections, and electromagnetic interference (EMI).
Design for Manufacturability: Consider manufacturing constraints such as process
technology, layer limitations, and fabrication tolerances. Follow design rules provided
by the fabrication process to ensure manufacturability and yield optimization.

What do you mean by FEOL and BEOL process?

FEOL (Front-End-of-Line) and BEOL (Back-End-of-Line) processes are critical stages

in semiconductor manufacturing, specifically in the production of integrated circuits
(ICs).

FEOL Process (Front-End-of-Line): This phase involves the creation of transistors

and other active components on the semiconductor wafer. It includes steps like
oxidation, ion implantation, deposition of various materials (such as polysilicon and
metal), and etching to define transistor structures. The FEOL process is where the core
functional elements of the IC, such as transistors and diodes, are formed.
BEOL Process (Back-End-of-Line): Following the FEOL process, the BEOL stage
focuses on interconnecting these active components to create a functional circuit. It
involves the deposition of insulating layers (dielectrics), formation of metal
interconnects (wires), vias (connections between metal layers), and top-level
passivation layers for protection. The BEOL process is crucial for creating the intricate
network of connections that allow signals to flow between different parts of the IC.
In summary, FEOL deals with creating active components, while BEOL deals with
interconnecting these components to form a functional integrated circuit. Both
processes are essential for producing advanced semiconductor devices with high
performance and complexity.
What should be the n-diffusion and p-diffusion layer in lambda
rule?
In lambda design rules, the dimensions of the n-diffusion and p-diffusion layers are
specified relative to the minimum feature size denoted by λ.
n-Diffusion Layer: Typically, the n-diffusion layer should be sized at a minimum of
2λ on each side of an n-well for NMOS (n-channel MOSFET) devices. This ensures
proper spacing and isolation between adjacent transistors, reducing the risk of leakage
currents and crosstalk.
p-Diffusion Layer: For PMOS (p-channel MOSFET) devices, the p-diffusion layer
should also be sized at a minimum of 2λ on each side of a p-well. This dimension
maintains symmetry with the n-diffusion layer and supports proper device operation.
These dimensions are crucial for achieving accurate and reliable transistor behavior
within a CMOS (Complementary Metal-Oxide-Semiconductor) process. Adhering to
lambda-based design rules helps ensure proper functionality, electrical performance,
and manufacturability of integrated circuits by controlling transistor sizes, spacings, and
alignments according to the chosen technology node.
Experiment_3:
Extraction of Logical effort and parasitic delay of a CMOS inverter.

Multi-stage Inverter with a FAN-OUT-

Figure 14: Schematic Representation of Multi-stage inverter logic network for FO4

Figure 15: Transient Simulations

Observation:

Rising propagation delay time (tpdr1) = 183.84 ps

Falling propagation delay time (tpdf1) = 1.19 ns
Calculation:
FO4 delay = (tpdr1 + tpdf1)/2 = 5τ
τ= time constant in 137.384 ps

Figure 16: Propagation delay of the Inverter chain designed based on the FO4

Multi-stage Inverter with a FAN-OUT-1 :

Figure 17: Multi-stage Inverter with a FAN-OUT-1

 Figure 18: Propagation delay of the Inverter chain designed based on the FO1

Observation:
Rising propagation delay time (tpdr1) = 1.32 ns
Falling propagation delay time (tpdf1) = 487.4 ps
Rising propagation delay time (tpdr2) = 211.3 ps
Falling propagation delay time (tpdf2) = 111.7 ps
Calculation:
According to d = gh +p, now we have two equations,
From the above simulations we have seen x1 = x4 = 1 for inverter p = 1 *RC of the
inverter. And it is 56.2ps
(𝑡𝑝𝑑𝑟1 + 𝑡𝑝𝑑𝑓1)/2 = 𝑔𝑥4 + 𝑝
903.7 ps = g*1+p
g = 903.7 – 56.3 ps = 847.4 ps
(𝑡𝑝𝑑𝑟2 + 𝑡𝑝𝑑𝑓2)/2 = 𝑔𝑥1 + 𝑝
161.5 ps = g*1+p
g = 161.5 – 56.3 ps = 105.2 ps
Practice Questions:

What is propagation delay?

Propagation delay refers to the time it takes for a signal to travel from the input of a
digital circuit to its output, accounting for the time required for signal propagation
through various components like gates, wires, and interconnects. It is a critical
parameter in digital circuit design as it directly impacts the speed and performance of
the circuit.
In practical terms, propagation delay can be divided into two main components:
Gate Delay: This refers to the time taken for a signal to propagate through the logic
gates in the circuit. Each gate introduces a delay due to its internal operation, which
includes signal propagation through transistors, capacitors, and interconnections.
Interconnect Delay: In addition to gate delays, signals traveling through wires and
interconnects experience a delay known as interconnect delay. This delay is influenced
by factors such as wire length, resistance, capacitance, and routing topology.
Propagation delay is a crucial factor in determining the maximum operating frequency
of a digital circuit. Lower propagation delays allow for faster signal processing and
higher clock frequencies, while longer delays can limit the overall performance and
speed of the circuit.
Designers aim to minimize propagation delays by optimizing circuit layouts, choosing
faster components, and employing techniques like pipelining and parallelism to
improve overall circuit speed and efficiency.

What happens to delay if load capacitance is increased?

When the load capacitance in a digital circuit is increased, the propagation delay typically also increases.
This is because load capacitance affects the time it takes for a signal to transition from one logic state
to another, impacting the overall speed of the circuit.
Here's how increased load capacitance affects delay:
Increased Charging and Discharging Time: A higher load capacitance means that more charge is
required to change the voltage across the load. Consequently, the time taken to charge or discharge the
load capacitance increases, leading to a longer propagation delay.
Slower Signal Transitions: The increased load capacitance slows down the transitions of the signal.
This delay is especially noticeable during the rising and falling edges of the signal, where the voltage
needs to change from one logic level to another.
Impact on Gate Delays: The increased load capacitance can also affect gate delays, as gates need to
drive larger capacitive loads. This can lead to longer gate delays, further contributing to the overall
propagation delay.
Designers often strive to minimize load capacitance to reduce propagation delays and improve circuit
performance. Techniques such as buffering, optimizing signal routing, and using lower-capacitance
components can help mitigate the effects of increased load capacitance on delay.
Why is rise time greater than fall time?

In CMOS circuits, the rise time is typically greater than the fall time due to differences
in the characteristics of p-channel (PMOS) and n-channel (NMOS) transistors. PMOS
transistors have slower response times compared to NMOS transistors due to their lower
electron mobility. This results in slower charging of the output node during rising
transitions, leading to a longer rise time. In contrast, during falling transitions, NMOS
transistors discharge the output node faster, resulting in a shorter fall time.
Experiment_04
Design and characterization of D-Latch and D-FlipFlop in
CMOS Technology.
TASK_A: To Design a D flip-flop using transmission gates as shown in fig.4 (b).

Figure 19: Schematic and Test bench of the D-FlipFlop

 Figure 20: Rise and fall time, propagation delay of the D flipflop

Observation:
Clock Parameters: Rise time = 2 ns
Fall time = 2 ns,
Pulse width = 488 ns,
Period = 1000 ns,
Input Parameters: Rise time = 20 ns
Fall time = 20 ns,
Pulse width = 580 ns,
Period =1200 ns,
Output Parameters: Rise time = 40.2 ps
Fall time = 31.56 ps
Propagation delay = 380.97 ps,
Part_02: To Design a D flip-flop using transmission gates as shown in fig.4 (b).

Figure 21: Schematic and Test bench of the D-latch

 Figure 22: Rise and fall time, propagation delay of the D Latch

Observation:
Clock Parameters: Rise time = 2 ns
Fall time = 2 ns,
Pulse width = 498 ns,
Period = 1000 ns,
Input Parameters: Rise time = 20 ns
Fall time = 20 ns,
Pulse width = 580 ns,
Period =1200 ns,
Output Parameters: Rise time = 16.8 ns
Fall time = 2.183 ns,
Propagation delay = 37.29 ps,
Practice Questions:

What is the difference between D latch and D flip-flop?

A D latch and a D flip-flop are both sequential logic circuits commonly used in digital
systems, but they differ in terms of functionality and operation.
D Latch:
 A D latch, also known as a transparent latch, has a data input (D) and a control
input (often denoted as enable or clock).
 When the control input is high (enable), the D latch operates in transparent mode,
meaning it passes the input data (D) to the output (Q).
 When the control input is low, the latch holds the previous data value at the
output, regardless of changes at the input.
D Flip-Flop:
 A D flip-flop is a clocked sequential circuit with a data input (D), clock input
(CLK), and output (Q).
 The D flip-flop stores data at its input (D) at the rising or falling edge of the clock
signal (CLK), depending on whether it's a positive-edge or negative-edge
triggered flip-flop.
 Unlike a D latch, a D flip-flop does not change its output based on the input when
the clock is not active.
Key Differences:
 A D latch is level-sensitive, reacting to the input as long as the control input is
enabled, while a D flip-flop is edge-triggered, storing data only at clock edges.
 D flip-flops are commonly used in synchronous systems for data storage and
synchronization, while D latches are used for level-sensitive operations or
temporary data storage within a clock cycle.
Write down the characteristic equation of D flip-flop?
The characteristic equation of a D flip-flop describes its behavior and how its output
(Q) changes based on the input (D) and clock signal (CLK). For a positive-edge
triggered D flip-flop, the characteristic equation is expressed as:

Describe the operation of a negative edge triggered D flip-flop?

A negative edge-triggered D flip-flop operates by storing and updating data at its input
(D) on the falling edge of the clock signal (CLK'). Here's how it works:
Initial State: When the clock signal CLK' is high, the flip-flop is in the hold state,
maintaining its current output state.
Data Input Change: When the data input (D) changes while CLK' is high, the flip-flop
does not immediately respond.
Clock Transition: When CLK' transitions from high to low (negative edge), the flip-
flop samples the data input (D) and updates its output accordingly.
Output Update: The updated output is held until the next clock cycle when CLK' rises
again, at which point the process repeats.
This type of flip-flop is used in synchronous digital systems where data needs to be
captured and stored precisely at the falling edge of the clock signal. It provides a stable
and reliable mechanism for data storage and synchronization within digital circuits.