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Experiment 1 PDF

The document describes an experiment to design and simulate a CMOS inverter using the SymicaDE tool. It provides background on CMOS inverters, including their structure, characteristics, and truth table. The experiment details the CMOS inverter circuit design in SymicaDE using 130nm PTM technology. Transient and DC analyses are performed to analyze the input-output voltage behavior and calculate the delay time. The results show the CMOS inverter was successfully designed and simulated in SymicaDE.

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Vmosa
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382 views3 pages

Experiment 1 PDF

The document describes an experiment to design and simulate a CMOS inverter using the SymicaDE tool. It provides background on CMOS inverters, including their structure, characteristics, and truth table. The experiment details the CMOS inverter circuit design in SymicaDE using 130nm PTM technology. Transient and DC analyses are performed to analyze the input-output voltage behavior and calculate the delay time. The results show the CMOS inverter was successfully designed and simulated in SymicaDE.

Uploaded by

Vmosa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Date: 24/08/2020

EXPERIMENT NO. 1

AIM: To design and simulate CMOS inverter using SymicaDE tool.


TOOLS USED: SymicaDE
THEORY: The inverter is universally accepted as the most basic logic gate doing a Boolean
operation on a single input variable. Image 1 depicts the symbol, truth table and a general
structure of a CMOS inverter. As shown, the simple structure consists of a combination of an
pMOS transistor at the top and a nMOS transistor at the bottom. CMOS is also sometimes
referred to as complementary-symmetry metal–oxide–semiconductor. The words
"complementary-symmetry" refer to the fact that the typical digital design style with CMOS
uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor
field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS
devices are high noise immunity and low static power consumption. Significant power is only
drawn while the transistors in the CMOS device are switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistortransistor logic (TTL) or NMOS logic, which uses all n-channel devices
without p-channel devices.

T1

T2

Image 1: CMOS Inverter Circuit

Vin Vout

0 1

1 0

Image 2: Voltage vs Time graph of Ideal CMOS Inverter Table 1: CMOS Inverter Truth Table
CIRCUIT DIAGRAM:

Image 3: CMOS inverter circuit has been successfully designed using SymicaDE tool.

Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns
Table 2: Design specifications of CMOS Inverter

OBSERVATIONS:
V1= 1.8 V, V2= 0V
Period= 100nsec, Pulse Width=50nsec

Transient Analysis:
Simulated Delay Time: 6.02111e-009
Image 4: Transient Analysis Input and Output

DC Analysis:

Image 5: DC analysis Output

RESULT:
• CMOS inverter circuit has been successfully designed using SymicaDE tool.
• Transient and DC analysis performed also delay time is also calculated.

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