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ECE429 Laboratory 4 NAND Schematic: Bapu A20489420 21/09/2021

The document discusses the design and analysis of a CMOS inverter. It covers the theory of operation, schematic creation in Cadence Virtuoso, simulation in HSPICE, and analysis of timing characteristics like delay and trip point for different transistor widths and loads. Key conclusions are that inverter delay depends on factors like transistor strength, load capacitance, and supply voltage.

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Prasanna Nalawar
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57 views

ECE429 Laboratory 4 NAND Schematic: Bapu A20489420 21/09/2021

The document discusses the design and analysis of a CMOS inverter. It covers the theory of operation, schematic creation in Cadence Virtuoso, simulation in HSPICE, and analysis of timing characteristics like delay and trip point for different transistor widths and loads. Key conclusions are that inverter delay depends on factors like transistor strength, load capacitance, and supply voltage.

Uploaded by

Prasanna Nalawar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ECE429 Laboratory 4

NAND Schematic

Bapu
A20489420
21/09/2021
Contents
 Introduction
 Theory/Pre-Lab
 Implementation
 Conclusion
Introduction (Inverter)
Inverter is a basic gate for every digital design. The function of the inverter is to
invert its input and provide the inverted output. Following are the few basic points
about inverter gate
 One input and one output terminal
 Output is always controlled by input unlike sequential circuit where
enable/clock signal is also required to have desired output
 CMOS inverter is made up of one PMOS and one NMOS
 The truth table and ideal waveform of inverter is shown below.
0 => Logical 0 (GND)
1 => Logical 1 (VDD)
BAR => Represents inversion

IN OUT Logical Expression


0 1
OUT = BAR(IN)
1 0

 It can be used as a delay element in digital design to introduce a specific


delay in any of the logic path
 Chain of odd number of inverters can be used as a oscillator
 All inputs in digital design generally hits to INV first in any block for power
isolation
Theory/Pre-Lab
As mentioned in the introduction section, there are many applications of CMOS-
inverter. All these applications pose different specifications for inverter.
Commonly used CMOS inverter is represented below with its symbol and
schematic view.

Inverter ideal waveform in time domain in represented below. This waveform is


assumed to be ideal because of the following reasons

1. Output rise and fall slope is assumed to be 0


2. No delay between input and output
In real CMOS circuits, inverter time domain characteristics are measured in
following parameters.

1. Transient delay

Transient delay is the delay between input and output signals. Transient delay is a
function of following parameters
 Input signal slope and its voltage value
 Output capacitance load
 Device(PMOS and NMOS) strengths
 VDD voltage value

2. Rise/Fall slope

Rise/fall slope is the time taken by output signal to reach its high/low value. For
example, generally rise slope is measured from 10% to 90% and fall slope is
measured from 90% to 10%. Rise/fall slopes are also function of following
parameters
 Input signal slope and its voltage value
 Output capacitance load
 Device(PMOS and NMOS) strengths
 VDD voltage value
Implementation
To analyze the real CMOS inverter non-ideal characteristics, we need to create
the inverter schematic (mentioned in theory section) using available PMOS and
NMOS models. To do this, majority of the people will use cadence-virtuoso
tool which helps us to draw schematic. Also, we can take out the netlist for the
simulation. There are many simulators available in the industry and most
widely used one is HSPICE by Synopsys. In this section, I will brief about the
schematic creation and its simulation for different load, slew conditions.

Schematic and testbench creation:

Step-1: Virtuoso setup. To do this, I have followed the steps mentioned in


the tutorial-1

Step-2: Library creation (File => New => Library); attaching technology
library
Step-3: Schematic view creation (File => New => CellView); assigning the
“width” and “length” values; INV symbol creation (Create => Cellview =>
From Cellview)
Step-4: Inverter testbench creation. Schematic creation procedure is
followed and added VDC/GND/VPULSE elements from “analogLib”
library.

Step-5: Hspice netlist which is simulated


Step-6: Inverter functionality verified using “hspice”

Step-7: Inverter output waveform and delay for different PMOS and
NMOS widths
PMOS=100nm PMOS=140nm PMOS=180nm
Delay
NMOS=90nm NMOS=90nm NMOS=90nm
VDD=1V
Rise (in ps) 11.58 8.85 7.19
Models = NOM
Fall (in ps) 8.58 8.86 9.11
Cload = 1fP
Rise / fall
135% 100% 79%
ratio

From the above waveform and table we can conclude on the following points:

1. Even though PMOS width (100nm) is more than NMOS width (90nm), fall
delay is smaller than rise delay. This is because; the charge carriers in
PMOS (holes) are slower than charge carriers in NMOS (electrons)
2. When PMOS width is 140nm and NMOS width is 90nm then rise and fall
delays are almost same. This means that the mobility difference between
PMOS and NMOS for 45nm technology is ~55%
3. In the above table it is also shown that fall delay is increasing with PMOS
width increase even though the NMOS size is not reduced. This is
happening because when we increase the PMOS strength as compared to
NMOS then the tripping point of inverter shifts towards VDD and hence
increases fall delay

Step-8: Inverter output waveform and delay for different Cload


Delay Cload = 1fP Cload = 5fP
Rise (in ps) 11.58 39.92 PMOS_W = 100nm
NMOS_W=90n
Fall (in ps) 8.58 28.96
VDD=1V
Rise / fall Models = NOM
135% 138%
ratio

1. Output delay will increase as we increase the capacitance on OUT node.


This is because the time constant (R*C) will increase. The rise or fall delay
is a function of (R*C) where C->Cload & R is nothing but resistance of
PMOS/NMOS
2. When the time constant (R*C) is more that pulse width, then OUT will not
reach to neither 0V nor 1V.
3. To make OUT reaches 0V/1V properly, we have to do the following
a. Reduce capacitance on OUT node
b. Increase device strength to reduce device resistance
c. Increase pulse width or period which in turn affects the frequency of
operation
d. Increase device strength by increasing input gate voltage (Vgs) of
PMOS/NMOS

Step-9: Inverter trip point analysis which we have seen during step-7

Netlist change for trip point analysis


1. Inverter trip point is a point where Vin=Vout
2. This is one of the major components in determining delay
3. In this experiment I have measured trip point using .TRAN analysis instead
of .DC analysis
4. As we are seeing in above table, waveform and graph the inverter trip point
is increasing with increasing in PMOS width. This is happening because as
we increase PMOS width keeping NMOS width constant, the inverter trip
point will move towards VDD
Questions mentioned in lab tutorial:

 Where are the bodies of the transistors in your schematic?


o PMOS body is connected to VDD and NMOS body is connected to
GND. This is done to avoid the forward bias diode current between
source and body terminals
• What are the widths and lengths of your transistors?
o PMOS=100nm; NMOS=90nm; Mentioned in schematic snapshot
• How much is the supply voltage?
o VDD=1V; Mentioned in the above snapshots
• What do ‘Rise time’ and ‘Pulse width’ mean for ‘vpulse’? Can you locate
these two values in the waveforms obtained from the SPICE simulation?
o Mentioned in the above snapshots
• Tutorial I shows a maximum rising delay of 7.1892p. How long is that in
seconds?
o It will be 7.1892e-12s
• To obtain an inverter design with equal rising and falling delays, will you
make the PMOS transistor larger or smaller?
o Since PMOS charge carriers are holes which less mobile than NMOS
charge carriers which are electrons, we need to have larger PMOS to
make rise and fall delay same for inverter
Conclusion
I would like to conclude this lab exercise with the following points

1. Inverter is the key element for any digital logic design


2. Through understanding of inverter timing, power, dc, noise characteristics
are very important
3. In this exercise we have mainly focused on timing characteristics with
different loads etc and below are the conclusion points for timing
characteristics
a. Inverter or any logic gate delay is most important to determine the
frequency of operation
b. To have optimum frequency many parameters need to be optimized
considering the tradeoff between speed, area, dynamic power, leakage
power, noise etc
c. The following parameters are important during any inverter design
i. Inverter size (Trade-off between speed and area/power)
ii. Capacitance reduction (With lower technologies it is becoming
difficult to have minimum capacitance. Many paths are RC
dominated rather that gate delay dominated)
iii. VDD value (This would determine many items like speed,
reliability, power, voltage guard band etc)

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