NMK 22003

INTEGRATED CIRCUIT DESIGN

LAB REPORT

NAME : MOHAMMAD NABIL BIN NAINA

MOHAMAD
Matric.No : 241391755

Programme : UR6523008-TELCO

Date : 05/11/2024
Introduction:

Analyzing and verifying a CMOS inverter circuit using Pyxis Project Manager
software enables designers to simulate and validate essential circuit
properties effectively. The CMOS inverter, comprising complementary PMOS
and NMOS transistors, serves as a foundational digital logic component. With
Pyxis, engineers can create and simulate the inverter layout, ensuring accurate
modeling of switching behavior, noise margins, and power consumption. By
running SPICE simulations within Pyxis, designers can verify performance
metrics and identify potential design improvements, ensuring the circuit
meets industry standards for digital applications.

Objectives:

The objective to construct, analyze, and verify the CMOS inverter circuit has been successfully achieved.
Through detailed circuit modeling and simulation using Pyxis Project Manager, the CMOS inverter was
carefully constructed and tested to meet key performance criteria. Simulations validated the expected
switching behavior, voltage transfer characteristics, and power efficiency, ensuring that the inverter
operates within design specifications. This accomplishment confirms the robustness and reliability of the
circuit, ready for integration into larger digital logic systems.
Methodology:

Figure 1: CMOS Schematic

 Figure 2: Inverter symbol is generated.

Figure 3: Inverter schematic for simulation

Figure 4: Shows the graph for simulation result. The voltages oh V(IN) and V(OUT) is shown
Results & Discussion:

Figure 5: Shows the delay when output switches from low to high.

Figure 6: Shows the delay when output switches from high to low
Therefore, now we can find the Propagation delay when output switches from low to high:

Tphl = 51.52000ns - 51.49223ns = 0.02777ns

Figure 7
 Figure 8

Write your comment on the drain current I(D).

The drain current I(D) in a CMOS inverter fluctuates as the transistor states change during switching.
Regions A, B, C, D, and E are involved. The NMOS is inactive while the PMOS is active in Region A,
leading to the elevation of Vout. Consequently,Input voltage near ground causes the PMOS to stay on,
while the NMOS transitions into saturation as the input voltage increases.Entering Zone B allows for a
moderate I(D). Both transistors in Zone C are in saturation, leading to.There is a high current flow and
a drastic decrease in Vout. The PMOS is in saturation and the NMOS is in the linear region.In Region D,
the current I(D) decreases as the output voltage Vout decreases. Eventually, in Region E, the PMOS
switches off when the input voltage Vin is high.The NMOS lowers Vout towards the ground, resulting
in I(D) returning to almost zero. This indicates that I(D) is at a low level.In Regions A and E, the level is
moderate in Region B, reaches its highest point in Region C, and then declines in Region D, as per the
given information

End the simulation, change the width (Wp) of the pMOS from 0.70um to 0.35um. Use equation 3 in
page24, calculate the switching voltage of the CMOS inverter:

VTH = √0.35um/2(0.35um) (1.2v + (-0.3)+0.25)

1 + √0.35um / 2(0.35um)

VTH = 0.519v
 Figure 9

Calculate the switching voltage for both Wp = 0.15um and Wp = 1.0um

When Wp = 0.15um , switching voltage = 0.517v

When Wp = 1.0um, switching voltage = 0.669971v

From the simulation waveform,

When Wp = 0.15um, switching voltage = 0.49v

When Wp = 1.0um, switching voltage = 0.59577v

Discussion:

The objective of this laboratory experiment is to design, construct, and analyze a CMOS inverter
circuit, and verify its functionality using ORACLE software for circuit simulation. A CMOS inverter is
composed of a PMOS and an NMOS transistor. The PMOS acts as a pull-up device, while the NMOS
serves as a pull-down device. When the input is LOW, the PMOS conducts, producing a HIGH output.
Conversely, when the input is HIGH, the NMOS conducts, resulting in a LOW output.

The circuit is constructed by connecting the drain of the PMOS to the power supply (VDD_{DD}DD)
and its source to the output node. The NMOS is connected with its drain at the output node, source to
ground, and gate tied to the same input as the PMOS. The simulation process involves modeling the
circuit in ORACLE software using appropriate transistor models with matching thresholds.

In ORACLE software, DC analysis is performed to obtain the voltage transfer characteristic (VTC) curve,
which illustrates the output voltage transition as the input voltage changes. Transient analysis is
conducted by applying a pulse signal at the input to observe the dynamic response of the inverter,
including switching speed and signal integrity. The results confirm that the CMOS inverter functions as
expected, producing an output logic level that is the inverse of the input.

The simulation results also verify the low static power dissipation of the CMOS inverter, consistent
with its theoretical design. The VTC curve shows a sharp transition between logic states, and the
transient analysis validates the inverter’s speed and reliability. In conclusion, the CMOS inverter was
successfully constructed and analysed, with ORACLE software confirming its theoretical and practical
performance.

Conclusion:

In conclusion, the CMOS inverter was successfully designed, constructed, and analyzed. The
theoretical operation of the inverter was validated through both practical circuit implementation and
simulation using ORACLE software. The voltage transfer characteristic (VTC) curve demonstrated a
sharp transition between logic states, confirming accurate inversion of the input signal. The transient
analysis verified the inverter’s switching speed and signal integrity, while power dissipation analysis
highlighted its low static power consumption. Overall, the experiment confirmed the efficiency and
reliability of the CMOS inverter, making it an essential component in digital circuit application.