DON BOSCO INSTITUTE OF TECHNOLOGY

DEPARTMENT OF INFORMATION SCIENCE& ENGINEERING

Module Wise Question Bank

SUB(CODE):DDCO(BCS302) Batch:2023
Academicyear:2024-25(ODDSem) Sem:3

MODULE1
1. Describe positivelogic and [Link] the equivalences inpositiveandnegative
logic.
2. Realizethe XORgate using(i)NANDgate (ii)NOR gate.

3. DefinecanonicalMintermformandcanonicalMaxtermform.

4. Expressthefunction F=x+yzasthe sumofits mintermsandproduct ofmaxterms

(i) ΠM(1,3,4,7)(ii)ΠM(0,1,2,4,10,13,15)
6. Findtheminimal SOP andminimal POS ofthefollowing Boolean function using K-Map.
f(a,b,c,d)m(6,7,9,10,13)d(1,4,5,11)
7. Withanexample explainduality?

8. ListallPostulatesandTheoremsavailableinBooleanalgebra?

9. Stateand ProveAbsorptionTheorem.

10. FindthecomplementandsimplifytheBooleanfunctionandalsowritelogiccircuit F = A ′
B ′C ′ + A ′ BC .
11. Drawatwo-levellogicdiagramtoimplementtheBooleanfunction F =
BC ′ + A B + A C D .
12. Demonstratingthenon-associativityofthebelowoperator: ( x
↓y ) ↓ z ≠ x ↓ ( y ↓ z )(3M)
13. DefinenegativelogicandWritethe equivalentnegativelogicforpositiveNANDgate.
14. Implementthe BooleanfunctionF=yz +z′ y′ + x ′ zWithNAND and inverter gates.
15. Simplifythefollowing using K-MaptechniqueandfindtheEssentialPrimeImplicants.
(i) Pf (w,x,y,z)m(7,9,12,13,14,15) d(4,11)
(ii) Y f(a,b,c,d)(0,1,2,6,7,9,10,12)d(3,5).VerifytheresultusingK-map.
(iii) f(A,B,C,D)m(0,1,2,3,10,11,12,13,14,15)
(iv) f(W,X,Y,Z)m(1,3,6,7,8,9,10,12,13,14)
16. [Link]
circuitusing the gates as indicated:
 (i) f(w,x,y,z)m(1,5,7,9,10,13,15)d(8,11,14)usingNANDgates.
(ii) f(A,B,C,D)M(0,1,2,4,5,6,8,9,12,13,14)usingNORgates.

17. Simplify the following Boolean expressions, using four-variable K- maps and design using
Nand and Nor gates.
F (A, B, C, D) =AD' + B'C'D + BCD' + BC'D
F(A, B, C, D) = πM(1, 2, 3, 7, 13, 15)
F (w, x, y, z) = ϵm (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)

18. Implement the following Boolean expressions, using Nand and Nor gates. F (x, y, z)
= Σ (0, 6,8,13,14) + d (1, 3, 10)

19. Design the multiple-level NOR and NAND circuit for the following expression: F=CD (B
+ C) A + (BC' + DE')

20. Demonstrate the validity of the following identities by means of truth tables: i. DeMorgan’s
theorem for three variables: (x + y + z)' = x'y'z' and (xyz)' = x' + y' + z'
ii. The distributive law: x (y + z) = xy + xz

21. Design AND, OR, Xor and Invert using NAND and NOR gates

22. Implement the following Boolean function F, using the two-level forms of logic (a)
NAND-AND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR
F (A, B, C, D) = ϵm (0, 4, 8, 9, 10, 11, 12, 14)

23. Draw the logic diagram of the digital circuit specified by the following Verilog
description:
module Circuit_A (A, B, C, D, F);
input A, B, C, D;
output F;
wire w, x, y, z, a, d;
or (x, B, C, d);
and (y, a, C);
and (w, z, B);
and (z, y, A);
or (F, x, w);
not (a, A);
not (d, D);
endmodule

24. Explain Nand gate, Nor gate and Xor gate with truth table and timing diagram for three input
variables a, b and c respective
MODULE2

1. Whatisamultiplexer?[Link] and
explain its working principle.
2. Construct4:1multiplexerusingonly2:1multiplexerandalsowriteVerilogprogram.
3. Construct8:1multiplexerusingonly2:1multiplexer.
4. Design32to 1multiplexerusing 16 to1 multiplexerandone2to1 multiplexer.
5. Design4:1multiplexerforBooleanfunctionf(A,B,C)=Σ(0,2,3,5,6,7)
6. Design8:1multiplexerforBooleanfunctionf(A,B,C,D)=Σ(0,2,4,5,8,10,14)
7. Mention the differences between decoder and demultiplexer.
8. Design3:8decoderforfullsubtractor .
9. Design2:4DecoderforBooleanfunctionf1(a,b)=Σ(0,2,3),f2(a,b)=Σ(1,2),
10. Design a priority encoder for a system witha3 inputs.
11. Give characteristic table and equation of SR,D, JKand Tflip flops.
12. Explaintheoperationofedgetriggered‘SR’flipflopwiththehelpofalogicdiagram and
truth table. Also draw the relevant waveforms.
13. Explain the working of MasterSlave JKflip flops with logic diagram.
14. Explain the operation ofD,T,SR, andJK latches.
15. Differentiate between Latch and flipflop.
16. Write difference between sequential circuits and combinationalcircuits.
17. Write Verilog program for demultiplexer,multiplexer,flip-flops.
18. Write the verilog HDL code for (i)Two to one line MUX (ii)Two to four line decoder (iii)Full
adder using half adder module.
20. Design a combinational circuit to convert BCD to Excess-3 or can ask any
design.
21. Design 4-bit parallel adder/ subtractor circuit.
22. Explain carry look ahead adder circuit with block diagram.
Or
What is a binary subtractor, explain.
23. Explain half adder/subtractor and design full adder using 2 half adders.
Or
Explain the full adder with the help of TT and Logic diagram
24. What is a decoder? Construct a two four line decoder with enable input along with
TT and Explain
25. Define Multiplexer? Explain 8:1 mux with the help of Logic diagram and logic
expression, Also implement function F (A, B, C, D) = ϵm (1,2,5,6,9,12) using 8:1 Mux
26. Design 32:1 MUX using 8:1 MUX and 4:1 MUX with the help of logic expression.
27. Explain the operation of JK, SR T and D flip flop and Positive edge triggered D Flip
flop with Characteristic table and truth table.
[Link] the working of SR Latch using NOR gates, show how SR Latch can be used
for switch debouncing.
  
29. (a)Realize YA BB C ABC usingan 8 to 1 Multiplexer.
(b)Can it be realized witha 4to 1 multiplxer?
MODULE3
1. With a neat diagram explain the different processor registers.

2. What are the factors that affect the performance? Explain any 4.

3. What is performance measurement? Explain the overall SPEC rating for a computer in a
program suite.

4. Write the difference b/w RISC and CISC processors.

5. A program contains 1000 instructions. Out of that 25% instructions requires 4 clock cycles,
40%instructionsrequires5clock cycles and remainingrequires3 clock cyclesforexecution. Find
the total time required to execute the program running in a 1GHz machine.

6. Write a note on byte addressability, big-endian and little-endian assignment.

7. Explain the basic operational concepts b/w the processor and the memory.

8. Derive the basic performance equation? Discuss the measures to improve the performance.

9. Explain processor clock and clock rate.

10. What is an addressing mode?Explain any fouraddressing modes.

11. WriteALPprogramtocopy‘N’numbersfromarray‘A’toarray‘B’usingindirect
addresses.(AssumeAandBarethestartingmemorylocationofaarray).

12. With a neat blockdiagram, describe the I/O operation.

13. Explain functional units of computer.

14. Discuss connection betweenprocessorandmemory.

15. Mention four types of operations to be performed by instructions in a computer. Explain with
basic types of instructions formats to carry out C<-[A]+[B].

16. HowinputandoutputoperationperformedbyProcessor?

17. With a neat diagram explain the basic operational concepts of computer , explain the
registers
of processor and explain the sequence of steps

17. Analyze Big-Endian and little-Endian methods of byte addressing with example.

18. WAP to evaluate Y= A*B+C*D or A+B*C+D is executed using one address, two address and
three address and zero address instruction

19. Define instruction sequencing and branching. Explain conditional flags and the concept of
branching with an example program
[Link] is performance measurement? Explain the overall SPEC rating.

[Link] processor clock, clock rate, basic performance equation and

[Link] all the addressing modes with examples

23. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the
effective- address of the memory operand in each of the following instructions?
(a) Load 20(R1), R5 (b) Move #3000, R5 (c) Store R5,30(R1, R2) (d) Add -(R2), R5 (e) Subtract
(R1)+, R5.

24. Consider the following possibilities for saving the return address of a subroutine: (a) In the
processor register. (b) In a memory-location associated with the call, so that a different location
is
used when the subroutine is called from different places (c) On a stack. Which of these
possibilities
supports subroutine nesting and which supports subroutine recursion(that is, a subroutine that
calls
itself)

MODULE4
1. Draw the arrangement of a single bus structure and briefexplain about memory mapped
I/O and program mapped I/O.
2. Whatisaninterrupt?Withexampleillustratetheconceptof interrupts.
3. Explain in detail the situation where a number of devices capable of initiating interrupts
are connected to the processor? How to resolve the problems?
4. Explaininterruptenabling,interruptdisabling,edgetriggeringwithrespecttointerrupts
5. Explainthefollowingtermsa)interruptserviceroutineb)interruptlatencyc)interrupt disabling.
6. Withneatsketches explain variousmethodsforhandlingmultipleinterruptrequests.
7. Explain how interrupt request from several I/0 devices can be communicated
toaprocessorthrough a single INTR line.
8. Definebusarbitration. Explain indetailboth approachofbus arbitration.
9. Drawthearrangementforbusarbitrationsusing adaisychainand explaininbrief.
10. Whatarethedifferent [Link] brief.
11. WhatisDMA?Explainthehardware registersthatarerequiredina DMA controller chip.
12. ExplaintheuseofDMAcontrollerinacomputersystem withaneat diagram.
13. Showwithdiagram thememoryhierarchy withrespect tospeed, size and cost.
14. Explaindifferentmapping functionsusedincache memory.

15. How the input and output are performed by the processor? Write a program that reads the
line or characters and displays it.
16. Differentiate memory mapped I/O and I/O mapped I/O
17. With neat sketches explain various methods for handling multiple interrupts raised by
multiple devices. (or explain how I/O devices are organized in priority structure)
 18. Define Interrupt and interrupt hardware. how enabling and disabling of interrupts are
performed.
19. Define exceptions, describe different kinds of exceptions.
20. Explain operation of DMA controller with neat block diagram.
21. Define DMA bus arbitration. Explain centralized and distributed bus arbitration.
22. Draw a neat diagram of memory hierarchy in a computer system. Discuss the variation of
size,speed and cost per bit in the hierarchy.
23. What is cache memory? Explain different mapping functions with diagrams.

MODULE5

1. Discussinternalorganizationofprocessorwithneatdiagram.
2. Explainwithneeddiagramasingle-busorganizationcomputerandfundamentalconcepts.

3. Writeandexplainthecontrolsequencesfortheexecutionofthefollowing instruction:
Add(R3),R1.
4. Explainbasic ideaofpipelining and4-stagepipelinestructure.
5. Discuss2-stagepipelinestructure with neat diagram.
6. Explaintheroleofcache memory in pipelining.
7. whatispipelining?Explain withneatsketchespipelining performance.

8. Write and explain the control sequence for execution of the instruction ADD (R3), R1 on
a single bus processor.
Or
Write and explain the control sequence for execution of an unconditional branch instruction
9. Explain the 3-bus organization of a data path with a neat diagram.
10. With a neat diagram explaining single bus processor data path wrt organization of
11. computer and fundamental concepts.
12. Write and explain the control sequence for execution of an unconditional branch
instruction.
13. Write a note on register transfer and ALU operation.
14. Briefly explain fetching a word from memory and storing a word in memory.
15. Explain in detail (i) Hazards and its types with examples (ii) pipeline performance
(iii)role of cache in pipelining (iv)process of fetching a word from memory with diagram

16. What is a stall or bubble in the pipeline? Explain in detail with example.

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