Module wise Question Bank

SUB (CODE): DDCO(BCS302) Batch: 2022

Academic year : 2023-24 (ODD Sem) Sem: 3

MODULE 1
1. Describe positive logic and negative logic. List the equivalences in positive and negative
logic.
2. Realize the XOR gate using (i) NAND gate (ii) NOR gate.
3. Define canonical Minterm form and canonical Maxterm form.
4. Express the function F=x+yz as the sum of its minterms and product of maxterms
5. Convert the following 4-variable POS to SOP form.
(i) ΠM(1,3,4,7) (ii) ΠM(0,1,2,4,10,13,15)
6. Find the minimal SOP and minimal POS of the following Boolean function using K-Map.
f (a, b, c, d ) = m(6, 7, 9,10,13) + d (1, 4, 5,11)
7. With an example explain duality?
8. List all Postulates and Theorems available in Boolean algebra?
9. State and Prove Absorption Theorem.
10. Find the complement and simplify the Boolean function and also write logic circuit
F = A ′ B ′C ′ + A ′ B C .
11. Draw a two-level logic diagram to implement the Boolean function
F = BC ′ + A B + A C D .

12. Define negative logic and Write the equivalent negative logic for positive NAND gate.
13. Implement the Boolean function F = yz + z ′ y ′ + x ′ z With NAND and inverter gates.
14. Simplify the following using K-Map technique and find the Essential Prime Implicants.
(i)P = f (w, x, y, z) = m(7, 9,12,13,14,15) +  d (4,11)
(ii)Y = f (a, b, c, d ) = (0,1, 2, 6, 7, 9,10,12) + d (3, 5). Verify the result using K-map.
(iii) f ( A, B, C, D) = m(0,1, 2, 3,10,11,12,13,14,15)
(iv) f (W , X ,Y , Z ) = m(1, 3, 6, 7,8, 9,10,12,13,14)
15. Simplify the following expressions using Karnaugh map. Implement the simplified
circuit using the gates as indicated:
(i) f (w, x, y, z) = m(1, 5, 7, 9,10,13,15) + d (8,11,14) using NAND gates.
(ii)f ( A, B, C, D) = M (0,1, 2, 4, 5, 6,8, 9,12,13,14) using NOR gates.
MODULE 2

1. What is a multiplexer? Design a 4 to 1 multiplexer using logic gates. Write the truth table
and explain its working principle.
2. Construct 4:1 multiplexer using only 2:1 multiplexer and also write Verilog program.
3. Construct 8:1 multiplexer using only 2:1 multiplexer.
4. Design 32 to 1 multiplexer using 16 to 1 multiplexer and one 2 to 1 multiplexer.
5. Design 4:1 multiplexer for Boolean function f(A,B,C)=Σ(0,2,3,5,6,7)
6. Design 8:1 multiplexer for Boolean function f(A,B,C,D)=Σ(0,2,4,5,8,10,14)
7. Mention the differences between decoder and demultiplexer.
8. (a) Realize Y = AB + BC + ABC using an 8 to 1 Multiplexer.

(b) Can it be realized with a 4 to 1 multiplxer?

9. Design 3: 8 decoder for full subtractor .
10. Design 2:4 Decoder for Boolean function f1(a,b)= Σ(0,2,3), f2(a,b)= Σ(1,2),
11. Design a priority encoder for a system with a 3 inputs.
12. Give characteristic table and equation of SR, D, JK and T flip flops.
13. Explain the operation of edge triggered ‘SR’ flip flop with the help of a logic diagram
and truth table. Also draw the relevant waveforms.
14. Explain the working of Master Slave J K flip flops with logic diagram.
15. Explain the operation of D, T,SR, and JK latches.
16 . Differentiate between Latch and flip flop.
17. Write difference between sequential circuits and combinational circuits.
18. write Verilog program for demultiplexer, multiplexer, flip-flops.

MODULE 3
1. With a neat diagram explain the different processor registers.

2. What are the factors that affect the performance?Explain any 4.

3. What is performance measurement? Explain the overall SPEC rating for a computer in a
program suite.

4. Write the difference b/w RISC and CISC processors.

5. A program contains 1000 instructions. Out of that 25% instructions requires 4 clock cycles,
40% instructions requires 5 clock cycles and remaining requires 3 clock cycles for execution.
Find the total time required to execute the program running in a 1GHz machine.

6. Write a note on byte addressability,big-endian and little-endian assignment.

7. Explain the basic operational concepts b/w the processor and the memory.
8. Derive the basic performance equation? Discuss the measures to improve the performance.

9. Explain processor clock and clock rate.

10. What is an addressing mode? Explain any four addressing modes.

11. Write ALP program to copy ‘N’ numbers from array ‘A’ to array ‘B’ using indirect
addresses.(AssumeAandBarethestartingmemorylocationofaarray).

12. With a neat block diagram, describe the I/O operation.

13. Explain functional units of computer.

14. Discuss connection between processor and memory .

15.Mention four types of operations to be performed by instructions in a computer. Explain with

basic types of instructions formats to carry out C<-[A]+[B].

16.How input and output operation performed by Processor?

MODULE 4
1. Draw the arrangement of a single bus structure and brief explain about memory mapped I/O
and program mapped I/O.
2. What is an interrupt? With example illustrate the concept of interrupts.
3. Explain in detail the situation where a number of devices capable of initiating interrupts are
connected to the processor? How to resolve the problems?

4. Explain interrupt enabling,interrupt disabling,edge triggering with respect to interrupts

5. Explain the following terms a) interrupt service routine b) interrupt latency c) interrupt
disabling.

6. With neat sketches explain various methods for handling multiple interrupt requests.

7. Explain how interrupt request from several I/0 devices can be communicated toaprocessor
through a single INTR line.

8. Define bus arbitration. Explain in detail both approach of bus arbitration.

9. Draw the arrangement for bus arbitrations using a daisychain and explain in brief.
10. What are the different methods of DMA. Explain in brief.

11. What is DMA? Explain the hardware registers that are required in a DMA controller chip.

12. Explain the use of DMA controller in a computer system with a neat diagram.
13. Show with diagram the memory hierarchy with respect to speed , size and cost.

14. Explain different mapping functions used in cache memory.

MODULE 5

1. Discuss internal organization of processor with neat diagram.

2.Explain with need diagram a single-bus organization computer and fundamental concepts.
3. Write and explain the control sequences for the execution of the following
instruction: Add(R3),R1.
4. Explain basic idea of pipelining and 4-stage pipeline structure.
5. Discuss 2-stage pipeline structure with neat diagram.
6. Explain the role of cache memory in pipelining.
7. what is pipelining? Explain with neat sketches pipelining performance.