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Fourth Semester
Electrical And Electronics Engineering
Scheme July 2009
DIGITAL TECHNIQUES AND APPLICATIONS
Time : Three Hours Maximum Marks : 100
Note : i) Attempt total six questions. Question No. 1 (Objective type)
is compulsory. From the remaining questions attempt any five.
Hw$b N>… àíZ hb H$s{OE & àíZ H«$‘m§H$ 1 (dñVw{Zð> àH$ma H$m)
A{Zdm¶© h¡ & eof àíZm| ‘| go {H$Ýht nm±M H$mo hb H$s{OE &
ii) In case of any doubt or dispute, the English version question
should be treated as final.
{H$gr ^r àH$ma Ho$ g§Xoh AWdm {ddmX H$s pñW{V ‘| A§J«oOr ^mfm Ho$
àíZ H$mo A§{V‘ ‘mZm Om¶oJm&

1. Choose the correct answer. 2 each

ghr CÎma H$m M¶Z H$s{OE&
i) Which number system has a base of 8
(a) decimal (b) octal
(c) hexadecimal (d) none of these
{ZåZ{b{IV ‘| go H$m¡Z-gr Zå~a àUmbr H$m AmYma 8 hmoVm h¡
(A) S>ogr‘b (~) Am°³Q>b
(g) ho³gmS>ogr‘b (X) Cnamo³V ‘| go H$moB© Zht
ii) A NAND gate is called a universal logic element because
(a) It is used by every body
(b) Any logic function can be realized by NAND gates alone
(c) All the minimization techniques are applicable for optimum
NAND gate realization
(d) Many digital computers use NAND gate

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NAND gate H$mo gmd©O{ZH$ bm°{OH$ VËd H$hm OmVm ³¶m|{H$

(A) Bgo g^r Ho$ Ûmam Cn¶moJ {H$¶m OmVm h¡&
(~) H$moB© ^r bm°{OH$ ’§$³eZ Ho$db NAND gate Ho$ Cn¶moJ go ~Zm¶m
(realized) Om gH$Vm h¡&
(g) g^r {‘Zr‘mBOoeZ VH$ZrHo$ Ho$db NAND gate [a¶bmBOoeZ hoVw
AZwà¶moJr h¡&
(X) H$B© {S>{OQ>b H$å߶yQ>am| ‘| NAND gate H$m Cn¶moJ {H$¶m OmVm h¡
iii) The gates required to build a half adder are
(a) Ex-OR gate and NOR gate
(b) Ex-OR gate and OR gate
(c) Ex-OR gate and AND gate
(d) Four NAND gate
hm°’$ ES>a ~ZmZo Ho$ {b¶o ______ JoQ²>g H$s Amdí¶H$Vm hmoVr h¡
(A) Ex-OR JoQ> Ed§ NOR JoQ>
(~) Ex-OR JoQ> Ed§ OR JoQ>
(g) Ex-OR JoQ> Ed§ AND JoQ>
(X) Mma NAND JoQ>
iv) Which of the following memory is volatile memory
{ZåZ{b{IV ‘| go H$m¡Z-gr ‘o‘moar dmoboQ>mBb ‘o‘moar h¡
(a) ROM (b) RAM
(c) PROM (d) EEPROM
v) The digital logic family which has the lowest propagation delay
time is ______
{ZåZ{b{IV ‘| go {H$g {S>OrQ>b bm°{OH$ ’¡${‘br H$m àmonoJoeZ {S>bo Q>mB‘
ݶyZV‘ ({ZåZV‘) hmoVm h¡
(a) ECL (b) TTL
(c) CMOS (d) PMOS

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2. a) i) Explain De-Morgan’s theorem and verify it. 4

{S>-‘m°J©Z à‘o¶ H$mo g‘PmB¶o Am¡a Bgo g˶m{nV H$s{OE&
ii) Realise the following logic operations using NAND gates
only. 6
{ZåZ{b{IV bm°{OH$ Am°naoeZm| H$mo {g’©$ NAND JoQ> H$m Cn¶moJ
H$a Xem©B¶o&
a) AND
b) OR
c) NOR
b) i) Convert the following binary number to equivalent decimal
number. 4
{ZåZ{b{IV ~m¶Zar Zå~am| H$mo Vwë¶ S>ogr‘b Zå~am| ‘| ~X{b¶o&
a) 101101 b) 110111
ii) Convert the following decimal number to equivalent binary
numbers. 4
{ZåZ{b{IV S>ogr‘b A§H$m| H$mo Vwë¶ ~m¶Zar A§H$m| ‘| ~X{b¶o&
a) 125 b) 175
3. a) Compare 0 to 10 decimal numbers with equivalent binary number,
octal number and BCD codes. 8
0 go 10 VH$ Ho$ S>ogr‘b A§H$m| H$s VwbZm Vwë¶ ~m¶Zar A§H$m|, Am°³Q>b
A§H$m| Am¡a BCD H$moS²>g go H$s{OE&
b) Find the minimal expression for the switching function given below
using Karnaugh map. 10
H$mZm} ‘¡n H$m Cn¶moJ H$a ZrMo {X¶o J¶o pñdqMJ ’§$³eZ Ho$ {b¶o g§{já
g‘rH$aU kmV H$s{OE&
∑ ( A, B, C, D ) = ( 0,1, 4,5, 6, 7,12,14 )

4. a) Design 4:1 multiplexer and explain its working. 9

4:1 ‘ëQ>rßbo³ga ~ZmB¶o Am¡a BgH$s H$m¶©àUmbr g‘PmB¶o&
b) Design a logic circuit of full adder using two half adder and explain
it. 9
Xmo hm°’$ ES>a H$m Cn¶moJ H$aHo$ EH$ ’w$b ES>a H$m bm°{OH$ g{H©$Q> ~ZmB¶o
Am¡a Bgo g‘PmB¶o&
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5. a) Define latch and its types. 4

b¡M Am¡a BgHo$ àH$mam| H$mo n[a^m{fV H$s{OE&
b) Explain D-flip-flop with its, logic symbol, logic diagram and truth
table. 6
D-pâbn-âbm°n H$mo bm°{OH$ g§Ho$V, bm°{OH$ S>m¶J«m‘ Ed§ Q®>W Q>o~b
~ZmH$a g‘PmB¶o&
c) Explain successive approximation type ADC with diagram. 8
g³g¡{gd Eàmo³gr‘oeZ Q>mBn EZmbm°J Qy> {S>{OQ>b H$ÝdQ>©a H$s H$m¶©àUmbr
{MÌ g{hV g‘PmB¶o&
6. a) Explain working of 4-bit shift register with timing diagram and
truth table. 10
4-{~Q> {eâQ> a{OñQ>a H$s H$m¶©{d{Y Q>mBq‘J S>m¶J«m‘ Ed§ Q¯>W Q>o~b
~ZmH$a g‘PmB¶o&
b) Compare synchronous counter with asynchronous counter. 8
qgH«$moZg H$mC§Q>a H$s VwbZm AqgH«$moZg H$mC§Q>a Ho$ gmW H$s{OE&
7. a) Explain 3-bit synchronous up/down counter with circuit diagram
and timing diagram. 9
An/S>mCZ àmê$nr qgH«$moZg H$mC§Q>a H$s H$m¶©{d{Y n[anW {MÌ Ed§
Q>mBq‘J S>m¶J«m‘ ~ZmH$a g‘PmB¶o&
b) Explain TTL logic family with diagram and its characteristics. 9
TTL bm°{OH$ ’¡${‘br H$mo {MÌ Ed§ {deofVmAm| g{hV g‘PmB¶o&

8. a) Describe various primary and secondary memories. 10

{d{^Þ àm¶‘ar Ed§ {ÛVr¶H$ ‘o‘moarO H$m dU©Z H$s{OE&
b) Write short notes on PAL and PLD. 8
PAL Am¡a PLD na g§{já {Q>ßnUr {b{IE&

9. a) Differentiate between dynamic RAM and static RAM. 8

J{VH$ RAM Am¡a pñWa RAM Ho$ ‘ܶ A§Va ñnï> H$s{OE&
b) Explain working of 1 to 8 demultiplexer with diagram. 10
ñdÀN> {MÌ H$s ghm¶Vm go 1 go 8 {S>‘ëQ>rßbo³ga H$s H$m¶©{d{Y g‘PmB¶o&
Y
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