JAYA ENGINEERING COLLEGE

Thiruninravur-602024
Question Bank
Department : CSE-B Subject Code : CS3351
Year/ Sem : II/ 03 Subject :Digital Principles and Computer Organization
Regulation : 2021 Staff Incharge : MrS.E.SUJATHA, AP/ECE

UNIT I COMBINATIONAL LOGIC 9

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary
Adder – Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder –
Multiplexers – Demultiplexers.
PART-A (3 MARKS)
1. Find the Octal equivalent of the hexadecimal number DCBA .
2. What is meant by multilevel gates networks?
3. Discuss the NOR operation with a truth table.
4. Write short notes on weighted binary codes.
5. Convert (126)10 to Octal number and binary number.
6. Prove the following using Demorgan’ theorem [(X+Y)’+(X+Y)’]’= X+Y
7. Convert (0.6875)10 to binary.
8. Implement AND gate using only NOR gate
9. State the principle of duality
10. State and prove the consensus theorem.
11. Find the octal equivalent of hexadecimal numbers AB.CD.
12. Realize XOR gate using only 4 NAND gates.
13. Realize JK flip flop using D flip flop.
14. Convert the following hexadecimal numbers into decimal numbers: a)263 b)1C3
15. What is the significance of BCD code.
16. Simplify the expression: X = (A’+B)(A+B+D)D’.
17. (a) Convert (11001010)2 into gray code. (b) Convert a Gray code 11101101 into binary code.
18. State & prove De-Morgan’s theorem.
19. Describe the canonical forms of the Boolean function.
20. Describe the importance of don’t care conditions.
21. What is a prime implicant?
22. Define the following: minterm and maxterm?
23. Minimize the function using K-map: F=∑m(1,2,3,5,6,7).
24. Define Karnaugh map.
25. Plot the expression on K-map: F (w,x,y) =∑m (0, 1, 3, 5, 6) + d (2, 4).
26. Express x + yz as the sum of minterms
27. Simplify: a) Y = AB’D + AB’D’ b) Z = (A’+B)(A+B).
28. What are Universal Gates? Why are they called so?
29. Implement OR using NAND only.
30. Implement NOR using NAND only.
PART B (13 MARKS)
1.Reduce the expression using Quine McCluskey's method F(x1, x2, x3, x4, x5) = ∑m (0, 2, 4, 5,
6, 7, 8, 10, 14, 17, 18, 21, 29, 31) + ∑d (11, 20, 22)
2. Simplify the following switching functions using Quine McCluskey's tabulation method and
realize expression using gates F(A,B,C,D) = Σ(0,5,7,8,9,10, 11, 14,15).
3. Simplify the following switching functions using Karnaugh map method and realize
expression using gates F(A,B,C,D) = Σ(0,3,5,7,8,9,10,12,15).
4. (a) Express the following function in sum of min-terms and product of max-terms
F(X,Y,Z)=X+YZ
(b) convert the following logic system into NAND gates only.
5. Simply the following Boolean expression in (i) sum of product (ii) product of sum using k-
map AC’+B’D+A’CD+ABCD
6. Simplify the Boolean function in SOP and POS F(A,B,C,D)=∑m(0,1,2,5,8,9,10)
7. (ii) plot the following Boolean function in k-map and simplify it.
F(w,x,y,z) = ∑m(0,1,2,4,5,6,8,9,12,13,14).
8. Simply the function F(w,x,y,z)= ∑m(2,3,12,13,14,15) using tabulation method .Implement the
simplified using gates.
9. Minimize the expression using quineMccluskey(tabulation) F=∑m(0,1,9,15,24,29,30)
+∑d(8,11,31). Method.
10. Simplify the following functions using K-map technique.
G=∑m (0,1,3,7,9,11) (ii) f(w,x;y,z)=∑m(0,7,8,9,10,12)+∑d(2,5,13).
11. Simplify the given boolean function in POS form using K-map and draw the logic diagram
using Only NOR gates F(A,B,C,D)= ∑m (0,1,4,7,8,10,12,15)+d(2,6,11,14).
12. ii)Convert 78.510 into binary.
ii)Find the dual and complement of the following Boolean expression Xyz’+x’yz+z(xy+w).
13. Simplify the Boolean function using QuineMcCluskey method:
F (A, B, C, D,E) = ∑m (0,1,3,7,13,14,21,26,28) + ∑d(2,5,9,11,17,24)
14. Reduce the following function using K-map technique.
i) f (A, B, C) = ∑m (0,1,3,7) + ∑d (2,5)
ii) F (w,x,y,z) = ∑m (0,7,8,9,10,12) + ∑d (2,5,13)
15. Simplify the following Boolean function F using Tabulation method.
i) F (A, B, C, D) = ∑m (0,6,8,13,14) ,d (A, B, C, D)= ∑m (2,4,10)
ii) F (A, B, C, D) = ∑m (1,3,5,7,9,15) ,d (A, B, C, D)= ∑m (4,6,12,13)
UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9
Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables,
Triggering of FF, Analysis and design of clocked sequential circuits – Design –
Moore/Mealy models, state minimization, state assignment, circuit implementation -
Registers – Counters.
PART-A (3 MARKS)
1. Design the combinational circuit with 3 inputs and 1 output. The output is 1 when the
binary value of the input is less than 3. The output is 0 otherwise.
2. Define Combinational circuits.
3. Draw the truth table of half adder.
4. Write the Data flow description of a 4-bit Comparator.
5. Implement a 4 bit even parity generator.
6. Implement a 4 bit even parity checker.
7. Write the data flow description of a 4-bit comparator.
8. Implement a full adder with 4×1 multiplexer.
9. Implement the following Boolean function using 8:1 multiplexer F(A,B,C)= ∑m(1,3,5,6)
10. Draw a 2 to 1 multiplexer circuit.
11. What is priority encoder?
12. Draw the truth table and circuit diagram of 4 to 2 encoder.
13. Obtain the truth table for BCD to Excess-3 code converter.
14. Write the stimulus for 2 to 1 line MUX.
15. Distinguish between a decoder and a demultiplexer.
16. Design a 2-bit binary to gray code converter.
17. Draw the 4 bit Gray to Binary code converter.
18. Draw the 4 bit Binary to Gray code converter.
19. Distinguish between combinational logic and sequential logic.
20. Implement half Adder using NAND Gates.
21. Design a half subtractor.
22. Give the truth table for half adder and write the expression for sum and carry.
23. Mention the different type of binary codes.
24. What is meant by self-complementing code?
25. Draw the logic diagram of a one to four line de-multiplexer.
26. List the advantages and disadvantages of BCD code
27. Implement a full adder with two half adder.
28. Define Tristate gates.
29. Define logic synthesis and simulation.
PART B (13 MARKS)
1. Implement the following Boolean function with 4 X 1 multiplexer and external gates.
Connect inputs A and B to the selection lines. The input requiremnts for the four data
lines will be a function of variables C and D these values are obatined by expressing
F as a function of C and D for each four cases when AB = 00, 01, 10 and 11. These
functions may have to be implemented with external gates. F(A, B, C, D) = Σ (1, 2, 5,
7, 8, 10, 11, 13, 15).
2. Design a full adder with x, y, z and two outputs S and C. The circuits performs
x+y+z, z is the input carry, C is the output carry and S is the Sum.

3. Design a code converter thet converts a 8421 to BCD code.

4. (i) Explain the Analysis procedure. Analyze the following logic diagram.
(ii) With neat diagram explain the 4-bit adder with carry lookahead.
 5. (a) Design 2-bit magnitude comparator and write a verilog HDL code.
(b)Implement the following Boolean functions with a multiplexer:
F(w,x,y,z)= ∑(2,3,5,6,11,14,15)
(c) Construct a 5 to 32 line decoder using 3 to 8 line decoders and 2 to 4 line decoder.
6. Design and implement a 8241 to gray code converter. Realize the converter using only
NAND gates .
7. Design a circuit that converts 8421 BCD code to Excess-3
8. (i).Realize 4 x 16 decoder using two 3 x 8 decoders with enable input.
(ii) Implement the following functions using a multiplexer.
F(W,X,Y,Z)= ∑m (0,1,3,4,8,9,15).
10 .(i).Design a combinational circuit to perform BCD addition.
(ii).Design a 4-bit magnitude comparator with three outputs :A<B ,A=B ,A>B.
11. Construct a 4 to 16 line decoder with an enable input using five 2 to 4 line decoders
with
enable inputs.
12. Design a BCD to 7 segment decoder and implement it by using basic gates.
13. Discuss the need and working principle of Carry Look ahead adder.
14. Design a full adder using 2 half adders.
15. Design a logic circuit that accepts a 4 bit Gray code and converts it into 4 bit binary
code.
UNIT III COMPUTER FUNDAMENTALS 9
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and
Operands of Computer Hardware Instruction – Instruction Set Architecture (ISA):
Memory Location, Address and Operation – Instruction and Instruction Sequencing –
Addressing Modes, Encoding of Machine Instruction – Interaction between Assembly and
High Level Language.
PART-A (3 MARKS)
1. Write the basic functional units of computer?
The basic functional units of a computer are input unit, output unit, memory unit, ALU unit
and control unit
2. Write the basic functional units of computer?
The basic functional units of a computer are input unit, output unit, memory unit, ALU unit
and control unit.

3. What is a bus? What are the different buses in a CPU?

A group of lines that serve as a connecting path for several devices is called bus .The
different buses in a CPU are 1] Data bus 2] Address bus 3] Control bus.
4. What is meant by stored program concepts?
Stored program concept is an idea of storing the program and data in the memory
5. Define multiprogramming?
Multiprogramming is a technique in several jobs are in main memory at once and the
processor is switched from job as needed to keep several jobs advancing while keeping the
peripheral devices in use.

6. What is meant by VLSI technology?

VLSI is the abbreviation for Very Large Scale Integration. In this technology millions of
transistors are put inside a single chip as tiny components. The VLSI chips do the function of
millions of transistors. These are Used to implement parallel algorithms directly in hardware

7. Define multiprocessing?
Multiprocessing is the ability of an operating system to support more than one process at the
same time
8. List the eight great ideas invented by computer architecture? APR/MAY-2015
• Design for Moore’s Law
• Use abstraction to simplify design
• Make the common case fast
• Performance via Parallelism
• Performance via Pipelining
• Performance via Prediction
• Hierarchy of Memory
• Dependability via Redundancy
9. Define power wall.
• Old conventional wisdom
• Power is free
• Transistors are expensive
• New conventional wisdom: “Power wall”
• Power expensive
• Transistors“free” (Can put more on chip than can afford to turn on)

10. What are clock and clock cycles?

The timing signals that control the processor circuits are called as clocks. The clock defines
regular time intervals called clock cycles.

11. What is uniprocessor?

A uniprocessor system is defined as a computer system that has a single central processing
unit that is used to execute computer tasks. As more and more modern software is able to
make use of multiprocessing architectures, such as SMP and MPP, the term uniprocessor is
therefore used to distinguish the class of computers where all processing tasks share a single
CPU.

12. What is multicore processor?

A multi-core processor is a single computing component with two or more independent
actual central processing units (called "cores"), which are the units that read and execute
program instructions.The instructions are ordinary CPU instructions such as add, move data,
and branch, but the multiple cores can run multiple instructions at the same time, increasing
overall speed for programs amenable to parallel computing

13. Differentiate super computer and mainframe computer.

A computer with high computational speed, very large memory and parallel structured
hardware is known as a super computer.EX: CDC 6600. Mainframe computer is the large
computer system containing thousands of IC’s. It is a room- sized machine placed in special
computer centers and not directly accessible to average users. It serves as a central
computing facility for an organization such as university, factory or bank.

14. Differentiate between minicomputer and microcomputer.

Minicomputers are small and low cost computers are characterized by Short word size i.e.
CPU word sizes of 8 or 16 bits. They have limited hardware and software facilities. They are
physically smaller in size.Microcomputer is a smaller, slower and cheaper computer packing
all the electronics of the computer in to a handful of IC’s, including CPU and memory and IO
chips
15. What is instruction register?
The instruction register (IR) holds the instruction that is currently being executed. Its output
is available to the control circuits which generate the timing signals that control the various
processing elements involved in executing the instruction.

16. What is program counter?

The program counter (PC) keeps track of the execution of a program. It contains the memory
address of the next instruction to be fetched and executed.

17.What is processor time?

The sum of the periods during which the processor is active is called the processor time
Give the CPU performance equation.
CPU execution time for a program =Instruction Count XClock cycles per instructionXClock
cycle time.

18. What is superscalar execution?

In this type of execution, multiple functional units are used to create parallel paths through
which different instructions can be executed in parallel. So it is possible to start the execution
of several instructions in every clock cycle. This mode of operation is called superscalar
execution

19. What is RISC and CISC?

The processors with simple instructions are called as Reduced Instruction Set Computers
(RISC). The processors with more complex instructions are called as Complex Instruction
Set Computers (CISC).

20. List out the methods used to improve system performance.

The methods used to improve system performance are
• Processor clock
• Basic Performance Equation
• Pipelining
• Clock rate
• Instruction set
• Compiler
21. Define addressing modes and its various types.(nov/dec 2017)
The different ways in which the location of a operand is specified in an instruction is referred
to as addressing modes. The various types are Immediate Addressing, Register Addressing,
Based or Displacement Addressing, PC-Relative Addressing, Pseudodirect Addressing.

22. Define register mode addressing.

In register mode addressing, the name of the register is used to specify the operand.

23. Define Based or Displacement mode addressing.

In based or displacement mode addressing, the operand is in a memory location whose
address is the sum of a register and a constant in the instruction.

24. State Amdahl’s Law.

Amdahl’s law is a formula used to find the maximum improvement improvement possible by
improving a particular part of a system. In parallel computing, Amdahl's law is mainly used
to predict the theoretical maximum speedup for program processing using multiple
processors.

25. Define Relative mode addressing.

 In PC-relative mode addressing, the branch address is the sum of the PC and a constant in the
instruction. - In the relative address mode, the effective address is determined by the index
mode by using the program counter in stead of general purpose processor register. This mode
is called relative address mode.

25. Distinguish pipelining from parallelism

parallelism means we are using more hardware for the executing the desired task. in parallel
computing more than one processors are running in parallel. there may be some dedicated
hardware running in parallel for doing the specific task.
while the pipelining is an implementation technique in which multiple instructions are
overlapped ninexecution.parallelism increases the performance but the area also increases.
in case of pipelining the performance and througput increases at the cost of pipelining
registers area pipelining there are different hazards like data hazards, control hazards etc.

26. Distinguish pipelining from parallelism

parallelism means we are using more hardware for the executing the desired task. in parallel
computing more than one processors are running in parallel. there may be some dedicated
hardware running in parallel for doing the specific task.
while the pipelining is an implementation technique in which multiple instructions are
overlapped ninexecution. parallelism increases the performance but the area also increases.
in case of pipelining the performance and througput increases at the cost of pipelining
registers area pipelining there are different hazards like data hazards, control hazards etc.

27. How to represent Instruction in a computer system?

Computer instructions are the basic components of a machine language program. They are
also known as macrooperations, since each one is comprised of a sequences of
microoperations. Each instruction initiates a sequence of microoperations that fetch operands
from registers or memory, possibly perform arithmetic, logic, or shift operations, and store
results in registers or memory. Instructions are encoded as binary instruction codes. Each
instruction code contains of aoperation code, or opcode, which designates the overall purpose
of the instruction (e.g. add, subtract, move, input, etc.). The number of bits allocated for the
 opcode determined how many different instructions the architecture supports. In addition to
the opcode, many instructions also contain one or more operands, which indicate where in
registers or memory the data required for the operation is located. For example, add
instruction requires two operands, and a not instruction requires one.

28. Brief about relative addressing mode.

Relative addressing mode - In the relative address mode, the effective address is determined
by the index mode by using the program counter in stead of general purpose processor
register. This mode is called relative address mode.

29. Distinguish between auto increment and auto decrement addressing mode?

30. State indirect addressing mode give example.

Indirect Mode. The effective address of the operand is the contents of a register or main
memory location, location whose address appears in the instruction. ... Once it's there, instead
of finding an operand, it finds an address where the operand is located.
LOAD R1, @R2 Load the content of the memory address stored atregister R2 to
register R1.

PART-B (13 MARKS)

1. i)Discuss in detail about Eight great ideas of computer Architecture.(6)
ii) Explain in detail about Technologies for Building Processors and Memory (7)
2. Explain the various components of computer System with neat diagram
3. Discuss in detail the various measures of performance of a computer
4. Define Addressing mode and explain the different types of basic addressing modes with
an example
5. i)Discuss the Logical operations and control operations of computer (7)
ii)Write short notes on Power wall(6)
6. Consider three different processors P1, P2, and P3 executing the same instruction set. P1
has 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a
4.0 GHz clock rate and has a CPI of 2.2.
 7. a. Which processor has the highest performance expressed in instructions per second?
b. If the processors each execute a program in 10 seconds, find the number of cycles and
the number of instructions.
c. We are trying to reduce the execution time by 30% but this leads to an increase of 20%
in the CPI. What clock rate should we have to get this time reduction?
8. Explain various instruction format illustrate the same with an example.
9. Explain direct ,immediate ,relative and indexed addressing modes with example.
10. State the CPU performance equation and the factors that affect performance
11. Discuss about the various techniques to represent instructions in a computer system.
12. What is the need for addressing in a computer system? Explain the different addressing
modes with suitable examples.
13. Explain types of operations and operands with examples.
14. Consider two different implementations of the same instruction set architecture. The
instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1
with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and
CPIs of 2, 2, 2, and 2.
15. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes
as follows: 10% class A, 20% class B, 50% class C, and 20% class D, which implementation is
faster?
a. What is the global CPI for each implementation?
b. Find the clock cycles required in both cases.
16. To what should the CPI of load/store instructions be reduced in order for a single processor
to match the performance of four processors using the original CPI values?
17. Describe the steps that transform a program written in a high-level language such as C into a
representation that is directly executed by a computer processor.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired
Control, Microprogrammed Control – Pipelining – Data Hazard – Control Hazards –
Exceptions.
 PART-A
1. What is pipelining?
The technique of overlapping the execution of successive instruction for substantial
improvement in performance is called pipelining.
2. What is and precise exception?
A precise exception is one in which all instructions prior to the faulting instruction are
complete and instruction following the faulting instruction, including the faulty
instruction; do not change the state of the machine.
3. Define processor cycle in pipelining.

The time required between moving an instruction one step down the pipeline is a
processor cycle.
4. What is meant by pipeline bubble?

To resolve the hazard the pipeline is stall for 1 clock cycle. A stall is commonly called a
pipeline bubble, since it floats through the pipeline taking space but carrying no useful work.
5. What is pipeline register delay?
Adding registers between pipeline stages me adding logic between stages and setup and
hold times
for proper operations. This delay is known as pipeline register delay.
6. What are the major characteristics of a pipeline?

The major characteristics of a pipeline are:

1. Pipelining cannot be implemented on a single task, as it works by splitting multiple
tasks into a number of subtasks and operating on them simultaneously.

2. The speedup or efficiency achieved by suing a pipeline depends on the number of pipe
stages and the number of available tasks that can be subdivided
7. What is data path?
As instruction execution progress data are transferred from one instruction to another, often
passing through the ALU to perform some arithmetic or logical operations. The registers, ALU,
and the interconnecting bus are collectively referred as the data path.
8. What is a pipeline hazard and what are its types?
Any condition that causes the pipeline to stall is called hazard. They are also called as stalls or
bubbles. The various pipeline hazards are:
Hazard Control Hazard
9. What is Instruction or control hazard?
The pipeline may be stalled because of a delay in the availability of an instruction. For example,
this may be a result of a miss in the cache, requiring the instruction to be fetched from the main
memory. Such hazards are often called control hazards or instruction hazard.
10. Define structural hazards.

This is the situation when two instruction require the use of a given hardware resource at the
same time. The most common case in which this hazard may arise is in access to memory
11. What is side effect?
When a location other than one explicitly named in an instruction as a destination operand is
affected, the instruction is said to have a side effect
12. What do you mean by branch penalty?
The time lost as a result of a branch instruction is often referred to as branch penalty
13. What is branch folding?
When the instruction fetch unit executes the branch instruction concurrently with the execution
of the other instruction, then this technique is called branch folding.
14. What do you mean by delayed branching?
Delayed branching is used to minimize the penalty incurred as a result of conditional branch
instruction. The location following the branch instruction is called delay slot. The instructions in
the delay slots are always fetched and they are arranged such that they are fully executed whether
or not branch is taken. That is branching takes place one instruction later than where the branch
instruction appears in the instruction sequence in the memory hence the name delayed branching
15. Define exception and interrupt.
Exception:
The term exception is used to refer to any event that causes an interruption.
Interrupt:
An exception that comes from outside of the processor. There are two types of interrupt.
1. Imprecise interrupt and 2.Precise interrupt
16. Why is branch prediction algorithm needed? Differentiate between the static and dynamic
techniques.
The branch instruction will introduce branch penalty which would reduce the gain in
performance expected from pipelining. Branch instructions can be handled in several ways to
reduce their negative impact on the rate of execution of instructions. Thus the branch prediction
algorithm is needed.
Static Branch prediction
The static branch prediction, assumes that the branch will not take place and to continue to fetch
instructions in sequential address order.
Dynamic Branch prediction
The idea is that the processor hardware assesses the likelihood of a given branch being taken by
keeping track of branch decisions every time that instruction is executed. The execution history
used in predicting the outcome of a given branch instruction is the result of the most recent
execution of that instruction.
17. What is branch Target Address?
The address specified in a branch, which becomes the new program counter, if the branch is
taken. In MIPS the branch target address is given by the sum of the offset field of the instruction
and the address of the instruction following the branch
18. How do control instructions like branch, cause problems in a pipelined processor?
Pipelined processor gives the best throughput for sequenced line instruction. In branch
instruction, as it has to calculate the target address, whether the instruction jump from one
memory location to other. In the meantime, before calculating the larger, the next sequence
instructions are got into the pipelines, which are rolled back, when target is calculated.
19. What is meant by super scalar processor?
Super scalar processors are designed to exploit more instruction level parallelism in user
programs. This means that multiple functional units are used. With such an arrangement it is
possible to start the execution of several instructions in every clock cycle. This mode of
operation is called super scalar execution.
20. Define pipeline speedup. [ APR/MAY 2012] (A.U.NOV/DEC 2012)
Speed up is the ratio of the average instruction time without pipelining to the average instruction
time with pipelining. Average instruction time without pipelining Speedup= Average instruction
time with pipelining
21. What is Vectorizer?
The process to replace a block of sequential code by vector instructions is called vectorization.
The system software, which generates parallelism, is called as vectorizing compiler.
22. What is pipelined computer?
When hardware is divided in to a number of sub units so as to perform the sub operations in an
overlapped fashion is called as a pipelined computer.
23. List the various pipelined processors.
8086, 8088, 80286, 80386. STAR 100, CRAY 1 and CYBER 205 etc
24. Classify the pipeline computers.
Based on level of processing → processor pipeline, instruction pipeline, arithmetic pipelines
Based on number of functions→ Uni-functional and multi functional pipelines.
Based on the configuration → Static and Dynamic pipelines and linear and non linear pipelines
Based on type of input→ Scalar and vector pipelines.Asf
25. Define Pipeline speedup.
The ideal speedup from a pipeline is equal to the number of stages in the pipeline.
26. Write down the expression for speedup factor in a pipelined architecture.
The speedup for a pipeline computer is S = (k + n -1) tp
Where,K → number of segments in a pipeline,N → number of instructions to be executed. Tp →
cycle time
27. What are the problems faced in instruction pipeline.
Resource conflicts → Caused by access to the memory by two at the same time. Most of the
conflicts can be resolved by using separate instruction and data memories.
Data dependency → Arises when an instruction depends on the results of the previous instruction
but this result is not yet available.
Branch difficulties → Arises from branch and other instruction that change the value of PC
(Program Counter).
28. What is meant by vectored interrupt?
An interrupt for which the address to which control is transferred is determined by the cause of
the exception.
29. What is the need for speculation?
One of the most important methods for finding and exploiting more ILP is speculation. It is an
approach whereby the compiler or processor guesses the outcome of an instruction to remove it
as dependence in executing other instructions. For example, we might speculate on the outcome
of a branch, so that instructions after the branch could be executed earlier.
Speculation (also known as speculative loading ), is a process implemented in Explicitly Parallel
Instruction Computing ( EPIC ) processors and their compiler s to reduce processor-memory
exchanging bottlenecks or latency by putting all the data into memory in advance of an actual
load instruction
30. Define Imprecise , Precise interrupt
Imprecise interrupt
Also called imprecise exception. Interrupts or exceptions in pipelined computers that are
not associated with the exact instruction that was the cause of the interrupt or exception.
Precise interrupt
Also called precise exception. An interrupt or exception that is always associated with the
correct instruction in pipelined computers
31. What are the advantages of pipelining?
The cycle time of the processor is reduced; increasing the instruction throughput.Some
combinational circuits such as adders or multipliers can be made faster by adding more circuitry.
If pipelining is used instead, it can save circuitry vs. a more complex combinational circuit.
32. What is Program counter (PC)(Fetching)
The register containing the address of the instruction in the program being executed

33. What is Adder:

An adder is needed to compute the next instruction address. The adder is an ALU wired
to always add its two 32-bit inputs and place the sum on its output.
 34. What is Register file(decoding):
A state element that consists of a set of registers that can be read and written by
supplying a register number to be accessed.

35. Define Sign-extend in data path.

To increase the size of a data item by replicating the high-order sign bit of the original
data item in the high-order bits of the larger, destination data item. a unit to sign-extend the 16-
bit offset field in the instruction to a 32-bit signed value
36. Define Shifter:
■ The jump instruction operates by replacing the lower 28 bits of the PC with the lower 26 bits
of the instruction shifted left by 2 bits. Simply concatenating 00 to the jump offset accomplishes
this shift
37. What is Delayed branch?
A type of branch where the instruction immediately following the branch is always executed,
independent of whether the branch condition is true or false.
38.What are the control lines of MIPS functions.
ALU control lines Function
0000 AND
0001 OR
0010 add
0110 sub
0111 Set lessthan
1100 NOR
39. Define Don’t-care term
An element of a logical function in which the output does not depend on the values of all
the inputs
40. What are the Function of seven control lines?
41.What are the Disadvantages of single cycle implementation?
• Although the single-cycle design will work correctly, it would not be used in modern
designs because it is inefficient.
• Although the CPI is 1 the overall performance of a single-cycle implementation is likely
to be poor, since the clock cycle is too long.
• The penalty for using the single-cycle design with a fixed clock cycle is significant,.
• To implement the floating-point unit or an instruction set with more complex
instructions, this single-cycle design wouldn’t work well .
• A single-cycle implementation thus violates the great idea of making the common case
fast.
42. What is Structural hazard?
When a planned instruction cannot execute in the proper clock cycle because the
hardware does not support the combination of instructions that are set to execute.
If there is a single memory instead of two memories. If the pipeline had a fourth
instruction, that in the same clock cycle the first instruction is accessing data from memory
while the fourth instruction is fetching an instruction from that same memory. Without two
memories, pipeline could have a structural hazard.
To avoid structural hazards
• When designing a pipeline designer can change the design
By providing sufficient resources
43.Define Data Hazards.
Data hazard is also called a pipeline data hazard. When a planned instruction cannot
execute in the proper clock cycle because data that is needed to execute the instruction is not yet
available.
• In a computer pipeline, data hazards arise from the dependence of one instruction on an
earlier one that is still in the pipeline
• Example:
add instruction followed immediately by a subtract instruction that uses the sum ($s0):
add$s0, $t0, $t1
sub$t2, $s0, $t3
44. Define data Forwarding
Forwarding is also called as bypassing. A method of resolving a data hazard by retrieving
the missing data element from internal buffers rather than waiting for it to arrive from
programmer-visible registers or memory.
45. Define load-use data hazard
A specific form of data hazard in which the data being loaded by a load instruction has
not yet become available when it is needed by another instruction
46. Define Pipeline stall
Pipeline stall is also called as bubble. A stall initiated in order to resolve a hazard.

47. What is Control Hazard?

Control hazard is also called as branch hazard. When the proper instruction cannot
execute in the proper pipeline clock cycle because the instruction that was fetched is not the one
that is needed; that is, the flow of instruction addresses is not what the pipeline expected.
48. What are the Schemes for resolving control hazards ?
1. Assume Branch Not Taken:
2. Reducing the Delay of Branches:
3. Dynamic Branch Prediction:
49. Define Branch delay slot
 The slot directly after a delayed branch instruction, which in the MIPS architecture is
filled by an instruction that does not affect the branch.
50. Define Correlating , Tournament branch predictor
Correlating predictor
A branch predictor that combines local behavior of a particular branch and global
information about the behavior of some recent number of executed branches.
Tournament branch predictor
A branch predictor with multiple predictions for each branch and a selection mechanism
that chooses which predictor to enable for a given branch
51. Name control signal to perform arithmetic operation.
1.Regdst
2.Regwrite
3.ALU Src
52. what is ideal cycle per instruction in pipelining?
With pipelining, a new instruction is fetched every clock cycle by exploiting instruction-level
parallelism, therefore, since one could theoretically have five instructions in the five pipeline
stages at once (one instruction per stage), a different instruction would complete stage 5 in every
clock cycle
PART-B (13 MARKS)
1. Explain the basic MIPS implementation with binary multiplexers and control lines
2. What is hazards ?Explain the different types of pipeline hazards with suitable examples.
3. Explain how the instruction pipeline works. What are the various situations where an
instruction pipeline can stall? Illustration with an example?
4. Explain data path in detail
5. Explain dynamic branch prediction.
6. Explain in detail How exceptions are handled in MIPS architecture.
7. Explain in detail about building a data path.
8. Explain in detail about control implementation scheme
9. What is pipelining? Discuss about pipelined data path and control
10. Why is branch prediction algorithm needed? Differentiate between static and dynamic
techniques?
 11. Design a simple path with control implementation and explain in detail.
12. Discuss the limitation in implementing the processor path. Suggest the methods to
overcome them.
13. When processor designers consider a possible improvement to the processor datapath, the
decision usually depends on the cost/performance trade-off . In the following three problems,
assume that we are starting with a datapath. where I-Mem, Add, Mux, ALU, Regs, D-Mem,
and Control blocks have
latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps, respectively,and costs
of 1000, 30, 10, 100, 200, 2000, and 500, respectively.Consider the addition of a multiplier to
the ALU. Th is addition will add 300 ps to the latency of the ALU and will add a cost of 600
to the ALU. Th e result will be 5% fewer instructions executed since we will no longer need
to emulate the MUL instruction.
1 What is the clock cycle time with and without this improvement?
2 What is the speedup achieved by adding this improvement?
3 Compare the cost/performance ratio with and without this improvement.
14. For the problems in this exercise, assume that there are no pipeline stalls and that the
breakdown of executed instructions is as follows:
add addi not beq lw sw
20% 20% 0% 25% 25% 10%
14.1 In what fraction of all cycles is the data memory used?
14.2 In what fraction of all cycles is the input of the sign-extend
circuit needed? What is this circuit doing in cycles in which its input is not needed?
15. Consider the following loop.
loop:lw r1,0(r1)
and r1,r1,r2
lw r1,0(r1)
lw r1,0(r1)
beq r1,r0,loop
Assume that perfect branch prediction is used (no stalls due to control hazards),that there are
no delay slots, and that the pipeline has full forwarding support. Also assume that many
iterations of this loop are executed before the loop exits. (Refer notes)
UNIT V MEMORY AND I/O 9
Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping
and Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel
and Serial Interface – Interrupt I/O – Interconnection Standards: USB, SATA
PART –A (3 MARKS)
1. What is principle of locality?
The principle of locality states that programs access a relatively small portion of their address
space at any instant of time
2. Define spatial locality.
The locality principle stating that if a data location is referenced, data locations with nearby
addresses will tend to be referenced soon.
3. Define Memory Hierarchy.
A structure that uses multiple levels of memory with different speeds and sizes. The faster
memories are more expensive per bit than the slower memories.
4. Define hit ratio.
When a processor refers a data item from a cache, if the referenced item is in the cache, then
such a reference is called Hit. If the referenced data is not in the cache, then it is called Miss,
Hit ratio is defined as the ratio of number of Hits to number of references.
Hit ratio =Total Number of references
5. What is TLB? What is its significance?
Translation look aside buffer is a small cache incorporated in memory management unit. It
consists of page table entries that correspond to most recently accessed pages. Significance
The TLB enables faster address computing. It contains 64 to 256 entries
6. Define temporal locality.
The principle stating that a data location is referenced then it will tend to be referenced again
soon.
7. How cache memory is used to reduce the execution time.
If active portions of the program and data are placed in a fast small memory, the average
memory access time can be reduced, thus reducing the total execution time of the program.
Such a fast small memory is called as cache memory.
8. Define memory interleaving.
 In order to carry out two or more simultaneous access to memory, the memory must be
partitioned in to separate modules. The advantage of a modular memory is that it allows the
interleaving i.e. consecutive addresses are assigned to different memory module

9. Define Hit and Miss?

The performance of cache memory is frequently measured in terms of a quantity called hit
ratio. When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
If the word is not found in cache, then it is in main memory and it counts as a miss
10. What is cache memory?
It is a fast memory that is inserted between the larger slower main memory and the processor.
It holds the currently active segments of a program and their data
11. What is memory system?
Every computer contains several types of devices to store the instructions and data required
for its operation. These storage devices plus the algorithm-implemented by hardware and/or
software-needed to manage the stored information from the memory system of computer
12. What is Read Access Time?
A basic performance measure is the average time to read a fixed amount of information, for
instance, one word, from the memory. This parameter is called the read access time
13. What is the necessary of virtual memory? State the advantages of virtual memory?
Virtual memory is an important concept related to memory management. It is used to
increase the apparent size of main memory at a very low cost. Data are addressed in a virtual
address space that can be as large as the addressing capability of CPU.
14. Virtual memory is a technique that uses main memory as a “cache” for secondary
storage. Two major motivations for virtual memory: to allow efficient and safe sharing of
memory among multiple programs, and to remove the programming burdens of a small,
limited amount of main memory
15. What are the units of an interface?
DATAIN, DATAOUT, SIN, SOUT
16. Distinguish between isolated and memory mapped I/O?
The isolated I/O method isolates memory and I/O addresses so that memory address values
are not affected by interface address assignment since each has its own address space.
In memory mapped I/O, there are no specific input or output instructions. The CPU can
manipulate I/O data residing in interface registers with the same instructions that are used to
manipulate memory words
17. Distinguish between memory mapped I/O and I/O mapped I/O. Memory mapped I/O:
When I/O devices and the memory share the same address space, the arrangement is called
memory mapped I/O. The machine instructions that can access memory is used to trfer data
to or from an I/O device.
I/O mapped I/O:
Here the I/O devices the memories have different address space. It has special I/O
instructions. The advantage of a separate I/O address space is that I/O devices deals with
fewer address lines.
18. Define virtual memory.
The data is to be stored in physical memory locations that have addresses different from
those specified by the program. The memory control circuitry translates the address specified
by the program into an address that can be used to access the physical memory
19. What is Semi Random Access?
Memory devices such as magnetic hard disks and CD-ROMs contain many rotating storage
tracks. If each track has its own read write head, the tracks can be accessed randomly, but
access within each track is serial. In such cases the access mode is semi random.
20. What is the use of DMA?
DMA (Direct Memory Access) provides I/O transfer of data directly to and from the memory
unit and the peripheral.
21. Mention the advantages of USB.
The Universal Serial Bus (USB) is an industry standard developed to provide two speed of
operation called low-speed and full-speed. They provide simple, low cost and easy to use
interconnect system.
22. What is meant by vectored interrupt?
Vectored Interrupts are type of I/O interrupts in which the device that generates the interrupt
request (also called IRQ in some text books) identifies itself directly to the processor
23. Compare Static RAM and Dynamic RAM.
Static RAM is more expensive, requires four times the amount of space for a given amount
of data than dynamic RAM, but, unlike dynamic RAM, does not need to be power-refreshed
and is therefore faster to access. Dynamic RAM uses a kind of capacitor that needs frequent
power refreshing to retain its charge. Because reading a DRAM discharges its contents, a
power refresh is required after each read. Apart from reading, just to maintain the charge that
holds its content in place, DRAM must be refreshed about every 15 microseconds. DRAM is
the least expensive kind of RAM.
SRAMs are simply integrated circuits that are memory arrays with a single access port that
can provide either a read or a write. SRAMs have a fixed access time to any datum.
SRAMs don’t need to refresh and so the access time is very close to the cycle time. SRAMs
typically use six to eight transistors per bit to prevent the information from being disturbed
when read. SRAM needs only minimal power to retain the charge in standby mode.
In a dynamic RAM (DRAM), the value kept in a cell is stored as a charge in a capacitor.
A single transistor is then used to access this stored charge, either to read the value or to
overwrite the charge stored there. Because DRAMs use only a single transistor per bit of
storage, they are much denser and cheaper per bit than SRAM
DRAMs store the charge on a capacitor, it cannot be kept indefinitely and must periodically
be refreshed.

24. what is DMA ?

Direct memory access (DMA) is a method that allows an input/output (I/O) device to
send or receive data directly to or from the main memory, bypassing the CPU to speed up
memory operations. The process is managed by a chip known as a DMA controller (DMAC).
25. Differentiate programmed I/O and interrupt i/O.
programmed I/O interrupt i/O
Programmed IO is the process of IO instruction written in computer program Interrupt
Initiated IO is done by using interrupt and some special command.
In Programmed IO technique to transfer data,required constant motoring on peripheral by
CPU,once data transfer is initiated, CPU have to wait for next transfer. In Interrupt Initiated
IO once data transfer initiated ,CPU execute next program without wasting time and the
interface keep monitoring the device.
26. what is the purpose of dirty /modified bit in cache memory.
A dirty bit or modified bit is a bit that is associated with a block of computer memory and
indicates whether or not the corresponding block of memory has been modified.[1] The dirty
bit is set when the processor writes to (modifies) this memory. The bit indicates that its
associated block of memory has been modified and has not yet been saved to storage.
27. What is the need to implement memory as a hierarchy?
28. Point out how DMA can improve I/O speed?
CPU speeds continue to increase, and new CPUs have multiple processing elements on the
same chip.A large amount of data can be processed very quickly Problem in the transfer of
data to CPU or even memory in a reasonable amount of time so that CPU has some work to
do at all time . Without DMA, when the CPU is using programmed input/output, it is
typically fully occupied for the entire duration of the read or write operation, and is thus
unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it
does other operations while the transfer is in progress, and it finally receives an interrupt
from the DMA controller when the operation is done.
29. What are the various memory Technologies?
Memory Technologies
Main memory is implemented from DRAM (dynamic random access memory), while levels
closer to the processor (caches) use SRAM (static random access memory). DRAM is less
costly per bit than SRAM, although it is substantially slower. The price difference arises
because DRAM uses significantly less area per bit of memory, and DRAMs thus have larger
capacity for the same amount of silicon;
Memory technology Typical access time $ per GiB in 2012
SRAM semiconductor memory 0.5–2.5 ns $500–$1000
DRAM semiconductor memory 50–70 ns $10–$20
Flash semiconductor memory 5,000–50,000 ns $0.75–$1.00
Magnetic disk 5,000,000–20,000,000 ns $0.05–$0
30. What is flash memory?
Flash memory is a type of electrically erasable programmable read-only memory
(EEPROM). Unlike disks and DRAM, EEPROM technologies can wear out flash memory
bits. To cope with such limits, most flash products include a controller to spread the writes by
remapping blocks that have been written many times to less trodden blocks. This technique is
called wear leveling.
In many computers the cache block size is in the range 32 to 128 bytes. What would be the
main Advantages and disadvantages of making the size of the cache blocks larger or smaller?
Larger the size of the cache fewer be the cache misses if most of the data in the block are
actually used. It will be wasteful if much of the data are not used before the cache block is
moved from cache. Smaller size means more misses
31.Define USB.
Universal Serial Bus, an external busstandard that supports data transfer ratesof 12 Mbps. A
single USB portcan be used to connect up to 127 peripheral devices, such as mice, modems,
and keyboards. USB also supportsPlug-and-Play installationandhot plugging.
31. Define Memory latency
The amount of time it takes to transfer a word of data to or from the memory.
32. Define Memory bandwidth
Tthe number of bits or bytes that can be transferred in one second. It is used to measure how
much time is needed to transfer an entire block of data.
33. Define miss Rate.
The miss rate (1−hit rate) is the fraction of memory accesses not found in the upper level.
34. Define Hit rate.
Hit rate The fraction of memory accesses found in a level of the memory hierarchy. •
35. Define miss rate.
Miss rate The fraction of memory accesses not found in a level of the memory hierarchy.
36. Define Hit time.
Hit time is the time to access the upper level of the memory hierarchy, which includes the
time needed to determine whether the access is a hit or a miss
37. Define miss penalty
The miss penalty is the time to replace a block in the upper level with the corresponding
block from the lower level, plus the time to deliver this block to the processor
38. Define tag in TLB
A field in a table used for a memory hierarchy that contains the address information required
to identify whether the associated block in the hierarchy corresponds to a requested word.
39. What are the steps to be taken on an instruction cache miss:
1. Send the original PC value (current PC – 4) to the memory.
2. Instruct main memory to perform a read and wait for the memory to complete its access.
3. Write the cache entry, putting the data from memory in the data portion of the entry,
writing the upper bits of the address (from the ALU) into the tag field, and turning the valid
bit on.
4. Restart the instruction execution at the first step, which will refetch the instruction, this
time finding it in the cache
40. What is write through cache
The simplest way to keep the main memory and the cache consistent is always to write the
data into both the memory and the cache. • This scheme is called write-through.
41. What is write back cache
In a write back scheme, when a write occurs, the new value is written only to the block in the
cache.
42.What are the techniques to improve cache performance?
Two different techniques for improving cache performance. • One focuses on reducing the
miss rate by reducing the probability that two different memory blocks will participate for the
same cache location. • The second technique reduces the miss penalty by adding an
additional level to the hierarchy. This technique, called multilevel caching
43. Define dirty bit
dirty bit is commonly used. This status bit indicates whether the block is dirty (modified
while in the cache) or clean (not modified).
44. What is TLB.
Translation-lookaside buffer (TLB)A cache that keeps track of recently used address
mappings to try to avoid an access to the page table.
45. What are the messages transferred in DMA?
To initiate the transfer of a block of words , the processor sends, i) Starting address ii)
Number of words in the block iii)Direction of transfer.
46. Define Burst mode.
Burst Mode: The DMA controller may be given exclusive(limited) access to the main
memory to transfer a block of data without interruption. This is known as Burst/Block Mode.
47. Define bus master
Bus Master: The device that is allowed to initiate data transfers on the bus at any given time
is called the bus master
48. Define bus arbitration.
Bus Arbitration: It is the process by which the next device to become the bus master is
selected and the bus mastership is transferred to it.
49. What are the approaches for bus arbitration?
There are 2 approaches to bus arbitration. They are i)Centralized arbitration ( A single bus
arbiter performs arbitration) ii)Distributed arbitration (all devices participate in the selection
of next bus master).
PART –B (13 MARKS)
1. Explain in detail about memory Technologies.
2. Expain in detail about memory Hierarchy with neat diagram.
3. Discuss the various mapping schemes used in cache memory.
4. Discuss the methods used to measure and improve the performance of the cache.
5. Explain the virtual memory address translation and TLB with necessary diagram.
6. Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer
between memory and peripherals.
7. Explain in detail about interrupts with diagram.
8. Describe in detail about programmed Input/ Output with neat diagram .
9. Explain in detail about the bus arbitration techniques.
10. Draw different memory address layouts and brief about the technique used to increase the average rate of
fetching words from the main memory .
11. Explain in detail about any two standard input and output interfaces required to connect the I/O devices to
the bus.
12. Explain mapping functions in cache memory in cache memory to determine how memory blocks are
placed in cache .
13. Explain the various mapping techniques associated with cache memories.
14. Explain sequence of operations carried on by a processor when interrupted by a peripheral device
connected to it.
15. Explain virtual memory and the advantages of using virtual memory.