CS 61C Reference Card Version 4.1.

Instruction Name Description Type Opcode Funct3 Funct7

add rd rs1 rs2 ADD rd = rs1 + rs2 R 011 0011 000 000 0000
sub rd rs1 rs2 SUBtract rd = rs1 - rs2 R 011 0011 000 010 0000
and rd rs1 rs2 bitwise AND rd = rs1 & rs2 R 011 0011 111 000 0000
or rd rs1 rs2 bitwise OR rd = rs1 | rs2 R 011 0011 110 000 0000
xor rd rs1 rs2 bitwise XOR rd = rs1 ^ rs2 R 011 0011 100 000 0000
sll rd rs1 rs2 Shift Left Logical rd = rs1 << rs2 R 011 0011 001 000 0000
srl rd rs1 rs2 Shift Right Logical rd = rs1 >> rs2 (Zero-extend) R 011 0011 101 000 0000
sra rd rs1 rs2 Shift Right Arithmetic rd = rs1 >> rs2 (Sign-extend) R 011 0011 101 010 0000
slt rd rs1 rs2 Set Less Than rd = (rs1 < rs2) ? 1 : 0 R 011 0011 010 000 0000
(signed)
sltu rd rs1 rs2 Set Less Than R 011 0011 011 000 0000
(Unsigned)
addi rd rs1 imm ADD Immediate rd = rs1 + imm I 001 0011 000
Arithmetic

andi rd rs1 imm bitwise AND rd = rs1 & imm I 001 0011 111
Immediate
ori rd rs1 imm bitwise OR rd = rs1 | imm I 001 0011 110
Immediate
xori rd rs1 imm bitwise XOR rd = rs1 ^ imm I 001 0011 100
Immediate
slli rd rs1 imm Shift Left Logical rd = rs1 << imm I* 001 0011 001 000 0000
Immediate
srli rd rs1 imm Shift Right Logical rd = rs1 >> imm (Zero-extend) I* 001 0011 101 000 0000
Immediate
srai rd rs1 imm Shift Right Arithmetic rd = rs1 >> imm (Sign-extend) I* 001 0011 101 010 0000
Immediate
slti rd rs1 imm Set Less Than rd = (rs1 < imm) ? 1 : 0 I 001 0011 010
Immediate (signed)
sltiu rd rs1 imm Set Less Than I 001 0011 011
Immediate
(Unsigned)
lb rd imm(rs1) Load Byte rd = 1 byte of memory at address I 000 0011 000
rs1 + imm, sign-extended
lbu rd imm(rs1) Load Byte rd = 1 byte of memory at address I 000 0011 100
(Unsigned) rs1 + imm, zero-extended
lh rd imm(rs1) Load Half-word rd = 2 bytes of memory starting at I 000 0011 001
address rs1 + imm, sign-extended
lhu rd imm(rs1) Load Half-word rd = 2 bytes of memory starting at I 000 0011 101
(Unsigned) address rs1 + imm, zero-extended
Memory

lw rd imm(rs1) Load Word rd = 4 bytes of memory starting at I 000 0011 010

address rs1 + imm
sb rs2 imm(rs1) Store Byte Stores least-significant byte of rs2 at S 010 0011 000
the address rs1 + imm in memory
sh rs2 imm(rs1) Store Half-word Stores the 2 least-significant bytes of S 010 0011 001
rs2 starting at the address rs1 +
imm in memory
sw rs2 imm(rs1) Store Word Stores rs2 starting at the address S 010 0011 010
rs1 + imm in memory
 Instruction Name Description Type Opcode Funct3

beq rs1 rs2 label Branch if EQual if (rs1 == rs2) B 110 0011 000
PC = PC + offset
bge rs1 rs2 label Branch if Greater or Equal (signed) if (rs1 >= rs2) B 110 0011 101
bgeu rs1 rs2 label Branch if Greater or Equal (Unsigned) PC = PC + offset B 110 0011 111
blt rs1 rs2 label Branch if Less Than (signed) if (rs1 < rs2) B 110 0011 100
bltu rs1 rs2 label Branch if Less Than (Unsigned) PC = PC + offset B 110 0011 110
bne rs1 rs2 label Branch if Not Equal if (rs1 != rs2) B 110 0011 001
Control

PC = PC + offset
jal rd label Jump And Link rd = PC + 4 J 110 1111
PC = PC + offset
jalr rd rs1 imm Jump And Link Register rd = PC + 4 I 110 0111 000
PC = rs1 + imm
auipc rd immu Add Upper Immediate to PC imm = immu << 12 U 001 0111
rd = PC + imm
lui rd immu Load Upper Immediate imm = immu << 12 U 011 0111
rd = imm
Other

ebreak Environment BREAK Asks the debugger to do I 111 0011 000

something (imm = 0)
ecall Environment CALL Asks the OS to do I 111 0011 000
something (imm = 1)
mul rd rs1 rs2 MULtiply (part of mul ISA extension) rd = rs1 * rs2 (omitted)
Ext

# Name Description # Name Desc Pseudoinstruction Name Description Translation

x0 zero Constant 0 x16 a6 Args beqz rs1 label Branch if if (rs1 == 0) beq rs1 x0 label
x1 ra Return x17 a7 EQuals Zero PC = PC + offset
Address bnez rs1 label Branch if Not if (rs1 != 0) bne rs1 x0 label
x2 sp Stack x18 s2 Equals Zero PC = PC + offset
Pointer j label Jump PC = PC + offset jal x0 label
x3 gp Global x19 s3 jal label Jump and Link PC = PC + offset jal ra label
Pointer ra = PC + 4
x4 tp Thread x20 s4 jr rs1 Jump Register PC = rs1 jalr x0 rs1 0
Saved Registers

Pointer
la rd label Load absolute rd = &label auipc, addi
x5 t0 x21 s5 Address
Temporary
x6 t1 x22 s6 li rd imm Load Immediate rd = imm lui (if needed), addi
Registers
x7 t2 x23 s7 mv rd rs1 MoVe rd = rs1 addi rd rs1 0
x8 s0 Saved x24 s8 neg rd rs1 NEGate rd = -rs1 sub rd x0 rs1
x9 s1 Registers x25 s9 nop No OPeration do nothing addi x0 x0 0
x10 a0 Function x26 s10 not rd rs1 bitwise NOT rd = ~rs1 xori rd rs1 -1
x11 a1 Arguments x27 s11
or Return ret RETurn PC = ra jalr x0 x1 0
Values 31 25 24 20 19 15 14 12 11 7 6 0
x12 a2 x28 t3
Temporaries

R funct7 rs2 rs1 funct3 rd opcode

x13 a3 Function x29 t4 I imm[11:0] rs1 funct3 rd opcode
x14 a4 Arguments x30 t5
I* funct7 imm[4:0] rs1 funct3 rd opcode
x15 a5 x31 t6
S imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
Caller saved registers
B imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode
Callee saved registers (except x0, gp, tp)
U imm[31:12] rd opcode
Immediates are sign-extended to 32 bits,
except in I* type instructions J imm[20|10:1|11|19:12] rd opcode
 Selected ASCII values
HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR
0x20 32 SPACE 0x30 48 0 0x40 64 @ 0x50 80 P 0x60 96 ` 0x70 112 p
0x21 33 ! 0x31 49 1 0x41 65 A 0x51 81 Q 0x61 97 a 0x71 113 q
0x22 34 " 0x32 50 2 0x42 66 B 0x52 82 R 0x62 98 b 0x72 114 r
0x23 35 # 0x33 51 3 0x43 67 C 0x53 83 S 0x63 99 c 0x73 115 s
0x24 36 $ 0x34 52 4 0x44 68 D 0x54 84 T 0x64 100 d 0x74 116 t
0x25 37 % 0x35 53 5 0x45 69 E 0x55 85 U 0x65 101 e 0x75 117 u
0x26 38 & 0x36 54 6 0x46 70 F 0x56 86 V 0x66 102 f 0x76 118 v
0x27 39 ' 0x37 55 7 0x47 71 G 0x57 87 W 0x67 103 g 0x77 119 w
0x28 40 ( 0x38 56 8 0x48 72 H 0x58 88 X 0x68 104 h 0x78 120 x
0x29 41 ) 0x39 57 9 0x49 73 I 0x59 89 Y 0x69 105 i 0x79 121 y
0x2A 42 * 0x3A 58 : 0x4A 74 J 0x5A 90 Z 0x6A 106 j 0x7A 122 z
0x2B 43 + 0x3B 59 ; 0x4B 75 K 0x5B 91 [ 0x6B 107 k 0x7B 123 {
0x2C 44 , 0x3C 60 < 0x4C 76 L 0x5C 92 \ 0x6C 108 l 0x7C 124 |
0x2D 45 - 0x3D 61 = 0x4D 77 M 0x5D 93 ] 0x6D 109 m 0x7D 125 }
0x2E 46 . 0x3E 62 > 0x4E 78 N 0x5E 94 ^ 0x6E 110 n 0x7E 126 ~
0x2F 47 / 0x3F 63 ? 0x4F 79 O 0x5F 95 _ 0x6F 111 o 0x00 0 NULL
C Format String Specifiers IEEE 754 Floating Point Standard
Specifier Output
Sign Exponent Significand
d or i Signed decimal integer Single Precision 1 bit 8 bits (bias = -127) 23 bits
u Unsigned decimal integer Double Precision 1 bit 11 bits (bias = -1023) 52 bits
o Unsigned octal Quad Precision 1 bit 15 bits (bias = -16383) 112 bits
x Unsigned hexadecimal integer, Standard exponent bias: - (2 E-1
-1) where E is the number of exponent bits
lowercase
X Unsigned hexadecimal integer,
SI Prefixes
uppercase Size Prefix Symbol Size Prefix Symbol Size Prefix Symbol
f Decimal floating point, 10-3 milli- m 103 kilo- k 210 kibi- Ki
lowercase
10-6 micro- μ 106 mega- M 220 mebi- Mi
F Decimal floating point,
uppercase 10-9 nano- n 109 giga- G 230 gibi- Gi
e Scientific notation 10-12 pico- p 1012 tera- T 240 tebi- Ti
(significand/exponent), lowercase
10-15 femto- f 1015 peta- P 250 pebi- Pi
E Scientific notation
(significand/exponent), uppercase 10-18 atto- a 1018 exa- E 260 exbi- Ei
g Use the shortest representation: 10-21 zepto- z 1021 zetta- Z 270 zebi- Zi
%e or %f
10-24 yocto- y 1024 yotta- Y 280 yobi- Yi
G Use the shortest representation:
%E or %F Laws of Boolean Algebra
a Hexadecimal floating point,
lowercase
A Hexadecimal floating point,
uppercase
c Character
s String of characters
p Pointer address
 RegWriteData
ALU
PC+4
+4
PC+4
0 PC
PC
ALU
1 RegFile
IMEM RegWriteData 1 DMEM
A
RegReadData1 0
inst[11:7] ALU
inst RegWriteIndex Branch MemAddress 1
PC Comp ALU PC+4
inst[19:15] 2
RegReadIndex1
Mem
RegReadData2 0 MemReadData 0
inst[24:20] B
RegReadIndex2 1
RegWEn
MemWriteData
Imm
Gen MemRW
PCSel inst[31:0] RegWEn ImmSel BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel
 ALU
+4
PC+4
0
PC +4
ALU
1 PC RegFile PC PC
IMEM RegWriteData 1 DMEM
A
RegReadData1 0
ALU
inst[11:7] RegRead
Branch MemAddress 1
RegWriteIndex Data1
PC Comp ALU ALU PC+4
inst[19:15] Out 2
inst RegReadIndex1
inst RegReadData2 0 MemReadData Mem
0
inst[24:20] RegRead B
RegReadIndex2 1
Data2
RegWEn
MemWriteData
Imm RegRead
Gen Data2 MemRW
imm
inst inst inst
inst (WB) RegWEn inst (ID) ImmSel inst (EX) BrUn BrEq BrLT BSel ASel ALUSel MemRW inst (M) PCSel WBSel