This document contains a summary of assembly instructions for the MIPS32 architecture organized into categories such as arithmetic/logical instructions, branch/jump instructions, load/store instructions, and system call instructions. It provides the instruction name and a brief description of the operation for each instruction type.
This document contains a summary of assembly instructions for the MIPS32 architecture organized into categories such as arithmetic/logical instructions, branch/jump instructions, load/store instructions, and system call instructions. It provides the instruction name and a brief description of the operation for each instruction type.
abs Rdest, Rsrc Absolute Value b label Branch instruction
add Rdest, Rsrc1, Src2 Addition (with overflow) bczt label Branch Coprocessor z True addi Rdest, Rsrc1, Imm Addition Immediate (with overflow) bczf label Branch Coprocessor z False addu Rdest, Rsrc1, Src2 Addition (without overflow) beq Rsrc1, Src2, label Branch on Equal addiu Rdest, Rsrc1, Imm Addition Immediate (without overflow) beqz Rsrc, label Branch on Equal Zero and Rdest, Rsrc1, Src2 AND bge Rsrc1, Src2, label Branch on Greater Than Equal andi Rdest, Rsrc1, Imm AND Immediate bgeu Rsrc1, Src2, label Branch on GTE Unsigned div Rsrc1, Rsrc2 Divide (with overflow) bgez Rsrc, label Branch on Greater Than Equal Zero divu Rsrc1, Rsrc2 Divide (without overflow) bgezal Rsrc, label Branch on Greater Than Equal Zero div Rdest, Rsrc1, Src2 Divide (with overflow) And Link divu Rdest, Rsrc1, Src2 Divide (without overflow) bgt Rsrc1, Src2, label Branch on Greater Than mul Rdest, Rsrc1, Src2 Multiply (without overflow) bgtu Rsrc1, Src2, label Branch on Greater Than Unsigned mulo Rdest, Rsrc1, Src2 Multiply (with overflow) bgtz Rsrc, label Branch on Greater Than Zero mulou Rdest, Rsrc1, Src2 Unsigned Multiply (with overflow) ble Rsrc1, Src2, label Branch on Less Than Equal mult Rsrc1, Rsrc2 Multiply bleu Rsrc1, Src2, label Branch on LTE Unsigned multu Rsrc1, Rsrc2 Unsigned Multiply blez Rsrc, label Branch on Less Than Equal Zero neg Rdest, Rsrc Negate Value (with overflow) bgezal Rsrc, label Branch on Greater Than Equal Zero negu Rdest, Rsrc Negate Value (without overflow) And Link nor Rdest, Rsrc1, Src2 NOR bltzal Rsrc, label Branch on Less Than And Link not Rdest, Rsrc NOT blt Rsrc1, Src2, label Branch on Less Than or Rdest, Rsrc1, Src2 OR bltu Rsrc1, Src2, label Branch on Less Than Unsigned ori Rdest, Rsrc1, Imm OR Immediate bltz Rsrc, label Branch on Less Than Zero rem Rdest, Rsrc1, Src2 Remainder bne Rsrc1, Src2, label Branch on Not Equal remu Rdest, Rsrc1, Src2 Unsigned Remainder bnez Rsrc, label Branch on Not Equal Zero rol Rdest, Rsrc1, Src2 Rotate Left j label Jump ror Rdest, Rsrc1, Src2 Rotate Right jal label Jump and Link sll Rdest, Rsrc1, Src2 Shift Left Logical jalr Rsrc Jump and Link Register sllv Rdest, Rsrc1, Rsrc2 Shift Left Logical Variable jr Rsrc Jump Register sra Rdest, Rsrc1, Src2 Shift Right Arithmetic srav Rdest, Rsrc1, Rsrc2 Shift Right Arithmetic Variable Load srl Rdest, Rsrc1, Src2 Shift Right Logical srlv Rdest, Rsrc1, Rsrc2 Shift Right Logical Variable la Rdest, address Load Address sub Rdest, Rsrc1, Src2 Subtract (with overflow) lb Rdest, address Load Byte subu Rdest, Rsrc1, Src2 Subtract (without overflow) lbu Rdest, address Load Unsigned Byte xor Rdest, Rsrc1, Src2 XOR ld Rdest, address Load Double-Word xori Rdest, Rsrc1, Imm XOR Immediate lh Rdest, address Load Halfword lhu Rdest, address Load Unsigned Halfword Constant-Manipulating lw Rdest, address Load Word lwcz Rdest, address Load Word Coprocessor z li Rdest, imm Load Immediate lwl Rdest, address Load Word Left lwr Rdest, address Load Word Right Comparison ulh Rdest, address Unaligned Load Halfword ulhu Rdest, address Unaligned Load Halfword Unsigned seq Rdest, Rsrc1, Src2 Set Equal ulw Rdest, address Unaligned Load Word sge Rdest, Rsrc1, Src2 Set Greater Than Equal sgeu Rdest, Rsrc1, Src2 Set Greater Than Equal Unsigned Store sgt Rdest, Rsrc1, Src2 Set Greater Than sgtu Rdest, Rsrc1, Src2 Set Greater Than Unsigned sb Rsrc, address Store Byte sle Rdest, Rsrc1, Src2 Set Less Than Equal sd Rsrc, address Store Double-Word sleu Rdest, Rsrc1, Src2 Set Less Than Equal Unsigned sh Rsrc, address Store Halfword slt Rdest, Rsrc1, Src2 Set Less Than sw Rsrc, address Store Word slti Rdest, Rsrc1, Imm Set Less Than Immediate swcz Rsrc, address Store Word Coprocessor z sltu Rdest, Rsrc1, Src2 Set Less Than Unsigned swl Rsrc, address Store Word Left sltiu Rdest, Rsrc1, Imm Set Less Than Unsigned Immediate swr Rsrc, address Store Word Right sne Rdest, Rsrc1, Src2 Set Not Equal ush Rsrc, address Unaligned Store Halfword usw Rsrc, address Unaligned Store Word Data Movement System Calls move Rdest, Rsrc Move 1 print_int ENTRADA: $a0 = integer mfhi Rdest Move From hi 2 print_float ENTRADA: $f12 = float mflo Rdest Move From lo 3 print_double ENTRADA: $f12 = double mthi Rdest Move To hi 4 print_string ENTRADA: $a0 = string mtlo Rdest Move To lo 5 read_int SALIDA: integer (in $v0) 6 read_float SALIDA: float (in $f0) mfcz Rdest, CPsrc Move From Coprocessor z 7 read_double SALIDA: double (in $f0) mfc1.d Rdest, FRsrc1 Move Double From Coprocessor 1 8 read_string ENTRADA: $a0 = buffer, $a1 = length mtcz Rsrc, CPdest Move To Coprocessor z