ABSTRACT

In parallel communication, due to simultaneous transmission of data bits the cost and
complexity increases. Serial communication removes this drawback and shows effective results
for long distance communication. UART (Universal Asynchronous Receiver Transmitter) is
referred as serial communication protocol. This report contains implementation of UART with
different baud rates. UART comprises three main modules baud rate generator, transmitter,
receiver. Further, it is tested on hardware boards i.e. FPGA. We used Virtex 5 board for testing
of UART as it holds the requirement needed for our project. The language used to design UART
is Verilog which is a hardware descriptive language. And tool used is Xilinx ISE design suit
14.7.

Keywords: UART, RTL, FPGA, PAR,THR

CONTENTS

List of Figures i

List of Tables ii

Abbreviations, Notations and Nomenclature iii

1. Introduction 1
2. Literature Survey 3
2.1 Specification Extraction 4
3. Pre-Requirements of Projects 5
3.1 Concept of Project 5
3.2 What is UART? 5
3.3 Synchronous and Asynchronous Transmission 6
3.4 Serial Communication 7
3.5 Baud Rate and Bit Rate 7
3.6 Tools used in project 8
4. Proposed Method 10
4.1 Top Level Diagram 10
4.2 Architecture 11
4.2.1 Transmitter Module 12
4.2.2 Receiver Module 14
4.2.3 Baud Rate Generator Module 17
5. Experimental Results 20
5.1 RTL Schematics 20
5.2 Design Reports 21
5.2.1 Synthesis Report 21
5.2.2 Map Report 26
5.2.3 Static Timing Report 28
5.2.4 Place and Route Report 30
5.3 RTL Simulations 32
5.3.1 Transmitter Simulation 32
5.3.2 Receiver Simulation 34
5.3.3 Baud Rate Generator Simulation 37
5.3.4 Top Level Simulation 38
6. Conclusions and Future Scope 39
6.1 Conclusion 39
 6.2 Future Scope 39
6.2.1 Transmitter Module 39
6.2.2 Receiver Module 40
6.2.3 Baud Rate Generator Module 41

References 43
 List of Figures

Fig. 1.1 Basic data frame of UART 2

Fig. 3.1 Virtex 5 FPGA board. 9
Fig. 4.1 Top level diagram of UART 10
Fig. 4.2 Architecture of UART 11
Fig. 4.3 Micro-architecture of transmitter module 12
Fig. 4.4 FSM for transmitter module 13
Fig. 4.5 Micro-architecture of receiver module 14
Fig. 4.6 FSM for receiver module 16
Fig. 4.7 Micro-architecture of baud rate generator 17
Fig. 4.8 Micro-architecture UART 19
Fig. 5.1 Block Level RTL Schematic 20
Fig. 5.2 Transmitter RTL Schematic 20
Fig. 5.3 Receiver RTL Schematic 21
Fig. 5.4 FPGA before PAR 31
Fig. 5.5 FPGA after PAR 31
Fig. 5.6 Simulation of Transmitter block of UART 33
Fig. 5.7 Simulation of Transmitter with false start bit 34
Fig. 5.8 Simulation of Transmitter with false stop bit 34
Fig. 5.9 Simulation of Receiver Block of UART 35
Fig. 5.10 Simulation of Receiver with false start bit 36
Fig. 5.11 Simulation of Receiver with false stop bit 36
Fig. 5.12 Simulation of Baud Rate Generator of UART 37
Fig. 5.13 Top Level Simulation of UART 38
Fig. 6.1 Transmitter module 39
Fig. 6.2 Receiver module 41

i
 List of Tables

Table 3.1 Synchronous and asynchronous transmission 6

Table 3.2 Bit rate and baud rate 8
Table 4.1 Pin description for top level diagram of UART 10
Table 4.2 Pin description of transmitter module 12
Table 4.3 Pin description for receiver module 15
Table 4.4 Pin description for baud rate generator 17
Table 5.1 Setup/Hold to clock sel_baud<0> 28
Table 5.2 Setup/Hold to clock sel_baud<1> 28
Table 5.3 Clock sel_baud<0> to Pad 29
Table 5.4 Clock sel_baud<1> to Pad 29
Table 5.5 Clock to Setup on destination clock clk 30
Table 5.6 Clock to Setup on destination clock sel_baud<0> 30
Table 5.7 Clock to Setup on destination clock sel_baud<1> 30
Table 5.8 Representation of States 32
Table 5.9 Representation of different Baud rates 37

ii
 Abbreviations, Notations and Nomenclature

UART Universal Asynchronous Receiver Transmitter

FPGA Field Programmable Gate Array
RTL Register Transfer Logic
THR Transmitter Hold Register
TSR Transmitter Shift Register
RHR Receiver Hold Register
RSR Receiver Shift Register
FSM Finite State Machine
LUT Look Up Table
HDL Hardware Description Language
PAR Place and Route
LSB Least Significant Bit
MSB Most Significant Bit
FIFO First In First Out

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 UART Implementation using FPGA

CHAPTER 1

INTRODUCTION
The FPGA consist of I/O processor (IOP) core and Front- End Subsystem. IOP is
used to handle data communication between PC and Design Under Test (DUT) in the FPGA
board. The IOP in UART module is utilized for serial communication.
UART stands for Universal Asynchronous Receiver Transmitter. UART is the
combination of hardware used for serial communication between computer and any other
peripheral devices. As we know, the processing of data in personal computers or any other
peripheral devices is in parallel form as it ensures speed. But the data communication in these
systems is in serial form, so first the data in parallel form is to be converted to serial form. To do
this process, UART is responsible for breaking parallel data into serial form and again convert it
to parallel form at the receiver end.
UART is called ‘Universal’ because the data frame and transmission speed can be
configured as per the requirement. And ‘Asynchronous’ as the transmitter and receiver are not
synchronized by a clock signal. UART needs two signals rx_data and tx_data. Tx_data is output
of the UART and rx_data is input to UART. In UART, it consists of two extra bits start and stop
bit. When data is sent ‘start bit’ is inserted at the beginning of the data frame and stop bit is
inserted at the end of the data frame. The start bit sends a signal to the receiver telling that the
data bits are to be sent and force the clock to synchronize with the transmitter clock.
After adding the start bit, the data bits are sent one by one with first sending LSB
and then remaining bits. In receiver, the data bits are counted bit by bit using the counter. After
every data bit is received it is converted into parallel form and transmitted to other peripheral
devices

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 UART Implementation using FPGA

Fig. 1.1 Basic data frame of UART

The clock synchronization is absent between transmitter and receiver. To synchronize transmitter
and receiver start bit and stop bit is used. UART design for FPGA can act as an interface for
FPGA based embedded system which used soft core processors. This reduces external routing
problems and cost as FPGA contains huge number of logic gates unused. Using FPGA can be
good solutions for reconfiguration of the hardware devices.

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 UART Implementation using FPGA

CHAPTER 2

LITERATURE SURVEY
An electronic system requires a medium for communicating with the external world.
It can transfer data to another device, sending or receiving commands or just for debugging
purpose. The most common interface used is UART. As UART works on serial transmission
concept. In early days RS232 interface where used to connect serial port. But now many PC you
will come across has no serial port, so it is commonly implemented using USB, however
transmission concept is same. In UART main tasks are firstly to convert parallel data coming
from data bus in serial form. Then transmitting the serial data, finally after receiving data
converting it again into parallel form.

UART is used for serial communication. The UART has 3 main blocks transmitter,
receiver and baud rate generator. The first UART was designed by Western Digital in 1971. The
first UART is designed by Gordon Bell for PDP series of computers. The main innovation was
this UART was using sampling to convert signal to digital domain, providing more steady timing
than previous telegraphic circuits. To reduce cost of wiring and other components, DEC
shortened the line unit design into a single chip, this was first UART.

In 1980s National Semiconductor 8250 UART were used. 8250 UART has an on-
chip programmable bit rate generator which allowed to transmit data at any frequency. These
UART were used in IBM PC5150. To avoid problem such as interrupts and to increase
efficiency, Intel designed a UART 82510 which has two independent 4-byte FIFOs. They
introduced this UART in 1993. It allowed operation up to 288 Kbit/s. After Intel’s UART many
companies designed various UART with different capacities of FIFO buffers, and different speed
of transmission. Further, NXP Semiconductor introduced dual UART (DUART), comprising of
two channels for communication, control registers and counter/timer. The channels are
independently programmable and supports independent transmission and reception. Some dual
UART model are SCC2692, SC26C92, SC28L92, etc. By mounting the dual UART in common
package NXP also designed Quad UART and Octal UART.

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 UART Implementation using FPGA

2.1 Specification Extraction

Following are the specification extracted and implemented

1. Mode: Full Duplex.

2. Data Frame Sequence: 8 bits
3. Primary Frequency: 50MHz
4. Maximum Operating Frequency: 100MHz
5. 1 start bit, 1 stop bit.
6. No. of flags : 2.

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 UART Implementation using FPGA

CHAPTER 3
PRE-REQUIREMENTS OF PROJECT
3.1 Concept of Project
Before starting the project, one should look upon the pre-requirements needed for
their project. In this project, pre-requirements for UART Implementation using FPGA includes
the study of serial communication, how data is transferred from peripheral devices to computer
and vise-versa. UART transmitter starts the transmission by taking a data frame in parallel form
and advising the UART to transmit the data frame in a serial form. Similarly, the receiver must
detect transmission and receive the data in serial form, remove the start bit and stop bit, and store
the data frame in parallel form. As the project states, UART is Universal Asynchronous Receiver
Transmitter, we should know the difference between synchronous and asynchronous system.
There are some main terms that we should study before starting the project work and the main
terms includes UART, baud rate, data frame, etc. We should study the main block of UART
separately - transmitter, receiver and baud rate generator. As this will have registers, flip flops,
latches, counters and others one should know Area optimization technique so that less amount of
area must be used on the board. Now, we will study some concepts that we need in this project.

3.2 What is UART?

UART stands for Universal Asynchronous Receiver Transmitter which is a serial

communication interface protocol. UART sends and receives data in the form of chunks or
packets which are known as “transmission characters”. There are two types of communications
in UART, half duplex and full duplex communications. In full duplex, both ends can
communicate with each other simultaneously. For example, Telephone; users at both ends can
speak and listen to each other simultaneously. With reference to UART, in full duplex
communication one end can transmit as well as receive the bits. In half duplex system, both ends
communicate each other but one user at a time. For example, walkie-talkie; in which one user
speaks and other only listen and vice-versa. Half duplex is used to conserve bandwidth. In
UART at a time one end can be active either transmitting or receiving end.

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 UART Implementation using FPGA

3.3 Synchronous and Asynchronous transmission

In synchronous transmission, data is transmitted in form of packets or frames.

Synchronous transmission follows full duplex type of communication. There is synchronization
between transmitter and the receiver. In synchronous transmission, there is no gap between two
data frames. It is more efficient and trustworthy to send large data. The transmission is
coordinated with one or more clock signal in synchronous transmission.

In asynchronous transmission, data is transmitted in form of byte or characters.

Asynchronous transmission follows half duplex type of communication. Synchronization is not
required. In this transmission, start bit and stop is added to the data frame. Therefore, there is
some gap between two data frames. The transmission is coordinated with no clock signal,
asynchronous transmission does not depend on any clock signal.

Table 3.1 synchronous and asynchronous transmission

Synchronous transmission Asynchronous transmission

1. Data is transmitted in the form of 1. Data is transmitted in the form of byte

packets or frames or character.

2. Synchronous transmission is much 2. Asynchronous transmission is slower

faster than asynchronous than synchronous.
3. Synchronous transmission is not 3. Asynchronous transmission is
economical. economical.

4. There is constant time interval in 4. There is no constant time interval in

transmission. transmission.

5. There is no gap between two data frames 5. There is gap between data frames as
start bit and stop bit is added to the frame.

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 UART Implementation using FPGA

3.4 Serial Communication

In serial communication, the data is sent one bit at a time, sequential over the
communication channel. It is opposite to parallel communication, where all the data bits are sent
all at a time. In serial communication, data is in binary pulse form. Binary ‘1’ represents high
logic and binary ‘0’ represent low logic. Serial communication can be of many types depending
on the type of transmission mode. It has 3 transmission modes, simplex mode, half duplex, full
duplex.

a) Simplex mode:
The simplex mode is one-way communication technique. Only one user
(either the transmitter or receiver is active at a time). If transmitter transmits, the receiver
can also accept. For example, Radio and Television.
b) Half Duplex:
Both transmitter and receiver in half duplex mode are active but one at a time
that means if transmitter transmits, the receiver can accept the data but cannot send and vice-
versa. For example, internet. If a user sends a request for any website, the web server processes
the application and sends back the information.
c) Full Duplex:
Full duplex mode is widely used communication mode in the world. In this
mode, transmitter and receiver can transmit and receive simultaneously. For example,
smartphone.

3.5 Baud Rate and Bit Rate

Baud rate is defined as the number of signal units per second. Whereas, Bit rate is the
number of bits transmitted per second. The formula which relates both the terms is given below:

Bit rate = Baud rate x the number of bits per baud.

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 UART Implementation using FPGA

Table 3.2 bit rate and baud rate.

Bit rate Baud rate

Number of bits transmitted per second. Number of signal transmitted units per second.

Also called as number of bits travelled per Also called as number of characters travelled
second per second
Bit rate emphasize the computer efficiency Baud rate emphasize data transmission.

The formula for bit rate is: The formula for baud rate is:
= baud rate x number of bits per = bit rate / number of bits per baud
second

3.6 Tools used in project

Another important aspect to be known before is the language we are using,
in this we are using Verilog. Some may use VHDL or any other language. We must have brief
knowledge of Verilog. Software used here is Xilinx ISE design suite 14.7, we can also use
Vivado which is another tool for writing Verilog codes. Tool should be selected by looking the
specifications or the package we will be requiring or the FPGA board we will be using, it can be
of Virtex 5, Spartan 3E, Spartan 3A, Spartan 6, etc. These boards have their specification, we
should choose board matching our requirements. For pin description and other details about
FPGA boards refer the data sheet.

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 UART Implementation using FPGA

Fig. 3.1 Virtex 5 FPGA board.

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 UART Implementation using FPGA

CHAPTER 4
PROPOSED WORK
4.1 Top level diagram

Fig. 4.1 Top level diagram of UART

Table 4.1 Pin description for top level diagram of UART.

Pins Width I/O Description

d_in 8 bits Input Input data from data bus.

sel_baud 2 bits Input Used to select different baud set for different
values of pin.

sys_clk 1 bit Input Input clock to UART from FPGA board on

which it runs.

d_out 8 bits Output Output data sent to data bus.

rx_status 1 bit Output Shows status of receiver.

tx_status 1 bit Output Shows status of transmitter.

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 UART Implementation using FPGA

4.2 Architecture

Fig. 4.2 Architecture of UART

UART architecture consists of three main blocks Transmitter, Receiver and Baud rate
generator. The data is taken from the computer or the peripheral devices. Below are the block
level micro-architecture and working of the modules.

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 UART Implementation using FPGA

4.2.1 Transmitter Module

Block level micro-architecture of transmitter module is given below,

Fig. 4.3 Micro-architecture of transmitter module

Table 4.2 Pin description of transmitter module.

Pins Width I/O Description

d_in 8 bits Input Input to the transmitter form data bus.

tx_status 1 bit Output Shows the status of the transmitter module.

tx_data 1 bit Output Sends data to receiver bit by bit.

bclk 1 bit Input Input clock to transmitter module from baud rate
generator.

All the operations in transmitter are with respect to clock which runs on multiple
baud rates. The transmitter converts the 8-bit parallel data into serial data and adds start bit at
start of the data frame and stop bit at the end of the data frame.
In transmitter, the 8-bit data from data bus is loaded to transmitter hold register
(THR), it is an 8-bit register to store the data parallelly through d_in pin. Then after all the data is

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 UART Implementation using FPGA

loaded in THR then data is loaded in Transmitter shift Register (TSR) parallelly. In TSR, start bit
and stop bit is added to the data bits, transmitter shift register is of 10-bit size. TSR convert
parallel data into serial form and then data is transmitted serially bit by bit through tx_out. While
transmitting data LSB of the data bit is transmitted first and then remaining data is transmitted
and last stop bit is transmitted to stop the transmission. The clock given to transmitter block is
the baud clock (bclk) on which the baud rate is set. Counter is used in TSR to count the data bits.
Until and unless all the data is transmitted no other data can be stored in hold register.
In this project, transmitter is designed based of FSM used as given below,

Fig. 4.4 FSM for transmitter module.

Transmitter FSM have four states they are named as follows:

• Idle State.
• Start State.
• Data State.
• Stop State.
In transmitter FSM first state is idle state in which transmitter remains in idle
condition means nothing will going to happen in this state. But when desired input is given to
this state then there is change of state takes place. Here when valid start bit (logic ‘0’) is given

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 UART Implementation using FPGA

as input then state changes from idle to start state means in idle state there is a detection of
valid start bit. When invalid input is given in idle state then transmitter remains in same state
i.e. idle state. Output of this state is logic ‘0’ for valid input (logic ‘0’).

When transmitter is in start state input is logic ‘0’ which is valid so there is change of state
from the start state to data state. If input is not logic ‘0’ then transmitter goes in idle state. Start
state will not change to data state until valid start bit is detected. In data state transmitter sends
frame sequence given to the input of transmitter and when complete frame sequence is
transmitted then state changes to stop state otherwise transmitter will remain in same state until
the complete transmission of frame sequence.

Stop state of transmitter will detect stop bit (logic ‘1’). If there will be any error in stop bit,
then transmitter remains in stop state only otherwise it will again go to idle state to detect another
start bit. The above process continues till required number of bits will be transmitted.

4.2.2 Receiver Module

Block level micro-architecture of receiver module is given below,

Fig. 4.5 Micro-architecture of receiver module.

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 UART Implementation using FPGA

Table 4.3 Pin description for receiver module.

Pin Width I/O Description

rx_data 1 bit Input Input data from transmitter.

bclkx8 1 bit Input Input clock to receiver from baud rate generator.
Receiver clock is 8 times faster than transmitter clock.

rx_status 1 bit Output Shows status of receiver block.

d_out 8 bit Output Sends output data to PC or peripheral devices.

The receiver module is complex than the transmitter module. It runs 4 X baud rate
faster than transmitter. The serial data is received from transmitter through rx_data pin 1-bit at a
time serially. Then, rx_data pin jumps into logic 0 from logic 1 indicating beginning of the data
frame. The start bit is identified by change in level from high to low level and stop bit by change
in the level from low to high. After identifying start bit, all the data bits are sampled and counted
using the bit counter generated in the receiver. The counter counts the positive edge of the clock
at every riding edge of the clock 1 bit is counted. When count equals to 8 then it says all bits are
received and stored in an 8 bit Receiver Shift Register (RSR) and the data bits are converted into
parallel data. Then it sends the data bits to Receiver Hold Register (RHR) which is also an 8 bit
register. RSR send only data bits to RHR, start bit and stop bit is not sent. Then the parallel data
is sent to the data bus or peripheral device.
In this project, Receiver is designed based on FSM used as given below,

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 UART Implementation using FPGA

Fig. 4.6 FSM for receiver module

Receiver FSM also have same four states like transmitter they are named as follows:

• Idle State.
• Start State.
• Data State.
• Stop State.

In receiver FSM first state is idle state in which receiver remains in idle condition means
nothing will going to happen in this state. But when desired input is given to this state then there
is change of state takes place. Here when valid start bit (logic ‘0’) detected idle state changes
from idle to start state. When wrong bit is received in idle state then receiver remains in idle
state. Output of this state is logic ‘0’ for valid input (logic ‘0’).

When receiver is in start state then it will not detect any bit because valid bit is already
detected in idle state, so receiver simply changes it’s states from start to data state. In data state,
if valid frame sequence received then there will be change in state from data to stop state
otherwise receiver will remain in same state until the arrival of valid data.

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 UART Implementation using FPGA

Stop state of receiver will detect stop bit (logic ‘1’). If there will be any error in stop bit,
then receiver remains in stop state only otherwise it will again go to idle state to detect another
start bit. The above process continues till required number of bits will be received.

Both transmitter and receiver works on mealy machine means output depends on state as well as
input. There is change in output when any one of them changes (state or input).

4.2.3 Baud rate Generator Module

Block level micro-architecture of baud rate generator is given below,

Fig.4.7 Micro-architecture of baud rate generator.

Table 4.4 Pin description for baud rate generator.

Pin Width I/O Description

sys_clk 1 bit Input Input clock to baud rate generator from FPGA board.

sel_baud 2 bits Input Select lines to select different baud rates.

bclk 1 bit Output Output clock given to transmitter module.

bclk x 8 1 bit Output Output clock given to receiver module.

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 UART Implementation using FPGA

Baud rate generator is also used to divide frequency. By using given clock frequency
and requested baud rate we can calculate the frequency factor. In baud rate generator, the input to
the generator is system clock which is available on FPGA board in our project we used 50 MHz.
The clock is first divided by 8 by using the clock divider to get the data bits on the positive edge
of the clock. Then a parameterized counter is used to count the data bits and the counter runs on
the divided clock. The output of the parameterized counter is divided into different divisors of
different baud rates to run the process on these baud rates. The divisor is found by the formula
proposed as,

Divisor = sys. Clock / (8 x baud rate)

A specific baud rate is selected from a 4x1 multiplexer

according to the select lines. Then the output of this multiplexer is given to transmitter and
receiver on which they run. The receiver baud clock is 8 times faster than transmitter baud clock.
To get this difference in clock speeds the output of the multiplexer is first given to divide by 8
block and then given to transmitter block and the output of the multiplexer is directly given to
receiver.

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 UART Implementation using FPGA

Fig 4.8 Micro-architecture UART

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 UART Implementation using FPGA

CHAPTER 5

EXPERIMENTAL RESULTS

5.1 RTL Schematics

Fig. 5.1 Block Level RTL Schematic

Fig. 5.2 Transmitter RTL Schematic

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 UART Implementation using FPGA

Fig. 5.3 Receiver RTL Schematic

5.2 Design Reports

5.2.1 Synthesis Report
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source parameters
Input File Name : "uart_top_module.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "uart_top_module"
Output Format : NGC
Target Device : xc5vlx50t-1-ff1136

---- Source Options

Top Module Name : uart_top_module
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes

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 UART Implementation using FPGA

RAM Style : Auto

ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Use DSP Block : Auto
Automatic Register Balancing : No

---- Target Options

LUT Combining : Off
Reduce Control Sets : Off
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO

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 UART Implementation using FPGA

Cross Clock Analysis : NO

Hierarchy Separator :
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

=====================================================================
=====================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors :1
3-bit adder :1
# Counters :6
26-bit up counter :4
3-bit up counter :1
4-bit up counter :1
# Registers : 12
1-bit register : 10
3-bit register :1
4-bit register :1
# Comparators :8
26-bit comparator less :4
3-bit comparator less :2
4-bit comparator lessequal :2
# Tristates :1
1-bit tristate buffer :1

=====================================================================
=====================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs :1
# Adders/Subtractors :1

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 UART Implementation using FPGA

3-bit adder :1
# Counters :6
26-bit up counter :4
3-bit up counter :1
4-bit up counter :1
# Registers : 17
Flip-Flops : 17
# Comparators :8
26-bit comparator less :4
3-bit comparator less :2
4-bit comparator less equal :2

=====================================================================
=====================================================================
* Final Report *
=====================================================================
Final Results
RTL Top Level Output File Name : uart_top_module.ngr
Top Level Output File Name : uart_top_module
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No

Design Statistics
# IOs : 21

Cell Usage :
# BELS : 461
# GND :1
# INV :8
# LUT1 : 100
# LUT2 : 14
# LUT3 : 11
# LUT4 : 17
# LUT5 : 38
# LUT6 : 42
# MUXCY : 122
# MUXF7 :3
# VCC :1
# XORCY : 104

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 UART Implementation using FPGA

# FlipFlops/Latches : 129
# FD : 12
# FDE :3
# FDR :6
# FDRE : 107
# FDS :1
# Shift Registers :1
# SRLC16E :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers : 20
# IBUF : 10
# OBUF :9
# OBUFT :1
=====================================================================
====

Device utilization summary:

---------------------------

Selected Device : 5vlx50tff1136-1

Slice Logic Utilization:

Number of Slice Registers: 129 out of 28800 0%
Number of Slice LUTs: 231 out of 28800 0%
Number used as Logic: 230 out of 28800 0%
Number used as Memory: 1 out of 7680 0%
Number used as SRL: 1

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 235
Number with an unused Flip Flop: 106 out of 235 45%
Number with an unused LUT: 4 out of 235 1%
Number of fully used LUT-FF pairs: 125 out of 235 53%
Number of unique control sets: 13

IO Utilization:
Number of IOs: 21
Number of bonded IOBs: 21 out of 480 4%

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 UART Implementation using FPGA

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 32 3%

5.2.2 Map Report

Design Information
------------------
Command Line : map -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol
high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr
off -lc off -power off -o uart_top_module_map.ncd uart_top_module.ngd
uart_top_module.pcf
Target Device : xc5vlx50t
Target Package : ff1136
Target Speed : -1
Mapper Version : virtex5 -- $Revision: 1.55 $
Mapped Date : Tue Oct 08 [Link] 2019

Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Slice Logic Utilization:
Number of Slice Registers: 129 out of 28,800 1%
Number used as Flip Flops: 129
Number of Slice LUTs: 212 out of 28,800 1%
Number used as logic: 207 out of 28,800 1%
Number using O6 output only: 87
Number using O5 output only: 96
Number using O5 and O6: 24
Number used as Memory: 1 out of 7,680 1%
Number used as Shift Register: 1
Number using O6 output only: 1

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 UART Implementation using FPGA

Number used as exclusive route-thru: 4

Number of route-thrus: 100
Number using O6 output only: 100

Slice Logic Distribution:

Number of occupied Slices: 68 out of 7,200 1%
Number of LUT Flip Flop pairs used: 214
Number with an unused Flip Flop: 85 out of 214 39%
Number with an unused LUT: 2 out of 214 1%
Number of fully used LUT-FF pairs: 127 out of 214 59%
Number of unique control sets: 13
Number of slice register sites lost
to control set restrictions: 26 out of 28,800 1%

A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
Number of bonded IOBs: 21 out of 480 4%

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number used as BUFGs: 1
Average Fanout of Non-Clock Nets: 3.71

Peak Memory Usage: 566 MB

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Total REAL time to MAP completion: 23 secs

Total CPU time to MAP completion: 18 secs

5.2.3 Static Timing Report

All values displayed in nanoseconds (ns)

Table 5.1 Setup/Hold to clock sel_baud<0>

Source Max Setup to Max Hold to Internal Clock(s) Clock Phase

clk (edge) clk (edge)
d_in_parallel<1> 1.180(R) 4.862(R) rx_temp_clk_out 0.000
d_in_parallel<2> 2.174(R) 3.948(R) rx_temp_clk_out 0.000
d_in_parallel<3> 2.437(R) 3.705(R) rx_temp_clk_out 0.000
d_in_parallel<4> 2.329(R) 3.804(R) rx_temp_clk_out 0.000
d_in_parallel<5> 2.241(R) 3.884(R) rx_temp_clk_out 0.000
d_in_parallel<6> 2.033(R) 4.078(R) rx_temp_clk_out 0.000
d_in_parallel<7> 2.154(R) 3.965(R) rx_temp_clk_out 0.000
d_in_parallel<8> 1.763(R) 4.324(R) rx_temp_clk_out 0.000

Table 5.2 Setup/Hold to clock sel_baud<1>

Source Max Setup to Max Hold to Internal Clock(s) Clock Phase

clk (edge) clk (edge)
d_in_parallel<1> 1.387(R) 4.721(R) rx_temp_clk_out 0.000
d_in_parallel<2> 2.381(R) 3.807(R) rx_temp_clk_out 0.000
d_in_parallel<3> 2.664(R) 3.564(R) rx_temp_clk_out 0.000
d_in_parallel<4> 2.536(R) 3.663(R) rx_temp_clk_out 0.000
d_in_parallel<5> 2.448(R) 3.743(R) rx_temp_clk_out 0.000
d_in_parallel<6> 2.240(R) 4.937(R) rx_temp_clk_out 0.000
d_in_parallel<7> 2.361(R) 3.824(R) rx_temp_clk_out 0.000
d_in_parallel<8> 1.970(R) 4.183(R) rx_temp_clk_out 0.000

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Table 5.3 Clock sel_baud<0> to Pad

Destination clk(edge) to Internal Clock(s) Clock

PAD Phase
d_out_parallel<0> 12.666(R) rx_temp_clk_out 0.000
d_out_parallel<1> 12.777R) rx_temp_clk_out 0.000
d_out_parallel<2> 12.602(R) rx_temp_clk_out 0.000
d_out_parallel<3> 12.596(R) rx_temp_clk_out 0.000
d_out_parallel<4> 12.613(R) rx_temp_clk_out 0.000
d_out_parallel<5> 12.263(R) rx_temp_clk_out 0.000
d_out_parallel<6> 12.393(R) rx_temp_clk_out 0.000
d_out_parallel<7> 12.446(R) rx_temp_clk_out 0.000
tx_status 13.075(R) rx_temp_clk_out 0.000
rx_status 9.012(R) rx_temp_clk_out 0.000

Table 5.4 Clock sel_baud<1> to Pad

Destination clk(edge) to Internal Clock(s) Clock

PAD Phase
d_out_parallel<0> 12.525(R) rx_temp_clk_out 0.000
d_out_parallel<1> 12.636(R) rx_temp_clk_out 0.000
d_out_parallel<2> 12.461(R) rx_temp_clk_out 0.000
d_out_parallel<3> 12.455(R) rx_temp_clk_out 0.000
d_out_parallel<4> 12.472(R) rx_temp_clk_out 0.000
d_out_parallel<5> 12.122(R) rx_temp_clk_out 0.000
d_out_parallel<6> 12.252(R) rx_temp_clk_out 0.000
d_out_parallel<7> 12.305(R) rx_temp_clk_out 0.000
tx_status 13.934(R) rx_temp_clk_out 0.000
rx_status 8.684(R) rx_temp_clk_out 0.000

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Table 5.5 Clock to Setup on destination clock clk

Source Clock Src :Rise Src :Fall Src :Rise Src :Fall
Dest :Rise Dest :Rise Dest :Fall Dest :Fall
Clk 3.806
sel_baud<0> 2.163 2.163
sel_baud<1> 2.071 2.071

Table 5.6 Clock to Setup on destination clock sel_baud<0>

Source Clock Src :Rise Src :Fall Src :Rise Src :Fall
Dest :Rise Dest :Rise Dest :Fall Dest :Fall
sel_baud<0> 7.492
sel_baud<1> 7.492

Table 5.7 Clock to Setup on destination clock sel_baud<1>

Source Clock Src :Rise Src :Fall Src :Rise Src :Fall
Dest :Rise Dest :Rise Dest :Fall Dest :Fall
sel_baud<0> 7.492
sel_baud<1> 7.492

5.2.4 Place and Route Report

Device Utilization Summary:

Number of BUFGs 1 out of 32 3%

Number of External IOBs 21 out of 480 4%

Number of LOCed IOBs 0 out of 21 0%

Number of Slices 68 out of 7200 1%

Number of Slice Registers 129 out of 28800 1%

Number used as Flip Flops 129

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 UART Implementation using FPGA

Number used as Latches 0

Number used as LatchThrus 0

Number of Slice LUTS 212 out of 28800 1%

Number of Slice LUT-Flip Flop pairs 214 out of 28800 1%

Fig. 5.4 FPGA before PAR Fig. 5.5 FPGA after PAR

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 UART Implementation using FPGA

5.3 RTL Simulation

5.3.1 Transmitter Simulation

Input d_in pin is 10-bit register consist of start bit which is LSB, stop bit as MSB and
remaining bits as data bits. During transmission operation, for every positive edge of clock pulse
1 bit is transmitted. Pin named as tx_state is output pin showing the 4 states of FSM. Pin
bit_counter is 4-bit register which is used to count the number of bits. Counting depends upon
the positive edge of the clock signal. The bit counter is counting the bits which are given to d_in
register as input and counter is in reset condition after ‘1010’. Pin tx_status is output pin showing
the output logic ‘1’ in stop state. This shows that transmission has been completed and output of
this pin is again arriving at logic ‘0’ in next state which is idle state.

Table 5.8 Representation of States

States Representation Value

Idle 00
Start 01
Data 10
Stop 11

Data stored in the d_in register is in parallel form and it is transmitted serially through
output pin d_out_serial.

• Transmitter is in idle state until arrival of start bit (logic ‘0’).

• The process of transmission is initialized by the start bit which is low level signal. Start bit is
sent when the state of the transmitter is in start state.
• Counter is counting the bits according to the transition of clock pulse.
• After transmitting start bit transmitter is changing state from start to data state.
• In data state, data bits are transmitted bit by bit. Only 1 bit is transmitted for every clock
pulse.
• After transmitting required number of data bits state is changing from data to stop state.

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 UART Implementation using FPGA

• In stop state, signal having high level value means logic ‘1’ is transmitted for the
accomplishment of transmission.
• If after transmitting whole frame sequence of data only, until the stop bit is detected the state
of the transmitter will not change.
• Meanwhile the bit counter is increasing by 1 bit for every clock pulse and it is going in reset
position in the stop state.
• When transmission of stop bit is done tx_status pin is becoming high in the stop state which
indicates completion of transmission.
• The time required for complete transmission of frame sequence is different for different baud
rates.

The below figure is simulation result of transmitter block of UART. Here data frame of 8 bits
with start bit and stop bit is transmitted serially. From 1 to 8 bits can be transmitted in 1 frame
sequence at a time.

Fig. 5.6 Simulation of Transmitter block of UART

In figure (5.7) when the start bit is not zero then initialization of transmitter is not done, and
transmitter remains in idle state. The output pin d_out_serial is always logic ‘0’ even if data bits
are given as input to d_in pin.

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 UART Implementation using FPGA

Fig. 5.7 Simulation of Transmitter with false start bit

In figure (5.8) when stop bit is not logic ‘1’ then transmission is not done since tx_status pin is
not logic ‘1’ in stop state. Transmitter remains in stop state due absence of stop bit as logic ‘1’.

Fig. 5.8 Simulation of Transmitter with false stop bit

5.3.2 Receiver Simulation

The serial data transmitted by transmitter is input to the receiver. Pin rx_d_in _serial is
input pin of the receiver which is receiving frame sequence containing start bit and stop bit along
with data bits. Receiver output pin rx_d_out is 8-bit register which contains data bits taken from
transmitter. Pin rx_status is used to indicate the complete of reception of data bits by changing
it’s value from logic ‘0’ to logic ‘1’. Clock input given to the receiver have frequency 8 times the

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 UART Implementation using FPGA

frequency given to the transmitter. But both the receiver and transmitter have same baud rate.
Otherwise, process of transmission and reception is invalid.

• Frame sequence is input to the receiver at the pin rx_d_in_serial (e.g. ‘1000011110’).
• The important work of receiver here is to receiver data as input in serial format but output
given by it must in parallel form.
• Bit by bit data is coming through rx_d_in_serial pin which is sampled by receiver in a such
way that 8 clocks require to detect single bit.
• Firstly, receiver detects start bit in 8 clock cycles where the receiver remains in start state.
• Receiver is also working on FSM based mechanism. So, there are 4 states present in FSM of
receiver. These states have mentioned in transmitter simulation.
• Clock counter is counting number of clocks required to sample one bit, which is going in reset
condition after counting 8 clocks.
• Bit counter is used to count bits received. Receiver have output containing 8-bits, so bit
counter is in reset condition after ‘0111’.
• After detection of start bit receiver reject it and receiving bits of data frame.
• Similar process is used to detect data bits as that for start bit.

Fig. 5.9 Simulation of Receiver Block of UART

• Data bits are now received in the data state.
• After data bits stop bit (logic ‘0’) is detected by the receiver in stop state.
• Pin rx_status is logic ‘1’ when state changes from stop to idle which indicates completion of
reception.

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 UART Implementation using FPGA

• Pin rx_d_out is 8-bit register showing data bits (‘00001111’) as output.

• High impedance parameter during the process is indicated by the blue wave form.
• Red wave shows the invalid data present or there is an error.
• We can see that, start bit and stop bits have been rejected by the receiver because we require
only data bits.

When start bit is not logic ‘0’ then there is error in detection as shown in figure (5.10) since
there is no change is state of the receiver as receiver is remaining in idle state only.

Fig. 5.10 Simulation of Receiver with false start bit

When stop bit is not logic ‘1’ then receiver remains in stop state so rx_status pin is not high
which indicates that complete reception is abandoned till the arrival of valid stop bit.

Fig. 5.11 Simulation of Receiver with false stop bit

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 UART Implementation using FPGA

5.3.3 Baud Rate Generator Simulation

• Baud rate generator can select one baud rate at a time from 4 different bauds.
• The following table is showing different bauds with their unique representation value.
Table 5.9 Representation of different Baud rates

Baud Value Representation value

4800 00
9600 01
19200 10
115200 11

• The below result obtained for specific baud rate (e.g.115200) which is calculated by using
formula
• In the output of baud rate generator contains two frequencies, where one of the output have
frequency 8 times the other. Lower output frequency is given to the transmitter and higher
frequency is given to the receiver

Fig. 5.12 Simulation of Baud Rate Generator of UART

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 UART Implementation using FPGA

5.3.4 Top Level Simulation

In figure below, we can see that

• When we gave input as ‘1000011110’ to transmitter input d_in then it sends the data in serial
form through output pin d_out_serial.
• When transmission completed then we can see the output of the pin tx_status as logic ‘1’ for
very short duration indicates completion of the transmission of whole data sequence.
• At the same time receiver is receiving data serially through input pin rx_d_in_serial and each
bit is detected by receiver after 8th clock pulse.
• After complete reception of the data frame there is a peak in rx_status wave form for very short
duration suggests that there is complete reception of data frame.
• Various counters are counting the number of clocks and number of bits according their
function.

Fig. 5.13 Top Level Simulation of UART

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 UART Implementation using FPGA

CHAPTER 6
Conclusion and Future Scope
6.1 Conclusion
In this project, UART is designed with configurable baud rates. The language used in this
project is Verilog descriptive language to achieve reliable serial data communication. The
Transmitter and Receiver module of the UART are designed using finite state machine concept
and successfully synthesized using Xilinx ISE 14.7. The UART with different baud rates is
successfully simulated and has being verified on Xilinx ISE 14.7. The design is compatible for
high speed due different baud rates.

6.2 Future Scope

Thinking about improving the UART system, we can use status registers and error logic for
modifications. Considering the individual blocks of UART after making the modifications.

6.2.1 Transmitter module

Fig. 6.1 Transmitter module

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 UART Implementation using FPGA

In transmitter module, the input data from data bus was directly stored into the hold
register but now we have added a FIFO before transmitter hold register and reset pin to reset the
transmitter. There are two pins to FIFO ‘wr_in’ and ‘fifo_full’ pin. The write pin will set to high
if FIFO is ready to accept data or it is empty and if it is not empty the fifo_full pin will be set to
high. The data from data bus will now first stored in FIFO which is a 16-byte storage element.
After the data is sent to FIFO, it will send a high bit to transmitter hold register that it has data
and then hold register will send another signal indicating it is ready to receive. If it is empty and
data is loaded from FIFO to hold register parallelly.

Transmitter shift register which is of 11-bit size it adds start

bit, stop bit and parity bit to the data frame. TSR will send a signal to THR indicating it is ready
to receive the data and then data is sent from THR to TSR. The shift register will add start bit (0)
at the beginning of data bits and a stop bit (1) at the end of data, parity bit (0 or 1) depends on the
number of 1’s in the data frame. After adding the extra bits, the data is transmitted through
tx_data in serial form.

6.2.2 Receiver module

The data will be received serially through rx_data pin. The received data is given
to the timing and sampling sub module. The synchronication of transmitter and receiver is done
by the timing and control unit. Initially, the rx_data pin will be high, whenever it goes low it will
take samples of the data bit and indicates beginning of the data frame/ sequence. After sampling,
data bits are loaded to RSR (11-bit register) serially where the data frame is stored. Now, if
RHR is empty it will send a high bit to RSR indicating it is ready to receive the data bits and the
remaining bits are used for identifying the errors. If receiver FIFO is empty, it will sent high bit
to RHR and is ready to receive the data bits. And when rd_in pin is set to high the data is ready
to be sent parallelly to the peripheral devices or computer.

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 UART Implementation using FPGA

Fig. 6.2 Receiver module

The status flags are implemented for indentifying errors in received data. The
error logic has four types of errors: Parity Error (PE), Overrun Error (OE), Frame Error (FE),
Break Error (BE). If the received parity and generated parity bit is not same then PE is set to high
indicating parity error has occurred. If the receiver FIFO already holds a data and another data
comes at RHR, OE is set to high. If the receiver fails to detect the correct stop bit then FE is set
to high it indicates Frame error has occurred. If the rx_data pin is low for longer time greater
than the time of data frame then Break Error has occurred and BE is set to high.

6.2.3 Baud rate generator

In this project, we have taken only few baud rate into consideration and are set
manually. What is the baud rate is set automatically by identifying the baud rate of one of the
block either of tranmsitter or receiver. as the baud rates of transmitter and receiver block is same.
It specifies the rate at which transmitter or receiver should work. The most commonly used
number of bits in UART is 8-bit data which relates to 1 byte. Here we can use ASCII code to
determine the baud rate. When ASCII is used only 7 LSB bits are used and MSB is 0. Assuming
there is sufficient time between subsequent transmissions. In this process, ASCII code is used for
rate detection and then implement normal operations. The receiver uses the ASCII code to detect
the baud rate, then use that baud rate for baud rate generator and remaining process. Detected

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 UART Implementation using FPGA

baud rates can be 4800, 9600, 19200 and so on. There are two modes of UART in this scheme
‘detection mode’ and ‘normal mode’. In dectection mode, detection of baud rate takes place and
in normal mode remaining transmission and reception process is done. As the clock given to
transmitter and receiver is different, we can use a divider using D flip flop. The receiver baud
clock is 8 times faster than the transmitter baud clock.

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REFERENCES

[1] [Link] R. Laddha, Prof. A. P. Thakare, “A Review on Serial Communication by UART”,

Volume 3, Issue 1, January 2013 International Journal of Advanced Research in Computer

Science and Software Engineering.

[2] Kavyashree S, “Design and Implementation of UART using Verilog”, International Journal
Of Engineering And Computer Science ISSN:2319-7242 Volume – 4 Issue - 12 December, 2015
Page No. 15240-15245

[3] FANG Yi-yuan, CHEN Xue-jun, “Design and Simulation of UART Serial Communication
Module Based on VHDL”, College of Electrical and Electronic Engineering Shanghai University
of Engineering Science Shanghai, China

[4] KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User Guide

by Texas Instruments.

[5] Hazim Kamal Ansari, Asad Suhail Farooqi, “ Design Of High Speed Uart For Programming
Fpga”, International Journal Of Engineering And Computer Science Volume1 Issue 1 Oct 2012
Page No. 28-36

[6] Virtex 5 FPGA Starter Kit Board User Guide

[7] [Link] › products › silicon-devices › fpga

[8] Umakanta Nanda, Sushant Kumar Pattnaik, “Universal Asynchronous Receiver and
Transmitter(UART)”, 2016 3rd International Conference on Advanced Computing and
Communication Systems (ICACCS -2016), Jan. 22 – 23, 2016, Coimbatore, INDIA

[9] Abhay Malviya, Vijay Kumar Sharma, “An Improved Approach of UART Implementation in
VHDL using Status Register”, Volume 4, Issue 10, May 2016 International Journal of Digital
Application & Contemporary Research.

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