Design and Implementation of Uart Serial Communication Protocol
Design and Implementation of Uart Serial Communication Protocol
PROJECT COORDINATOR: Mrs. Ester Gandhimadhi INTERNAL GUIDE: Mrs. M.Nageswari Project Members: KISHORE.T
KAVI PRIYA.K.S
KARTHIKEYAN.R
ABSTRACT
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol. Used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language. Integrated into the FPGA to achieve compact, stable and reliable data transmission. Its significant for the design of SOC.
2003-2008 BYU
A UART may be used when: High speed is not required An inexpensive communication link between two devices is required UART communication is very cheap Single wire for each direction (plus ground wire) Asynchronous because no clock signal is transmitted Relatively simple hardware PC devices such as mice and modems used to often use UARTs for communication to the PC
UART Uses
Serial Cable
Serial Port
Serial Cable
Device
UART Uses
Serial Cable
Modem
Modem
UART Uses
Internet
Server
Serial Cable
Modem
UART Uses
Serial Cables
Terminal
UART Uses
Becoming much less common Largely been replaced by faster, more sophisticated interfaces
PCs: USB
(networking)
(peripherals),
Ethernet
UART Functions
Transmitter
Convert from parallel to serial Add start and stop delineators (bits) Add parity bit
Receiver
Convert from serial to parallel Remove start and stop delineators (bits) Check and remove parity bit
1 bit time
Start Bit
7 Data Bits
Stop Bit
Start bit
Line idling
Mark
Stop bit
1 Space
Mark
Space Receiver uses a timer (counter) to time when it samples. Transmission rate (i.e., bit duration) must be known!
Mark
Space
Mark
Space Receiver resynchronizes on every start bit. Only has to be accurate enough to read 9 bits.
UART Options
UART Options
Baud Rate
The symbol rate of the transmission system For a UART, same as the number of bits per second (bps) Each bit is 1/(rate) seconds wide
Example:
9600 baud 9600 Hz 9600 bits per second (bps) Each bit is 1/(9600 Hz) 104.17 s long
UART Throughput
10 bits
It takes 10 bits to send 8 bits (1 byte) of data 19.2 kbps 8/10 = 15.36 kbps
A Note on Signaling
RS232 is the most common UART standard Used by PC serial ports RS232 does NOT use positive logic Logic 1 is any signal from -25V to -3V Logic 0 is any signal from +3V to 25V The range -3V to +3V is a transition region that is not assigned to a logic level On an oscilloscope, an RS232 waveform looks inverted from the actual data values transmitted
Parameters: 9600 baud, 8 data bits, 1 stop bit, even or odd parity
Inputs: Din[7:0]: 8-bit parallel data input Send: Instructs transmitter to initiate a transmission ParitySelect: Selects even parity (ParitySelect=0) or odd parity (ParitySelect=1) Outputs: Dout: Serial data output
System Diagram
To host system
UART Transmitter
Dout
To serial cable
Transmitter/System Handshaking
System asserts Send and holds it high when it wants to send a byte UART asserts Busy signal in response When UART has finished transfer, UART de-asserts Busy signal System de-asserts Send signal
Send Busy
Parity Generator
ParityBit
Combinational circuit Generates ParityBit according to value of Din[6:0] and ParitySelect input
The value of ParityBit is the bit needed to make the number of 1s even (if even parity) or odd (if odd parity) Even Parity Odd Parity
(ParitySelect = 0) Even number of 1s (ParitySelect = 1)
ParityBit = 0
ParityBit = 1
Odd number of 1s
ParityBit = 1
ParityBit = 0
Din[0] Din[1] Din[2] Din[3] Din[4] Din[5] Din[6] Din[7] For 7-bit parity, tie Din[7] to a 0
Odd/Even# ParityBit
Transmitter
Send Reset
Idle
Send
Load Load Busy ResetCounter ResetTimer
Send
Send
Wait
Busy
Count
NextBit
NextBit Count10
Shift Shift Increment Busy
Count10
Be sure to choose state encodings and use logic minimization that ensures Busy signal will have no hazards!
REFERENCES
[1] Design and Simulation of UART Serial Communication Module Based on VHDL, FANG Yiyuan CHEN Xue-jun. [2] HU Hua, BAI Feng-e. Design and Simulation of UART Serial Communication Module Based on Verilog HDL[J]. J ISUANJ I YU XIANDA IHUA 2008 Vol. 8 [3]A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY,Mohd Yamani Idna Idris, Mashkuri Yaacob, Zaidi Razak. [4] A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY,Mohd Yamani Idna Idris, Mashkuri Yaacob, Zaidi Razak. [5] www.wikipedia.org
2003-2008 BYU
THANK YOU
2003-2008 BYU