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Open Collector Transistor Theory

This document summarizes a lecture about open collector gates. It discusses that open collector chips have no internal pull-up resistor and require an external resistor. Open collector gates can be used to implement a "wired AND" or "wired OR" depending on whether the output is active high or active low. An example circuit is given and the equations for the output in both the active high and active low cases are derived.

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Paul Casale
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158 views3 pages

Open Collector Transistor Theory

This document summarizes a lecture about open collector gates. It discusses that open collector chips have no internal pull-up resistor and require an external resistor. Open collector gates can be used to implement a "wired AND" or "wired OR" depending on whether the output is active high or active low. An example circuit is given and the equations for the output in both the active high and active low cases are derived.

Uploaded by

Paul Casale
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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University of Florida Joel D.

Schipper
ECE Department Summer 2007

LECTURE #8.5: Open Collector Gates


EEL 3701: Digital Logic and Computer Systems
Based on lecture notes by Dr. Eric M. Schwartz

Open Collectors:
***Never Connect Chip Outputs Together in the Laboratory***
-There are two types of logic chips where you may connect outputs:
-Tri-state buffers: Enables must be carefully controlled (see Lecture 08)
-Open Collector (O.C.) Logic Gates
-Your lab kit contains neither of these
***Never Connect Chip Outputs Together in the Laboratory***

-Transistor-Transistor Logic (TTL) uses bipolar junction transistors (BJT’s)

5V

OUTPUT
COLLECTOR
INPUT
BASE
EMITTER

Simple Inverter Circuit w/ BJT

-An input of 5V creates a short between collector and emitter (0V output)
-An input of 0V creates an open circuit between collector and emitter (5V output)
-What is this? An inverter.

-Open collector chips have no internal pull-up resistor


-You must add the resistor

Page 1 of 3
University of Florida Joel D. Schipper
ECE Department Summer 2007

-Usually, a vertical bar at the output is used to represent O.C. gates


-Sometimes the gate is simply labeled with the letters “O.C.”

Case 1: Active-High I/O Viewpoint (i.e. Z1, Z0, and Znet are active high)
If Z1 AND Z0 are high => Znet is high
Z net ( H ) = Z 1 ( H ) ⋅ Z 0 ( H )
Known as “wired AND”

“Wired AND” Representation

Case 2: Active-Low I/O Viewpoint (i.e. Z1, Z0, and Znet are active low)
If Z1 OR Z0 is low => Znet is low
Z net ( L) = Z 1 ( L) + Z 0 ( L)
Known as a “wired OR”

“Wired OR” Representation

Note: DeMorgan’s Law shows the two representations to be equivalent.


Note 2: Our figures show 4 inputs, but any number of inputs is allowable.

Page 2 of 3
University of Florida Joel D. Schipper
ECE Department Summer 2007

Example: Determine the equations for the following circuit where:


1) The output is active high
2) The output is active low

5V

A(L)
Z1
B(H)

C(H) Z0
Znet
D(L)

Case 1: Output is active high


Z1 ( H ) = A B Z net ( H ) = Z 1 ⋅ Z 0
Z 0 (H ) = C + D Z net ( H ) = A B ⋅ (C + D )

Case 2: Output is active low


Z 1 ( L) = A B Z net ( L) = Z 1 + Z 0
Z 0 ( L) = C + D Z net ( L) = A B + (C + D )

Note: Because active high is the complement of active low, Z net ( H ) = Z net ( L) .

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