Module No.

3
Control Unit Design
3.2 Microprogrammed Control Unit

P. M. Manegopale
Asst. Prof. VPPCOE & VA
Control Unit Implementation
• Hardwired
Memory Instruction code

Combinational . Control
Sequence Counter
Logic Circuits . signals

• Microprogrammed
CAR: Control Address Register
Memory Instruction code CDR: Control Data Register

Next Address . Control

Control CDR Decoding
Generator CA .
Memory Circuit signals
(sequencer) R
Microproramming
• The control unit is responsible for initiating the sequence of
microoperations that comprise instructions.
• When these control signals are generated by hardware,
the control unit is hardwired .
• A control unit whose binary control variables are stored in memory is
called a micro programmed control unit.
• The control function specifying a micro operation is a binary
variable whose active state could be either 1 or 0.
– In the variable ’s active state, the micro operation is
executed.
– The string of control variables which control the sequence of
micro operations is called a control word.
• The micro operations specified in a control word is called a
microinstruction.
The Microprogrammed Control Unit
– Each microinstruction specifies one or more
microoperations that is performed.
• The control unit coordinates stores microinstruction in its
own memory (usually ROM) and performed the necessary
steps to execute the sequences of microinstructions (called
microprograms).
• In a microprogrammed processor, the control unit
consists of:
– Control address register (CAR) – contains the address
of the next microinstruction to be executed.
– Control data register(CDR) –
– contains the microinstruction to be executed.
– The sequencer – determines the next address from
within control memory
– Control memory – where microinstructions are stored.
 Microprogrammed Control Unit
• A control unit whose binary control values are saved as
words in memory is called a microprogrammed control
unit.
• Thus, the sets of control signals are generated for a
definite micro-operations that can be saved in the
memory.
• Each bit that forms the microinstruction is linked to one
control signal. When the bit is set, the control signal is
active. When it is cleared the control signal turns inactive.
• These microinstructions in a sequence can be saved in
the internal ’control’ memory
Micro-programmed Control
• The Microprogrammed Control organization is
implemented by using the programming
approach.
• In Microprogrammed Control, the micro-
operations are performed by executing a
program consisting of micro-instructions.
Components

• The Control memory address register(CAR)

specifies the address of the micro-instruction.
• The Control memory is assumed to be a ROM,
within which all control information is permanently
stored.
• The control data register(CDR) holds the
microinstruction fetched from the memory.
• The micro-instruction contains a control word that
specifies one or more micro-operations for the data
processor.
• While the micro-operations are being executed,
the next address is computed in the next address
generator circuit and then transferred into the
control address register to read the next
microinstruction.
• The next address generator is often referred to
as a micro-program sequencer, as it determines
the address sequence that is read from control
memory.
Advantages & Disadvantages of
Microprogrammed Control Unit
• Advantages
• It can more systematic design of the control unit.
• It is simpler to debug and change.
• It can make the design of the control unit much
simpler. Hence, it is inexpensive and less error-prone.
• It can orderly and systematic design process.
• It is used to control functions implemented in
software and not hardware.
• It is more flexible.
• It is used to complex function is carried out easily.
• Disadvantages
• Adaptability is obtained at more cost.
• It is slower than a hardwired control unit.
Control Memory
• Read-only memory (ROM)
• Content of word in ROM at given address
specifies microinstruction
• Each computer instruction initiates series of
microinstructions (microprogram) in control
memory
• These microinstructions generate microoperations
to
— Fetch instruction from main memory
— Evaluate effective address
— Execute operation specified by instruction
— Return control to fetch phase for next instruction

Control Control word

Address memory (microinstruction)
(ROM)
Microprogrammed Control
Organization

External Next Address Control

input Control
Generator CA Memory CDR
word
(sequencer) R (ROM)

• Control memory
—Contains microprograms (set of
microinstructions)
—Microinstruction contains
– Bits initiate microoperations
– Bits determine address of next microinstruction
• Control address register (CAR)
—Specifies address of next microinstruction
Microprogrammed Control Organization

• Next address generator (microprogram

sequencer)
—Determines address sequence for control
memory
• Microprogram sequencer functions
—Increment CAR by one
—Transfer external address into CAR
—Load initial address into CAR to start control
operations
 Microprogrammed Control
Organization

• Control data register (CDR)- or pipeline

register
—Holds microinstruction read from control
memory
—Allows execution of microoperations specified by
control word simultaneously with generation of
next microinstruction
• Control unit can operate without CDR
External Next Address Control
input Control
Generator CAR Memory word
(sequencer) (ROM)
Address Sequencing
• Address sequencing capabilities required
in control unit
• Used to generate the address of next
instruction. It is obtained through-
—Incrementing CAR
—Unconditional or conditional branch,
depending on status bit conditions
—Mapping from bits of instruction to address for
control memory
—Facility for subroutine call and return
Address Sequencing

Instruction code

Mapping
logic

Status Branch MUX Multiplexers

bits logic select
Subroutine
Control Address Register Register
(CAR)
(SBR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Selection of address for control memory

• shows four different paths from which the control
address register (CAR) receives the address.
• 1) The incrementer, increments the content of the
control address register by one, to select the next
microinstruction in sequence.
• 2) Branching is achieved by specifying the branch
address in one of the fields of the microinstruction.
• Conditional branching is obtained by using part of the
microinstruction to select a specific status bit in order to
determine its condition.
• 3) An external address is transferred into control
memory via a mapping logic circuit
• 4) The return address for a subroutine is stored in a
special register whose value is then used when the
micro-program wishes to return from the subroutine.
• The status bits in the system that provide parameter
information such as the carry-out of an adder, the
sign bit of a number, the mode bits of an instruction,
and input or output status conditions.
• The status bits, together with the field in the
microinstruction that specifies a branch address,
control the conditional branch decisions generated in
the branch logic.
• A- 1 output in the multiplexer generates a control
signal to transfer the branch address
• from the microinstruction into the control address
register.
• A ―0‖ output in the multiplexer causes the address
register to be incremented.
Mapping of Instruction
• Each computer instruction has its own
microprogram routine stored in a given
location of the control memory
• Mapping
—Transformation from instruction code bits to
address in control memory where routine is
located
• This mapping consists of placing a 0 in the
most significant bit of the address,
transferring the four operation code bits,
and clearing the two least significant bits
of the control address register
Mapping of Instruction
Microprogram Example

Computer instruction format

15 14 11 10 0
I Opcode Address

Four computer instructions

Symbol OP-code Description
ADD 0000 AC  AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC
EA is the effective address

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field
Microinstruction Format
• 1. The three fields F1, F2, and F3 specify microoperations
for the computer.
• The microoperations are subdivided into three fields of
three bits each.
• The three bits in each field are encoded to specify seven
distinct microoperations.
• This gives a total of 21 microoperations.
• 2. The CD field selects status bit conditions.
• 3. The BR field specifies the type of branch to be used.
• 4. The AD field contains a branch address. The address
field is seven bits wide, since the control memory has 128
= 27 words
Microinstruction Fields

F1 Microoperation Symbol F2 Microoperation Symbol

000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved
Microinstruction Fields
The CD (condition) field consists of two bits which are encoded to specify four status bit
conditions as listed in

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC
The BR (branch) field consists of two bits. It is used, in conjunction with the
address field AD, to choose the address of the next microinstruction shown in
Table
BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Symbolic Microinstruction

 Sample Format Label: Micro-ops CD BR AD

 Label may be empty or may specify symbolic address

terminated with colon

 Micro-ops consists of 1, 2, or 3 symbols separated by commas

 CD one of {U, I, S, Z}
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

 BR one of {JMP, CALL, RET, MAP}

 AD one of {Symbolic address, NEXT, empty}

Fetch Routine
 Fetch routine
- Read instruction from memory
- Decode instruction and update PC
Microinstructions for fetch routine:
AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for fetch routine:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary microporgram for fetch routine:

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000
Symbolic Microprogram
• Control memory: 128 20-bit words
• First 64 words: Routines for 16 machine instructions
• Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH
ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
Binary Microprogram
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000
Design of Control Unit

microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

76 54 321 0 7 6 54 3 21 0 76 54 321 0

AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR
Microprogram Sequencer

External
(MAP)

L
I 3 2 1 0
Input Load
0I S1 MUX1 SBR
logic
T
1 S0

1 Incrementer
I Test
S MUX2
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...
 Input Logic for Microprogram
Sequencer

1 L L(load SBR with PC)

From I MUX2 Test
CPU SZ T Input for subroutine Call
Select BR field I0 logic
of CS I1
S0 for next address
S1 selection
CD Field of CS

Input Logic
I1I0=BR I1I0T Meaning Source of Address S1S0 L

000 In-Line CAR+1 00 0

001 JMP CS(AD) 01 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 01 1
10x RET SBR 10 0
11x MAP DR(11-14) 11 0

S1 = I1
S0 = I0I1 + I1’T
L = I1’I0T
• The block diagram of the microprogram sequencer is
shown in figure .
• There are two multiplexers in the circuit.
• The first multiplexer selects an address from one of four
sources and routes it into a control address register CAR.
• The second multiplexer tests the value of a selected status bit
and the result of the test is applied to an input logic circuit.
• The output from CAR provides the address for the control
memory.
• The content of CAR is incremented and applied to one of
the multiplexer inputs and to the subroutine registers
SBR.
• The other three inputs to multiplexer 1 come from the address
field of the present microinstruction, from the output of SBR,
and from an external source that maps the instruction.
• The CD (condition) field of the microinstruction selects one of the
status bits in the second multiplexer.
• If the bit selected is equal to 1, the T (test) variable is equal to 1;
otherwise, it is equal to 0.
• The T value together with the two bits from the BR (branch) field
goes to an input logic circuit.
• The input logic in a particular sequencer will determine the type
of operations that are available in the unit.
• Typical sequencer operations are: increment, branch or jump, call
and return from
• subroutine, load an external address, push or pop the stack, and
•other address sequencing operations.
With three inputs, the sequencer can provide up to eight
•address sequencing operations.
Some commercial sequencers have three or four inputs in
addition to the T input and thus provide a wider range of
operations.
 Microprogram Example

MUX
10 0
Computer AR
Address Memory
Configuration 2048 x 16
10 0
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC
Computer hardware configuration
• The block diagram of the computer is shown in Figure. It
consists of
• 1. Two memory units:
• Main memory -> for storing instructions and data, and
• Control memory -> for storing the microprogram.
• 2. Six Registers:
• Processor unit register: AC(accumulator),PC(Program
Counter), AR(Address Register), DR(Data Register)
• Control unit register: CAR (Control Address Register),
SBR(Subroutine Register)
• 3. Multiplexers:
• The transfer of information among the registers in the
processor is done through multiplexers rather than a
common bus.
• 4. ALU: The arithmetic, logic, and shift unit performs
microoperations with data from AC and DR and places the
result in AC.
Difference : Hardwired Control Unit &
Microprogrammed Control Unit
Hardwired Control Unit Microprogrammed Control Unit
Hardwired control unit Micrprogrammed control unit
generates the control signals generates the control signals with
needed for the processor using the help of micro instructions
logic circuits stored in control memory
Hardwired control unit is faster This is slower than the other as
when compared to micro instructions are used for
microprogrammed control unit generating signals here
as the required control signals
are generated with the help of
hardwares
Difficult to modify as the control Easy to modify as the modification
signals that need to be generated need to be done only at the instruction
are hard wired level
More costlier as everything has to Less costlier than hardwired control as
be realized in terms of logic gates only micro instructions are used for
generating control signals
Hardwired Control Unit Microprogrammed Control
Unit
It cannot handle complex instructions It can handle complex instructions
as the circuit design for it becomes
complex
Only limited number of instructions are Control signals for many instructions
used due to the hardware can be generated
implementation
Used in computer that makes use of Used in computer that makes use of
Reduced Instruction Set Complex Instruction Set
Computers(RISC) Computers(CISC)