Computer Organization &

Operating systems

By
NILOFER
(Assistant prof)
Dept. ECE, MRCET
 Unit-2
contents
MICRO PROGRAMMED CONTROL: Control Memory, Address Sequencing, Micro
program Examples, Design of Control Unit, Hard Wired Control, Micro programmed Control.

THE MEMORY SYSTEM: Basic Concepts of Semiconductor RAM Memories, Read-Only

Memories, Cache Memories Performance Considerations, Virtual Memories secondary Storage,
Introduction to RAID.
Introduction:
➢ The function of the control unit in a digital computer is to initiate sequence of micro
operations.
➢ Control unit can be implemented in two ways
• Hardwired control
• Micro programmed control

Hardwired Control:
➢ When the control signals are generated by hardware using conventional logic design
techniques, the control unit is said to be hardwired.
➢ The key characteristics are
o High speed of operation
o Expensive
o Relatively complex
o No flexibility of adding new instructions
➢ Examples of CPU with hardwired control unit are Intel 8085, Motorola 6802, Zilog 80, and
any RISC CPUs.
 Micro programmed Control:

➢ Control information is stored in control memory.

➢ Control memory is programmed to initiate the required sequence of micro-operations.
The key characteristics are
O Speed of operation is low when compared with hardwired
O Less complex
O Less expensive
O Flexibility to add new instructions
➢ Examples of CPU with micro programmed control unit are Intel 8080, Motorola 68000 and
any CISC CPUs.
1. Control Memory:
➢ The control function that specifies a micro operation is called as control variable.
➢ When control variable is in one binary state, the corresponding micro operation is
executed. For the other binary state the state of registers does not change.
➢ The active state of a control variable may be either 1 state or the 0 state, depending on the
application.
➢ For bus-organized systems the control signals that specify micro operations are groups of
bits that select the paths in multiplexers, decoders, and arithmetic logic units.
➢ Control Word: The control variables at any given time can be represented by a string of 1’s
and 0's called a control word.
➢ All control words can be programmed to perform various operations on the components of
the system.
➢ Micro program control unit: A control unit whose binary control variables are stored in
memory is called a micro program control unit.
➢ The control word in control memory contains within it a microinstruction.
➢ The microinstruction specifies one or more micro-operations for the system.
➢ A sequence of microinstructions constitutes a micro program.
➢ The control unit consists of control memory used to store the micro program.
➢ Control memory is a permanent i.e., read only memory (ROM).
➢ The general configuration of a micro-programmed control unit organization is shown as
block diagram in above slide
➢ The control memory is ROM so all control information is permanently stored.
➢ The control memory address register (CAR) specifies the address of the microinstruction and
the control data register (CDR) holds the microinstruction read from memory.
➢ The next address generator is sometimes called a micro program sequencer. It is used to
generate the next micro instruction address.
➢ The location of the next microinstruction may be the one next in sequence or it may be
located somewhere else in the control memory.
➢ So it is necessary to use some bits of the present microinstruction to control the generation
of the address of the microinstruction.
➢ Sometimes the next address may also be a function of external input conditions.
➢ The control data register holds the present microinstruction while next address is computed
and read from memory. The data register is times called a pipeline register.
➢ A computer with a micro programmed control unit will have two separate memories: a main
memory and a control memory.
➢ The micro program consists of microinstructions that specify various internal control signals
for execution of register micro operations
➢ These microinstructions generate the micro operations to:

• fetch the instruction from main memory

• evaluate the effective address
• execute the operation
• return control to the fetch phase for the next instruction
Micro program:
➢ Program stored in memory that generates all the control signals required to execute the
instruction set Correctly. Consists of micro instructions

➢ It Contains a control word and a sequencing word

Control Word: All the control information required for one clock cycle

Sequencing Word: Information needed to decide the next microinstruction address.

Control Memory:

Control Memory(Control Storage: CS) Storage in the micro programmed control unit to store the
micro program.

Writeable Control Memory(Writeable Control Storage :WCS) CS whose contents can be

modified, Allows the micro program can be changed, Instruction set can be changed or
modified.
Address Sequencing:

➢ Microinstructions are stored in control memory in groups, with each group specifying a
routine.
➢ Each computer instruction has its own micro program routine to generate the micro
operations.
➢ The hardware that controls the address sequencing of the control memory must be capable
of sequencing the microinstructions within a routine and be able to branch from one routine
to another
➢ Steps the control must undergo during the execution of a single computer instruction:

▪ Load an initial address into the CAR when power is turned on in the computer. This
address is usually the address of the first microinstruction that activates the
instruction fetch routine –IR holds instruction .
▪ The control memory then goes through the routine to determine the effective
address of the operand –AR holds operand address .
▪ The next step is to generate the micro operations that execute the instruction by
considering the opcode and applying a mapping process.
• The transformation of the instruction code bits to an address in control
memory where the routine of instruction located is referred to as
mapping process
▪ After execution, control must return to the fetch routine by executing an
unconditional branch
 In brief the address sequencing capabilities required in a control memory are:
➢ Incrementing of the control address register.
➢ Unconditional branch or conditional branch, depending on status bit conditions.
➢ A mapping process from the bits of the instruction to an address for control memory.
➢ A facility for subroutine call and return.

The block diagram of a control memory and the associated hardware needed for selecting the
next microinstruction address.
➢ The microinstruction in control memory contains a set of bits to initiate micro
operations in computer registers and other bits to specify the method by which the
next address is obtained.
➢ In the figure four different paths form which the control address register (CAR)
receives the address.
• The incrementer increments the content of the control register address register by one, to
select the next microinstruction in sequence.
• Branching is achieved by specifying the branch address in one of the fields of the
microinstruction.
• Conditional branching is obtained by using part of the microinstruction to select a specific
status bit in order to determine its condition.
• An external address is transferred into control memory via a mapping logic circuit.
• The return address for a subroutine is stored in a special register, that value is used when the
mico program wishes to return from the subroutine
Conditional Branching:

➢ Conditional branching is obtained by using part of the microinstruction to select a specific

status bit in order to determine its condition.
➢ The status conditions are special bits in the system that provide parameter information
such as the carry-out of an adder, the sign bit of a number, the mode bits of an
instruction, and i/o status conditions.
➢ The status bits, together with the field in the microinstruction that specifies a branch
address, control the branch logic.
➢ The branch logic tests the condition, if met then branches, otherwise, increments the
CAR.
➢ If there are 8 status bit conditions, then 3 bits in the microinstruction are used to specify
the condition and provide the selection variables for the multiplexer.
➢ For unconditional branching, fix the value of one status bit to be one load the branch
address from control memory into the CAR

Conditions to Test: O(overflow), N(negative),Z(zero), C(carry), etc.

Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
 MAPPING OF INSTRUCTIONS
Direct Mapping

OP-codes of Instructions
address
0000 ADD Routine
ADD 0000
AND 0001 0001 AND Routine
LDA 0010
STA 0011
BUN LDA Routine
0100 0010

Mapping 0011 STA Routine

10 xxxx 010
Bits
0100 BUN Routine
10 0000 010 ADD routine
10 0001 010 AND routine Control
Storage
10 0010 010 LDA routine
10 0011 010 STA routine
10 0100 010 BUN routine
Mapping function implemented by ROM or PLA

OP-code

Mapping memory
(ROM or PLA)

Control address
register

Control Memory
Subroutines:

➢ Subroutines are programs that are used by other routines to accomplish a particular task
and can be called from any point within the main body of the micro program.
➢ Frequently many micro programs contain identical section of code.
➢ Microinstructions can be saved by employing subroutines that use common sections of
microcode.
➢ Micro programs that use subroutines must have a provision for storing the return
address during a subroutine call and restoring the address during a subroutine return.
➢ A subroutine register is used as the source and destination for the addresses
MICROPROGRAM EXAMPLE ➢ The process of code generation for the
control memory is called
microprogramming.
➢ The block diagram of the computer
configuration is shown in figure
➢ Two memory units:
▪ Main memory –stores instructions
and data
▪ Control memory –stores micro
program
➢ Four processor registers
▪ Program counter –PC
▪ Address register –AR
▪ Data register –DR
▪ Accumulator register -AC
➢ Two control unit registers
Control address register –CAR .
Subroutine register –SBR

➢ Transfer of information among registers in the processor is through MUXs rather

than a bus.
 MACHINE INSTRUCTION FORMAT
Instruction: groups of bits in form of 0’s and 1’s
examples: 01010000, 100101010 ADD a, b
➢ Address of a, b is obtained
➢ Opcode of add is obtained
Instruction format: instructions are divided into 3 parts
➢ Type of addressing mode
1) Address
2) Opcode 15 14 11 10 0
3) Addressing mode
I OPCODE ADDRESS

ADDRESSING MODE
Sample machine instructions EA-effective address
Symbol opcode description

ADD 0000 AC  AC + M[EA]

BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC
 Microinstruction Format

F1, F2, F3: Micro operation fields

F1 F2 F3 CD BR AD CD: Condition for branching
BR: Branch field
3 3 3 2 2 7 AD: Address field

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC AC + DR ADD 001 AC AC - DR SUB
010 AC 0 CLRAC 010 AC AC v DR OR
011 AC AC + 1 INCAC 011 AC AC ^ DR AND
100 AC DRDRTAC 100 DR M[AR] READ
101 AR DR(0-10) DRTAR 101 DR AC ACTDR
110 AR PC PCTAR 110 DR DR + 1 INCDR
111 M[AR] DR WRITE 111 DR(0-10) PC PCTDR
 F3 MicrooperationSymbol
000 None NOP
001 AC  AC  DRXOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC
BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
SYMBOLIC MICROINSTRUCTIONS
Each line of an assembly language micro program defines a symbolic microinstruction and is
divided into five parts

A symbolic micr oprogram can be translated into its binary equivalent by a micro program
assembler.

Sample Format
five fields: label; micro-ops; CD; BR; AD

Label: may be empty or may specify a symbolic

address terminated with a colon

Micro-ops: consists of one, two, or three symbols

separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

 The symbol ORG defines the first address of a microprogram routine.
Fetch Routine: ORG 64 – places first microinstruction at control memory 1000000.
➢ The control memory has 128 locations, each one is 20 bits.
➢ The first 64 locations are occupied by the routines for the 16 instructions, addresses 0-63.
➢ Can start the fetch routine at address 64.
➢ The fetch routine requires the following three microinstructions (locations 64-66).
➢ The microinstructions needed for fetch routine are:
SYMBOLIC MICROPROGRAM
DESIGN OF CONTROL UNIT

- DECODING ALU CONTROL INFORMATION

MICROPROGRAM PROGRAMMED CONTROL
MUX-1 selects an address
from one of four sources
and routes it into a CAR

- In-Line Sequencing
→ CAR + 1
- Branch, Subroutine
Call → CS(AD)
- Return from
Subroutine → Output of
SBR
- New Machine
instruction → MAP
 HORIZONTAL AND VERTICAL MICROINSTRUCTION

In the micro-program control unit all the control signals associated with micro-operations are
Stored in memory called control memory.

Set of control signals that cause micro operation to occur is called micro-instructions

Micro-programmed control unit can be classified into two types based on the type of Control
Word stored in the Control Memory, viz.,
➢ Horizontal micro-programmed control unit
➢ Vertical micro-programmed control unit.

In Horizontal micro-programmed control unit, the control signals are represented in the
decoded binary format, i.e., 1 bit/CS. Here ‘n’ control signals require n bit encoding. On the
other hand.

In Vertical micro-programmed control unit, the control signals are represented in the encoded
binary format. Here ‘n’ control signals require log2n bit encoding.
In Horizontal micro-programmed control unit, the control signals are represented in the
decoded binary format, i.e., 1 bit/CS. Here ‘n’ control signals require n bit encoding. On the
other hand.

EXAMPLE: 16 bits are required for 16 control signals

Control signals . . ……. next address field

16 15 14 13 …………………………… 0

In Vertical micro-programmed control unit, the control signals are represented in the encoded
binary format. Here ‘n’ control signals require log2n bit encoding.

EXAMPLE: if 16 control signals are needed in a system then 4 bits are required
then 𝐥𝐨𝐠 𝟐 𝟏𝟔= 𝐥𝐨𝐠 𝟐 𝟐𝟒 = 4 𝐥𝐨𝐠 𝟐 𝟐= 4bits
next address field

3 0

Decoder 4x16

16 0
Horizontal micro instructions Vertical micro instructions

Lengthy instructions shorter instructions

Degree of parallelism is high Degree of parallelism is low

No external hardware required external hardware required

To generate control signal To generate control signal

Faster instruction execution slower instruction execution

Requires large control memory space requires less memory control space
 UNIT-2 PART B
• Memory Hierarchy

• Main Memory

• Auxiliary Memory

• Associative Memory

• Cache Memory

• Virtual Memory

• Memory Management Hardware

 ASSOCIATIVE MEMORY

➢ An associative memory can be considered as a memory unit whose stored data

can be identified for access by the content of the data itself rather than by an
address or memory location.

➢ Associative memory is often referred to as Content Addressable Memory (CAM).

➢ When a write operation is performed on associative memory, no address or

memory location is given to the word. The memory itself is capable of finding an
empty unused location to store the word.

➢ On the other hand, when the word is to be read from an associative memory, the
content of the word, or part of the word, is specified. The words which match the
specified content are located by the memory and are marked for reading.
 ➢ The words which are kept
in the memory are
compared in parallel with
the content of the
argument register.

➢ The key register (K)

provides a mask for
choosing a particular field
or key in the argument
word.

➢ If the key register contains

a binary value of all 1's,
then the entire argument is
compared with each
memory word. Otherwise,
only those bits in the
argument that have 1's in
their corresponding
➢ Thus, the key provides a mask for identifying a piece of position of the key register
information which specifies how the reference to are compared.
memory is made.
 relation between the memory array and the external registers in an associative memory.
The cells present inside the
memory array are marked
by the letter C with two
subscripts. The first
subscript gives the word
number and the second
specifies the bit position in
the word. For instance, the
cell Cij is the cell for bit j in
word i.
A bit Aj in the argument
register is compared with all
the bits in column j of the
array provided that Kj = 1.
This process is done for all
columns j = 1, 2, 3......, n.
If a match occurs between
all the unmasked bits of the
argument and the bits in
If one or more unmasked bits of the argument and the word word i, the corresponding
do not match, Mi is cleared to 0. bit Mi in the match register
is set to 1.
 Matching process

Internal organization of a typical cell Cij

We now include the key bit Kj in the comparison logic. The requirement is that
if Kj= 0, the corresponding bits of Aj and Fij need no comparison. Only when
Kj= 1 must they be compared. This requirement is achieved by ORing each
term with Kj‘
 READ OPERATION

If more than one word in memory matches the unmasked argument field, all the matched words
will have 1‘s in the corresponding bit position of the catch register. It is then necessary to scan
the bits of the match register on eat time. The matched words are read in sequence by applying
a read signal to each word line whose corresponding Mi bit is a 1

WRITE OPERATION
if unwanted words have to be deleted and new words inserted one at a time, there is a need for
a special register to distinguish between active and inactive words. This register, sometimes
called a tag register, would have as many bits as there are words in the memory. For every active
word stored in memory, the corresponding bit in the tag register is set to 1. A word is deleted
from memory by clearing its tag bit to 0.
 Cache Memory
➢ The data or contents of the main memory that are used frequently by CPU are
stored in the cache memory so that the processor can easily access that data in a
shorter time.
➢ Whenever the CPU needs to access memory, it first checks the cache memory. If
the data is not found in cache memory, then the CPU moves into the main
memory.

Cache memory is placed between the CPU and the main memory. The block diagram for a
cache memory can be represented as:
 Performance of Cache Memory System:
.
➢ The performance of the cache memory is frequently measured in terms of a
quantity called hit ratio.
➢ When the CPU refers to memory and finds the word in cache, it is said to produce a
hit.
➢ If the word is not found in the cache, it is in main memory and it counts as a miss.
➢ The ratio of the number of hits divided by the total CPU references to memory (hits
plus misses) is the hit ratio.
Performance of Cache Memory System

Hit Ratio - % of memory accesses satisfied by Cache memory system

Te: Effective memory access time in Cache memory system
Tc: Cache access time
Tm: Main memory access time

Te = Tc + (1 - h) Tm

Example: Tc = 0.4 s, Tm = 1.2s, h = 0.85%

Te = 0.4 + (1 - 0.85) * 1.2 = 0.58s
 Mapping Techniques
Cache Mapping-
Cache mapping is a technique by which the contents of main memory are brought into the
cache memory.

➢ Main memory is divided into equal size partitions called as blocks or frames.
➢ Cache memory is divided into partitions having same size as that of blocks called as lines.
➢ During cache mapping, block of main memory is simply copied to the cache and the block
is not actually brought from the main memory.

Cache mapping is performed using

following three different techniques-

1. Direct Mapping
2. Associative Mapping
3. Set Associative Mapping
1. Direct Mapping-
In direct mapping,
➢ A particular block of main memory can map only to a particular line of the cache.
➢ The line number of cache to which a particular block can map is given by-

Cache line number

= ( Main Memory Block Address ) Modulo (Number of lines in Cache)

Example-

• Consider cache memory is divided into ‘n’ number of lines.

• Then, block ‘j’ of main memory can map to line number (j mod n) only of the cache.
Need of Replacement Algorithm-

In direct mapping,
• There is no need of any replacement algorithm.
• This is because a main memory block can map only to a particular line of the cache.
• Thus, the new incoming block will always replace the existing block (if any) in that
particular line.

Division of Physical Address-

In direct mapping, the physical address is divided as-

2. Fully Associative Mapping-
In fully associative mapping,
➢ A block of main memory can map to any line of the cache that is freely available at
that moment.
➢ This makes fully associative mapping more flexible than direct mapping.
Example-

Consider the following scenario-

Here,
• All the lines of cache are
freely available.
• Thus, any block of main
memory can map to any
line of the cache.
• Had all the cache lines
been occupied, then one
of the existing blocks will
have to be replaced.
Need of Replacement Algorithm-

In fully associative mapping,

➢ A replacement algorithm is required.
➢ Replacement algorithm suggests the block to be replaced if all the cache lines are
occupied.
➢ Thus, replacement algorithm like FCFS Algorithm, LRU(least recently used), etc is
employed.

Division of Physical Address-

In fully associative mapping, the physical address is divided as-
3. Set Associative Mapping-

In k-way set associative mapping,

➢ Cache lines are grouped into sets where each set contains k number of lines.
➢ A particular block of main memory can map to only one particular set of the cache.
➢ However, within that set, the memory block can map any cache line that is freely
available.
➢ The set of the cache to which a particular block of the main memory can map is
given by-

Cache set number

= ( Main Memory Block Address ) Modulo (Number of sets in Cache)
Here,
• k = 2 suggests that each set contains two cache lines.
• Since cache contains 6 lines, so number of sets in the cache = 6 / 2 = 3 sets.
• Block ‘j’ of main memory can map to set number (j mod 3) only of the cache.
• Within that set, block ‘j’ can map to any cache line that is freely available at that
moment.
• If all the cache lines are occupied, then one of the existing blocks will have to be
replaced.
Need of Replacement Algorithm-

➢ Set associative mapping is a combination of direct mapping and fully associative

mapping.
➢ It uses fully associative mapping within each set.
➢ Thus, set associative mapping requires a replacement algorithm.

Division of Physical Address-

In set associative mapping, the physical address is divided as-

Special Cases-
If k = 1, then k-way set associative mapping becomes direct mapping i.e

1-way Set Associative Mapping ≡ Direct Mapping

 VIRTUAL MEMORY
Give the programmer the illusion that the system has a very large memory, even
though the computer actually has a relatively small main memory
Address Space(Logical) and Memory Space(Physical)

address generated by programs actual main memory address

ADDRESS MAPPING USING PAGES
ASSOCIATIVE MEMORY PAGE TABLE Each entry in the associative memory array
consists of two fields.
1. The first three bits specify a field from
storing the page number.
2. The last two bits constitute a field for
storing the block number.

➢ The virtual address is placed in the argument

register.
➢ The page number bits in the argument are
compared with all page numbers in the page
field of the associative memory.

If the page number is found, the 5-bit word is read out from memory. The corresponding block
number, being in the same word, is transferred to the main memory address register. If no
match occurs, a call to the operating system is generated to bring the required page from
auxiliary memory.
PAGE FAULT: if page is not available in memory the it is said to be page fault

PAGE REPLACEMENT
Decision on which page to displace to make room for an incoming page when no free frame is
available

The policy for choosing pages to remove is determined from the replacement algorithm that is
used.

Three of the most common replacement algorithms used are

1. First-in first-out (FIFO) .
2. Least recently used (LRU).
3. Optimal replacement( OPT)
FIFO: in this algorithm, a queue is maintained. The page which is assigned the frame first will
be replaced first. In other words, the page which resides at the rare end of the queue will be
replaced on the every page fault.
Least Recently Used –
In this algorithm page will be replaced which is least recently used.

Example-Consider the page reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2 with 4 page

frames. Find number of page faults.
Optimal Page replacement –
In this algorithm, pages are replaced which would not be used for the longest duration of time
in the future.

Example: Consider the page references 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, with 4 page frame. Find

number of page fault.
 MEMORY MANAGEMENT HARDWARE

A hardware device or circuit that supports virtual memory and paging by translating virtual
addresses into physical addresses.

SEGMENTATION:
- A segment is a set of logically related instructions
or data elements associated with a given name
- Variable size

User's view of memory

The user does not think of

memory as a linear array
of words. Rather the user
prefers to view memory as
a collection of variable
sized segments, with no
necessary ordering among
segments.
- A memory management scheme which supports
user's view of memory
- A logical address space is a collection of segments
- Each segment has a name and a length
- Address specify both the segment name and the
offset within the segment.
- For simplicity of implementations, segments are numbered

SEGMENTATION EXAMPLE
- A memory management scheme which supports
user's view of memory
- A logical address space is a collection of segments
- Each segment has a name and a length
- Address specify both the segment name and the
offset within the segment.
- For simplicity of implementations, segments are numbered