UNIT-II

Part-1: MICROPROGRAMMED CONTROL

Contents:
 Control memory
 Address Sequencing
 Microprogram Example
 Design of Control Unit
Introduction:
 The function of the control unit in a digital computer is to initiate sequence of microoperations.
 Control unit can be implemented in two ways
o Hardwired control
o Microprogrammed control
Hardwired Control:

 When the control signals are generated by hardware using conventional logic design techniques, the control
unit is said to be hardwired. 
 The key characteristics are
oHigh speed of operation
oExpensive
oRelatively complex
oNo flexibility of adding new instructions
 Examples of CPU with hardwired control unit are Intel 8085, Motorola 6802, Zilog 80, and any RISC

CPUs. Microprogrammed Control:

 Control information is stored in control memory.

 Control memory is programmed to initiate the required sequence of micro-operations.
 The key characteristics are
o Speed of operation is low when compared with hardwired
oLess complex
oLess expensive
oFlexibility to add new instructions
 Examples of CPU with microprogrammed control unit are Intel 8080, Motorola 68000 and any CISC CPUs.
1. Control Memory:

 The control function that specifies a microoperation is called as control variable.

 When control variable is in one binary state, the corresponding microoperation is executed. For the other
binary state the state of registers does not change.
 The active state of a control variable may be either 1 state or the 0 state, depending on the application.
 For bus-organized systems the control signals that specify microoperations are groups of bits that select
the paths in multiplexers, decoders, and arithmetic logic units.
 Control Word: The control variables at any given time can be represented by a string of 1’s and 0's called a
control word.
 All control words can be programmed to perform various operations on the components of the system.
 Microprogram control unit: A control unit whose binary control variables are stored in memory is called a
microprogram control unit.
 The control word in control memory contains within it a microinstruction.
 The microinstruction specifies one or more micro-operations for the system.
 A sequence of microinstructions constitutes a microprogram.
 The control unit consists of control memory used to store the microprogram.
 Control memory is a permanent i.e., read only memory (ROM).
 The general configuration of a micro-programmed control unit organization is shown as block diagram below.
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  The control memory is ROM so all control information is permanently stored.
 The control memory address register (CAR) specifies the address of the microinstruction and the control data
register (CDR) holds the microinstruction read from memory.
 The next address generator is sometimes called a microprogram sequencer. It is used to generate the next
micro instruction address.
 The location of the next microinstruction may be the one next in sequence or it may be located somewhere
else in the control memory.
 So it is necessary to use some bits of the present microinstruction to control the generation of the address of
the microinstruction.
 Sometimes the next address may also be a function of external input conditions.
 The control data register holds the present microinstruction while next address is computed and read from
memory. The data register is times called a pipeline register.

 A computer with a microprogrammed control unit will have two separate memories: a main memory and a
control memory
 The microprogram consists of microinstructions that specify various internal control signals for execution of
register microoperations
 These microinstructions generate the microoperations to:
 fetch the instruction from main memory
 evaluate the effective address
 execute the operation
 return control to the fetch phase for the next instruction
2. Address Sequencing:
 Microinstructions are stored in control memory in groups, with each group specifying a routine.
 Each computer instruction has its own microprogram routine to generate the microoperations.
 The hardware that controls the address sequencing of the control memory must be capable of sequencing the
microinstructions within a routine and be able to branch from one routine to another
 Steps the control must undergo during the execution of a single computer instruction:
o Load an initial address into the CAR when power is turned on in the computer. This address is usually
the address of the first microinstruction that activates the instruction fetch routine – IR holds
instruction
o The control memory then goes through the routine to determine the effective address of the operand
– AR holds operand address
o The next step is to generate the microoperations that execute the instruction by considering the
opcode and applying a mapping process.
 The transformation of the instruction code bits to an address in control memory where the
routine of instruction located is referred to as mapping process.

o After execution, control must return to the fetch routine by executing an unconditional branch
 In brief the address sequencing capabilities required in a control memory are:
o Incrementing of the control address register.
o Unconditional branch or conditional branch, depending on status bit conditions.
o A mapping process from the bits of the instruction to an address for control memory.

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 o A facility for subroutine call and return.
 The below figure shows a block diagram of a control memory and the associated hardware needed for
selecting the next microinstruction address.

 The microinstruction in control memory contains a set of bits to initiate microoperations in computer registers
and other bits to specify the method by which the next address is obtained.
 In the figure four different paths form which the control address register (CAR) receives the address.
o The incrementer increments the content of the control register address register by one, to select the
next microinstruction in sequence.
o Branching is achieved by specifying the branch address in one of the fields of the microinstruction.
o Conditional branching is obtained by using part of the microinstruction to select a specific status bit in
order to determine its condition.
o An external address is transferred into control memory via a mapping logic circuit.
o The return address for a subroutine is stored in a special register, that value is used when the
micoprogram wishes to return from the subroutine.

Conditional Branching:

 Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order to
determine its condition.
 The status conditions are special bits in the system that provide parameter information such as the carry-out of
an adder, the sign bit of a number, the mode bits of an instruction, and i/o status conditions.
 The status bits, together with the field in the microinstruction that specifies a branch address, control the
branch logic.
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  The branch logic tests the condition, if met then branches, otherwise, increments the CAR.
 If there are 8 status bit conditions, then 3 bits in the microinstruction are used to specify the condition and
provide the selection variables for the multiplexer.
 For unconditional branching, fix the value of one status bit to be one load the branch address from control
memory into the CAR.

Mapping of Instruction:
 A special type of branch exists when a microinstruction specifies a branch to the first word in control memory
where a microprogram routine is located.
 The status bits for this type of branch are the bits in the opcode.
 Assume an opcode of four bits and a control memory of 128 locations. The mapping process converts the 4-bit
opcode to a 7-bit address for control memory shown in below figure.

 Mapping consists of placing a 0 in the most significant bit of the address, transferring the four
operation code bits, and clearing the two least significant bits of the control address register.
 This provides for each computer instruction a microprogram routine with a capacity of four microinstructions.

Subroutines:
 Subroutines are programs that are used by other routines to accomplish a particular task and can be called
from any point within the main body of the microprogram.
 Frequently many microprograms contain identical section of code.
 Microinstructions can be saved by employing subroutines that use common sections of microcode.
 Microprograms that use subroutines must have a provision for storing the return address during a subroutine
call and restoring the address during a subroutine return.
 A subroutine register is used as the source and destination for the addresses

3. Microprogram Example:

 The process of code generation for the control memory is called microprogramming.
 The block diagram of the computer configuration is shown in below figure.
 Two memory units:
 Main memory – stores instructions and data
 Control memory – stores microprogram
 Four processor registers
 Program counter – PC
 Address register – AR
 Data register – DR
 Accumulator register - AC
 Two control unit registers
 Control address register – CAR
 Subroutine register – SBR

 Transfer of information among registers in the processor is through MUXs rather than a bus.

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 The computer instruction format is shown in below figure.

 Three fields for an instruction:

 1-bit field for indirect addressing
 4-bit opcode
 11-bit address field

 The example will only consider the following 4 of the possible 16 memory instructions

 The microinstruction format for the control memory is shown in below figure.

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 The microinstruction format is composed of 20 bits with four parts to it
 Three fields F1, F2, and F3 specify microoperations for the computer [3 bits each]
 The CD field selects status bit conditions [2 bits]
 The BR field specifies the type of branch to be used [2 bits]
 The AD field contains a branch address [7 bits]
 Each of the three microoperation fields can specify one of seven possibilities.
 No more than three microoperations can be chosen for a microinstruction.
 If fewer than three are needed, the code 000 = NOP.
 The three bits in each field are encoded to specify seven distinct microoperations listed in below table.

 Five letters to specify a transfer-type microoperation

 First two designate the source register
 Third is a ‘T’
 Last two designate the destination register
AC ← DR F1 = 100 = DRTAC
 The condition field (CD) is two bits to specify four status bit conditions shown below

 The branch field (BR) consists of two bits and is used with the address field to choose the address of the
next microinstruction.

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 Each line of an assembly language microprogram defines a symbolic microinstruction and is divided into five
parts
1. The label field may be empty or it may specify a symbolic address. Terminate with a colon (: ).
2. The microoperations field consists of 1-3 symbols, separated by commas. Only one symbol from each
field. If NOP, then translated to 9 zeros
3. The condition field specifies one of the four conditions
4. The branch field has one of the four branch symbols
5. The address field has three formats
a. A symbolic address – must also be a label
b. The symbol NEXT to designate the next address in sequence
c. Empty if the branch field is RET or MAP and is converted to 7 zeros
 The symbol ORG defines the first address of a microprogram routine.
 ORG 64 – places first microinstruction at control memory 1000000.

Fetch Routine:
 The control memory has 128 locations, each one is 20 bits.
 The first 64 locations are occupied by the routines for the 16 instructions, addresses 0-63.
 Can start the fetch routine at address 64.
 The fetch routine requires the following three microinstructions (locations 64-66).
 The microinstructions needed for fetch routine are:

 It’s Symbolic microprogram:

 It’s Binary microprogram:

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4. Design of control Unit:

 The control memory out of each subfield must be decoded to provide the distinct microoperations.
 The outputs of the decoders are connected to the appropriate inputs in the processor unit.
 The below figure shows the three decoders and some of the connections that must be made from their
outputs.

 The three fields of the microinstruction in the output of control memory are decoded with a 3x8 decoder to
provide eight outputs.
 Each of the output must be connected to proper circuit to initiate the corresponding microoperation as
specified in previous topic.
 When F1 = 101 (binary 5), the next pulse transition transfers the content of DR (0-10) to AR.
 Similarly, when F1= 110 (binary 6) there is a transfer from PC to AR (symbolized by PCTAR). As
shown in Fig, outputs 5 and 6 of decoder F1 are connected to the load input of AR so that when
either one of these outputs is active, information from the multiplexers is transferred to AR.
 The multiplexers select the information from DR when output 5 is active and from PC when
output 5 is inactive.
 The transfer into AR occurs with a clock transition only when output 5 or output 6 of the decoder is
active.
 For the arithmetic logic shift unit the control signals are instead of coming from the logical gates,
now these inputs will now come from the outputs of AND, ADD and DRTAC respectively.
Microprogram Sequencer:

 The basic components of a microprogrammed control unit are the control memory and the circuits that select
the next address.
 The address selection part is called a microprogram sequencer.
 The purpose of a microprogram sequencer is to present an address to the control memory so that a
microinstruction may be read and executed.
 The next-address logic of the sequencer determines the specific address source to be loaded into the control
address register.
 The block diagram of the microprogram sequencer is shown in below figure.
 The control memory is included in the diagram to show the interaction between the sequencer and the
memory attached to it.
 There are two multiplexers in the circuit.
o The first multiplexer selects an address from one of four sources and routes it into control address
register CAR.
o The second multiplexer tests the value of a selected status bit and the result of the test is applied to an
input logic circuit.
 The output from CAR provides the address for the control memory.

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 The content of CAR is incremented and applied to one of the multiplexer inputs and to the subroutine register
SBR.
 The other three inputs to multiplexer come from
o The address field of the present microinstruction
o From the out of SBR
o From an external source that maps the instruction
 The CD (condition) field of the microinstruction selects one of the status bits in the second multiplexer.
 If the bit selected is equal to 1, the T variable is equal to 1; otherwise, it is equal to 0.
 The T value together with two bits from the BR (branch) field goes to an input logic circuit.
 The input logic in a particular sequencer will determine the type of operations that are available in the unit.

 The input logic circuit in above figure has three inputs I0, I1, and T, and three outputs, S0, S1, and L.
 Variables S0 and S1 select one of the source addresses for CAR. Variable L enables the load input in SBR.
 The binary values of the selection variables determine the path in the multiplexer.
 For example, with S1,S0 = 10, multiplexer input number 2 is selected and establishes transfer path from SBR to
CAR.
 The truth table for the input logic circuit is shown in Table below.

 Inputs I1 and I0 are identical to the bit values in the BR field.

 The bit values for S1 and S0 are determined from the stated function and the path in the multiplexer that
establishes the required transfer.
 The subroutine register is loaded with the incremented value of CAR during a call microinstruction (BR = 01)
provided that the status bit condition is satisfied (T = 1).
 The truth table can be used to obtain the simplified Boolean functions for the input logic circuit:
S1=I1
S0=I1I0+I’1
T L = I’1T I0

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 Part-II: Central Processing Unit

General Register Organization :

The Central Processing Unit (CPU) is called the brain of the computer that performs data-
processing operations. Figure below shows the three major parts of CPU.

Intermediate data is stored in the register set during the execution of the instructions. The micro
operations required for executing the instructions are performed by the arithmetic logic unit
whereas the control unit takes care of transfer of information among the registers and guides the
ALU. The control unit services the transfer of information among the registers and instructs the
ALU about which operation is to be performed. The computer instruction set is meant for
providing the specifications for the design of the CPU. The design of the CPU largely, involves
choosing the hardware for implementing the machine instructions.
The need for memory locations arises for storing pointers, counters, return address,
temporary results and partial products. Memory access consumes the most of the time off an
operation in a computer. It is more convenient and more efficient to store these intermediate values
in processor registers.

A common bus system is employed to contact registers that are included in the CPU in a
large number. Communications between registers is not only for direct data transfer but also for
performing various micro-operations. A bus organization for such CPU register shown in below
Figure, is connected to two multiplexers (MUX) to form two buses A and B. The selected lines in
each multiplexers select one register of the input data for the particular bus.

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·

OPERATION OF CONTROL UNIT:

The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus

Control Word

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Encoding of register selection fields

Encoding of ALU operations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word

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 Instruction Formats:
A computer performs a task based on the instruction provided. Instruction in computers comprises groups
called fields. These fields contain different information as for computers everything is in 0 and 1 so each field
has different significance based on which a CPU decides what to perform. The most common fields are:
 Operation field specifies the operation to be performed like addition.
 Address field which contains the location of the operand, i.e., register or memory location.
 Mode field which specifies how operand is to be founded.
Instruction is of variable length depending upon the number of addresses it contains. Generally, CPU
organization is of three types based on the number of address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
In the first organization, the operation is done involving a special register called the accumulator. In second on
multiple registers are used for the computation purpose. In the third organization the work on stack basis
operation due to which it does not contain any address field. Only a single organization doesn’t need to be
applied, a blend of various organizations is mostly what we see generally.
Based on the number of address, instructions are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions –

A stack-based computer does not use the address field in the instruction. To evaluate an expression first it is
converted to reverse Polish Notation i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X= AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP ← A

PUSH B TOP ← B

ADD TOP ← A+B

PUSH C TOP ← C

PUSH D TOP ← D

ADD TOP ← C+D

MUL TOP ← (C+D)*(A+B)

POP X M[X] ← TOP

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2 .One Address Instructions –
This uses an implied ACCUMULATOR register for data manipulation. One operand is in the accumulator and
the other is in the register or memory location. Implied means that the CPU already knows that one operand is
in the accumulator so there is no need to specify it.
Expression: X= (A+B)*(C+D)
AC is accumulator
M[X] is any memory location
M[T] is temporary location

LOAD A AC ← M[A]

ADD B AC ← AC + M[B]

STORE T M[T] ← AC

LOAD C AC ← M[C]

ADD D AC ← AC + M[D]

MUL T AC ← AC * M[T]

STORE X M[X] ← AC

3.Two Address Instructions –

This is common in commercial computers. Here two addresses can be specified in the instruction. Unlike earlier
in one address instruction, the result was stored in the accumulator, here the result can be stored at different
locations rather than just accumulators, but require more number of bit to represent address.
Here destination address can also contain operand.
Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[X] is any memory location

MOV R1, A R1 ← M[A]

ADD R1, B R1← R1 + M[B]

MOV R2, C R2 ← M[C]

ADD R2, D R2 ← R2 + M[D]

MUL R1, R2 R1 ← R1 * R2

MOV X, R1 M[X] ← R1

4.Three Address Instructions –

This has three address field to specify a register or a memory location. Program created are much short in size
but number of bits per instruction increase. These instructions make creation of program much easier but it does
not mean that program will run much faster because now instruction only contain more information but each
micro operation (changing content of register, loading address in address bus etc.) will be performed in one
cycle only.
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Expression: X= (A+B)*(C+D)
R1, R2 are registers
M[X] is any memory location

ADD R1, A, B R1 ← M[A] + M[B]

ADD R2, C, D R2 ← M[C] + M[D]

MUL X, R1, R2 M[X] ← R1 * R2

5.RISC Instructions
The instruction set of a typical RISC(Reduced Instruction Set Computer) processor is restricted to the use of
load and store instructions when communicating between memory and CPU.
Expression: X= (A+B)*(C+D)
R1, R2,R3,R4 are registers
M[X] is any memory location

LOAD R1,A R1 ← M[A]

LOAD R2,B R2 ← M[B]

LOAD R3,C R3 ← M[C]

LOAD R4,D R4 ← M[D]

ADD R1,R1,R2 R1 ← R1 + R2

ADD R3,R3,R4 R3 ← R3 + R4

MUL R1, R1, R3 R1← R1 * R3

STORE X R1 M[X] ← R1

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 ADDRESSING MODES :
* Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is
actually referenced)

* Variety of addressing modes

- to give programming flexibility to the user
- to use the bits in the address field of the
instruction efficiently
-
Types Of Addressing Modes:
Various types of addressing modes are:
1.Implied Mode
2.Immediate Addressing Modes
3.Direct Addressing Modes
4.Indirect Addressing Modes
5.Register Mode
6.Register Indirect Addressing Mode
7. Indexed Addressing Mode
8.Auto-Increment and Auto-Decrement Addressing Modes
Implied Mode − In this mode, the operands are specified implicitly in the definition of the instruction. For example, the
instruction "complement accumulator" is an implied-mode instruction because the operand in the accumulator register is
implied in the definition of the instruction. All register reference instructions that use an accumulator are implied-mode
instructions.

Instruction format with mode field

Opcode Mode Address

Immediate Mode − In this mode, the operand is specified in the instruction itself. In other words, an immediate-mode
instruction has an operand field instead of an address field. The operand field includes the actual operand to be used in
conjunction with the operation determined in the instruction. Immediate-mode instructions are beneficial for initializing
registers to a constant value.
Register Mode − In this mode, the operands are in registers that reside within the CPU. The specific register is selected
from a register field in the instruction. A k-bit field can determine any one of the 2k registers.
Register Indirect Mode − In this mode, the instruction defines a register in the CPU whose contents provide the address
of the operand in memory. In other words, the selected register includes the address of the operand rather than the
operand itself.
A reference to the register is then equivalent to specifying a memory address. The advantage of a register indirect mode
instruction is that the address field of the instruction uses fewer bits to select a register than would have been required to
specify a memory address directly.
Autoincrement or Autodecrement Mode &minuend; This is similar to the register indirect mode except that the register
is incremented or decremented after (or before) its value is used to access memory. When the address stored in the
register defines a table of data in memory, it is necessary to increment or decrement the register after every access to the
table. This can be obtained by using the increment or decrement instruction.
Direct Address Mode − In this mode, the effective address is equal to the address part of the instruction. The operand
resides in memory and its address is given directly by the address field of the instruction. In a branch-type instruction, the
address field specifies the actual branch address.

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Indirect Address Mode − In this mode, the address field of the instruction gives the address where the effective address
is stored in memory. Control fetches the instruction from memory and uses its address part to access memory again to
read the effective address.
Indexed Addressing Mode − In this mode, the content of an index register is added to the address part of the instruction
to obtain the effective address. The index register is a special CPU register that contains an index value. The address
field of the instruction defines the beginning address of a data array in memory.

Numerical Example:

 To show the differences between the various modes, we will show the effect of the addressing modes on the
instruction defined in Fig. 7.

 The two-word instruction at address 200 and 201 is a "load to AC" instruction with an address field equal to 500.

 The first word of the instruction specifies the operation code and mode, and the second word specifies the
address part.

 PC has the value 200 for fetching this instruction. The content of processor register R1 is 400, and the content of
an index register XR is 100.
 AC receives the operand after the instruction is executed. The figure lists a few pertinent addresses and shows
the memory content at each of these addresses.

 The mode field of the instruction can specify any one of a number of modes. For each possible mode we
calculate the effective address and the operand that must be loaded into AC.
 In the direct address mode the effective address is the address part of the instruction 500 and the operand to be
loaded into AC is 800. In the immediate mode the second word of the instruction is taken as the operand rather
than an address, so 500 is loaded into AC. (The effective address in this case is 201 .)
 In the indirect mode the effective address is stored in memory at address 500. Therefore, the effective address is
800 and the operand is 300. In the relative mode the effective address is 500 + 202 = 702 and the operand is
325.
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  (Note that the value in PC after the fetch phase and during the execute phase is 202.) In the index mode the
effective address is XR + 500 = 100 + 500 = 600 and the operand is 900. In the register mode the operand is in
R1 and 400 is loaded into AC.
 (There is no effective address in this case.) In the register indirect mode the effective address is 400, equal to the
content of R1 and the operand loaded into AC is 700.
 The autoincrement mode is the same as the register indirect mode except that R1 is incremented to 401 after the
execution of the instruction. The autodecrement mode decrements R1 to 399 prior to the execution of the
instruction.
 The operand loaded into AC is now 450. Table 4 lists the values of the effective address and the operand loaded
into AC for the nine addressing modes.

Data Transfer and Manipulation:

• Instruction set of different computers differ from each other mostly in way the operands are determined from the
address and mode fields.
Most computer instructions can be classified into three categories :
 Data Transfer Instructions
 Data Manipulation Instruction
 Program Control Instructions

Data Transfer Instructions

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Table : Typical Data Transfer Instructions

Data Manipulation Instructions :

Data manipulation instructions perform operations on data and provide the computational capabilities for the computer.
The data manipulation instructions in a typical computer usually divided into three basic types as follows.
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
Let’s discuss one by one.
1. Arithmetic instructions :
The four basic arithmetic operations are addition, subtraction, multiplication, and division. Most computers provide
instructions for all four operations.

Typical Arithmetic Instructions –

Name MnemonicExample Explanation
It will increment the register B by 1
B<-B+1
Increment INC INC B

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 It will decrement the register B by 1
B<-B-1
Decrement DEC DEC B

It will add contents of register B to the contents

of the accumulator
and store the result in the accumulator
AC<-AC+B

Add ADD ADD B

It will subtract the contents of register B from the

contents of the
accumulator and store the result in the
accumulator
AC<-AC-B
Subtract SUB SUB B

It will multiply the contents of register B with the

contents of the
accumulator and store the result in the
accumulator
AC<-AC*B
Multiply MUL MUL B

It will divide the contents of register B with the

contents of the
accumulator and store the quotient in the
accumulator
AC<-AC/B
Divide DIV DIV B

It will add the contents of register B and the

carry flag with the

contents of the accumulator and store the result

in the
accumulator
ADDC
AC<-AC+B+Carry flag
Add with carry ADDC B

It will subtract the contents of register B and the

carry flag from
the contents of the accumulator and store the
result in the
accumulator
Subtract with
AC<-AC-B-Carry flag
borrow SUBB SUBB B

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 It will negate a value by finding 2’s complement
of its single operand.
This means simply operand by -1.
Negate(2’s
B<-B’+1
complement) NEG NEG B
2. Logical and Bit Manipulation Instructions :
Logical instructions perform binary operations on strings of bits stored in registers. They are useful for manipulating
individual bits or a group of bits.
Typical Logical and Bit Manipulation Instructions –
Name MnemonicExample Explanation
It will set the accumulator to 0
AC<-0
Clear CLR CLR

It will complement the accumulator

COM
AC<-(AC)’
Complement COM A

It will AND the contents of register B with the contents of accumulator and
store
it in the accumulator
AC<-AC AND B
AND AND AND B

It will OR the contents of register B with the contents of accumulator and

store it

in the accumulator
AC<-AC OR B
OR OR OR B

It will XOR the contents of register B with the contents of the accumulator
and
store it in the accumulator
AC<-AC XOR B
Exclusive-OR XOR XOR B

It will set the carry flag to 0

Carry flag<-0
Clear carry CLRC CLRC

It will set the carry flag to 1

Carry flag<-1
Set carry SETC SETC

It will complement the carry flag

Complement Carry flag<- (Carry flag)’
carry COMC COMC

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 Enable interrupt EI EI It will enable the interrupt

Disable interrupt DI DI It will disable the interrupt

3. Shift Instructions :
Shifts are operations in which the bits of a word are moved to the left or right. Shift instructions may specify either
logical shifts, arithmetic shifts, or rotate-type operations.
Typical Shift Instructions –
Name Mnemonic

Logical shift right SHR

Logical shift left SHL

Arithmetic shift right SHRA

Arithmetic shift left SHLA

Rotate right ROR

Rotate left ROL

Rotate right through carry RORC

Rotate left through carry ROLC

PROGRAM CONTROL

Program control instructions specify conditions for altering the content of the program counter , while data transfer and
manipulation instructions specify condtions for data-processing operations.

NAME Mnemonic

Branch BR

Jump JMP

Skip SKP

Call CALL

Return RET

Compare(by subtraction) CMP

Test(by ANDing) TST

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Status Bit Conditions:

• It is convinent to supplement the ALU circuit in the CPU with a status register where status bit condition can be
stored for further analysis.
• Status bits are also called condition code bit or flag bit.
• The four status bits are symbolized by C,S,Z and V.
• The bits are set or cleared as a result of an operation performed in the ALU

4-bit status register:

Conditional Branch Instructions :

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Subroutine Call and Return:

 It is a self-contained sequence of instructions that performs a given computational task.

 During the execution of a program,a subroutine may call when it is called, a branch is executed to the beginning
of the subroutine to start executing its set of instructions. After the subroutine has been executed,a branch is
made back to the main program.
 A subroutine call is implemented with the following microoperations:

CALL:
SP← SP-1: Decrement stack point
M[SP] ←PC : Push content of PC onto the stack
PC←Effective Address : Transfer control to the subroutine

RETURN:
PC ← M[SP] : Pop stack and transfer to PC
SP ← SP+1 : Increment stack pointer

Program Interrupt:
» Transfer program control from a currently running program to another service program
as a result of an external or internal generated request
» Control returns to the original program after the service program is executed

Types of Interrupts:
1) External Interrupts
» come from I/O device, from a timing device, from a circuit
monitoring the power supply, or from any other external source
2) Internal Interrupts or TRAP
» caused by register overflow, attempt to divide by zero,
an invalid operation code, stack overflow, and protection violation
3) Software Interrupts
» initiated by executing an instruction (INT or RST)
» used by the programmer to initiate an interrupt procedure at any desired point in the program

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