KOREA-VIETNAM FRIENDSHIP IT COLLEGE

DIGITAL CIRCUITS

CHAPTER 2:
COMBINATIONAL LOGIC CIRCUITS

15 October 2006
OVERVIEW

 Binary logic and Gates

 Boolean Algebra
 Standard and Canonical Forms
 Karnaugh Maps (K-Maps)
 K-Map Manipulation
 More Logic Gates
 NAND and NOR Gates
 Exclusive-OR (XOR) Gates
October 17, 2008 Chapter 2. Combinational Logic Circuits 2
BINARY LOGIC

 Deals with binary variables that take 2

discrete values (0 and 1), and with logic
operations
 Three basic logic operations:
 AND, OR, NOT
 Binary/logic variables are typically
represented as letters: A,B,C,…,X,Y,Z

October 17, 2008 Chapter 2. Combinational Logic Circuits 3

Binary Logic Function

F(vars) = expression

 Operators ( +, •, ’ )
 Variables
set of binary  Constants ( 0, 1 )
variables  Groupings (parenthesis)

Example: F(a,b) = a’•b + b’

G(x,y,z) = x•(y+z’)

October 17, 2008 Chapter 2. Combinational Logic Circuits 4

Basic Logic Operators

 AND (also • , Λ)
 OR (also + , V)
 NOT (also ’ , - )

 F(a,b) = a•b, reads F is 1 if and only if a=b=1

 G(a,b) = a+b,reads G is 1 if either a=1 or b=1
 H(a) = a’, reads H is 1 if a=0

October 17, 2008 Chapter 2. Combinational Logic Circuits 5

Basic Logic Operators (cont.)

 1-bit logic AND resembles binary

multiplication:
0 • 0 = 0, 0 • 1 = 0,
1 • 0 = 0, 1•1 =1
 1-bit logic OR resembles binary addition,
except for one operation:
0 + 0 = 0, 0 + 1 = 1,
1 + 0 = 1, 1 + 1 = 1 (≠ 102)

October 17, 2008 Chapter 2. Combinational Logic Circuits 6

Truth Tables for logic operators

Truth table: tabular form that uniguely

represents the relationship between the input
variables of a function and its output
2-Input AND 2-Input OR NOT
A B F=A•B A B F=A+B A F=A’
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
October 17, 2008 Chapter 2. Combinational Logic Circuits 7
Truth Tables (cont.)

 Q: Let a function F() depend on n

variables. How many rows are there in the
truth table of F() ?

 A: 2n rows, since there are 2n possible

binary patterns/combinations for the n
variables

October 17, 2008 Chapter 2. Combinational Logic Circuits 8

 Logic Gates

 Logic gates are abstractions of electronic

circuit components that operate on one or
more input signals to produce an output
signal.
2-Input AND 2-Input OR NOT (Inverter)
A A
F G A H
B B
F = A•B G = A+B H = A’
October 17, 2008 Chapter 2. Combinational Logic Circuits 9
 Timing Diagram

t0 t1 t2 t3 t4 t5 t6
1
Input A 0
1 Transitions
signals B
0

1
Gate F=A•B 0 Basic
Assumption:
1
Output G=A+B 0 Zero time for
Signals 1
signals to
H=A’ 0 propagate
Through gates
October 17, 2008 Chapter 2. Combinational Logic Circuits 10
Combinational Logic Circuit
from Logic Function
 Consider function F = A’ + B•C’ + A’•B’
 A combinational logic circuit can be constructed to
implement F, by appropriately connecting input signals
and logic gates:
 Circuit input signals  from function variables (A, B, C)
 Circuit output signal  function output (F)
 Logic gates  from logic operations

A F

October 17, 2008 Chapter 2. Combinational Logic Circuits 11

 Combinational Logic Circuit
from Logic Function (cont.)
 In order to design a cost-effective
and efficient circuit, we must A B C F G
minimize the circuit’s size (area) 0 0 0 1 1
and propagation delay (time
required for an input signal 0 0 1 1 1
change to be observed at the 0 1 0 1 1
output line)
0 1 1 1 1
 Observe the truth table of F=A’ +
B•C’ + A’•B’ and G=A’ + B•C’ 1 0 0 0 0
 Truth tables for F and G are 1 0 1 0 0
identical  same function 1 1 0 1 1
 Use G to implement the logic
1 1 1 0 0
circuit (less components)
October 17, 2008 Chapter 2. Combinational Logic Circuits 12
Combinational Logic Circuit
from Logic Function (cont.)
C

A F

B G

A
October 17, 2008 Chapter 2. Combinational Logic Circuits 13
BOOLEAN ALGEBRA

 VERY nice machinery used to manipulate

(simplify) Boolean functions
 George Boole (1815-1864):
“An investigation of the laws of thought”
 Terminology:
 Literal: A variable or its complement
 Product term: literals connected by •
 Sum term: literals connected by +

October 17, 2008 Chapter 2. Combinational Logic Circuits 14

Boolean Algebra Properties

Let X: boolean variable, 0,1: constants

 X+0=X -- Zero Axiom

 X•1 =X -- Unit Axiom
 X+1 =1 -- Unit Property
 X•0 =0 -- Zero Property

October 17, 2008 Chapter 2. Combinational Logic Circuits 15

Boolean Algebra Properties (cont.)

Let X: boolean variable, 0,1: constants

3. X+X = X -- Idepotence
4. X•X = X -- Idepotence
5. X + X’ = 1 -- Complement
6. X • X’ = 0 -- Complement
7. (X’)’ = X -- Involution

October 17, 2008 Chapter 2. Combinational Logic Circuits 16

The Duality Principle

 The dual of an expression is obtained by

exchanging (• and +), and (1 and 0) in it,
provided that the precedence of operations is
not changed.
 Cannot exchange x with x’
 Example:
 Find H(x,y,z), the dual of F(x,y,z) = x’yz’ + x’y’z
 H = (x’+y+z’) (x’+y’+ z)
 Dual does not always equal the original
expression
 If a Boolean equation/equality is valid, its dual
is also valid
October 17, 2008 Chapter 2. Combinational Logic Circuits 17
The Duality Principle (cont.)

With respect to duality, Identities 1 – 8 have

the following relationship:

1. X + 0 = X 2. X • 1 = X (dual of 1)
3. X + 1 = 1 4. X • 0 = 0 (dual of 3)
5. X + X = X 6. X • X = X (dual of 5)
7. X + X’ = 1 8. X • X’ = 0 (dual of 8)

October 17, 2008 Chapter 2. Combinational Logic Circuits 18

 More Boolean Algebra Properties

Let X, Y, and Z: boolean variables

10. X + Y = Y + X 11. X • Y = Y • X -- Commutative
12. X + (Y+Z) = (X+Y) + Z 13. X•(Y•Z) = (X•Y)•Z -- Associative
14. X•(Y+Z) = X•Y + X•Z 15. X+(Y•Z) = (X+Y) • (X+Z) -- Distributive
16. (X + Y)’ = X’ • Y’ 17. (X • Y)’ = X’ + Y’ -- DeMorgan’s

In general,
( X1 + X2 + … + Xn )’ = X1’•X2’ • … •Xn’,
and ( X1•X2•… •Xn )’ = X1’ + X2’ + … + Xn’

October 17, 2008 Chapter 2. Combinational Logic Circuits 19

Absorption Property (Covering)

1. x + x•y = x
2. x•(x+y) = x (dual)
 Proof:
x + x•y = x•1 + x•y
= x•(1+y)
= x•1
=x
QED (2 true by duality)

October 17, 2008 Chapter 2. Combinational Logic Circuits 20

Consensus Theorem

 xy + x’z + yz = xy + x’z
 (x+y)•(x’+z)•(y+z) = (x+y)•(x’+z) -- (dual)
 Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
QED (2 true by duality).

October 17, 2008 Chapter 2. Combinational Logic Circuits 21

Truth Tables (revisited)

 Enumerates all possible x y z F1 F2 F3

combinations of variable 0 0 0 0 1 1
values and the 0 0 1 0 0 1
corresponding function 0 1 0 0 0 1
value
0 1 1 0 1 1
 Truth tables for some
1 0 0 0 1 0
arbitrary functions
F1(x,y,z), F2(x,y,z), and 1 0 1 0 1 0

F3(x,y,z) are shown to the 1 1 0 0 0 0

right. 1 1 1 1 0 1
October 17, 2008 Chapter 2. Combinational Logic Circuits 22
Truth Tables (cont.)

 Truth table: a unique representation of a

Boolean function
 If two functions have identical truth tables, the
functions are equivalent (and vice-versa).
 Truth tables can be used to prove equality
theorems.
 However, the size of a truth table grows
exponentially with the number of variables
involved, hence unwieldy. This motivates the
use of Boolean Algebra.
October 17, 2008 Chapter 2. Combinational Logic Circuits 23
Boolean expressions-NOT unique

 Unlike truth tables, expressions x y z F G

representing a Boolean function are 0 0 0 1 1
NOT unique. 0 0 1 0 0
 Example:
0 1 0 1 1
 F(x,y,z) = x’•y’•z’ + x’•y•z’ + x•y•z’
0 1 1 0 0
 G(x,y,z) = x’•y’•z’ + y•z’
1 0 0 0 0
 The corresponding truth tables for
F() and G() are to the right. They 1 0 1 0 0
are identical! 1 1 0 1 1
 Thus, F() = G() 1 1 1 0 0
October 17, 2008 Chapter 2. Combinational Logic Circuits 24
Algebraic Manipulation

 Boolean algebra is a useful tool for simplifying

digital circuits.
 Why do it? Simpler can mean cheaper,
smaller, faster (revisit slides 11-13).
 Example: Simplify F = x’yz + x’yz’ + xz.
F = x’yz + x’yz’ + xz
= x’y(z+z’) + xz
= x’y•1 + xz
= x’y + xz
October 17, 2008 Chapter 2. Combinational Logic Circuits 25
Algebraic Manipulation (cont.)

 Example: Prove
x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’
 Proof:
x’y’z’ + x’yz’ + xyz’
= x’y’z’ + x’yz’ + x’yz’ + xyz’
= x’z’(y’+y) + yz’(x’+x)
= x’z’•1 + yz’•1
= x’z’ + yz’
QED.

October 17, 2008 Chapter 2. Combinational Logic Circuits 26

Complement of a Function

 The complement of a function is derived by

interchanging (• and +), and (1 and 0), and
complementing each variable.
 Otherwise, interchange 1s to 0s in the truth
table column showing F.
 The complement of a function IS NOT THE
SAME as the dual of a function.

October 17, 2008 Chapter 2. Combinational Logic Circuits 27

 Complementation: Example

 Find G(x,y,z), the complement of

F(x,y,z) = xy’z’ + x’yz
 G = F’ = (xy’z’ + x’yz)’
= (xy’z’)’ • (x’yz)’ DeMorgan
= (x’+y+z) • (x+y’+z’) DeMorgan again
 Note: The complement of a function can also be
derived by finding the function’s dual, and then
complementing all of the literals
October 17, 2008 Chapter 2. Combinational Logic Circuits 28
 Canonical and Standard Forms

 We need to consider formal techniques for

the simplification of Boolean functions.
 Minterms and Maxterms
 Sum-of-Minterms and Product-of- Maxterms
 Product and Sum terms
 Sum-of-Products (SOP) and Product-of-Sums
(POS)

October 17, 2008 Chapter 2. Combinational Logic Circuits 29

Definitions

 Literal: A variable or its complement

 Product term: literals connected by •
 Sum term: literals connected by +
 Minterm: a product term in which all the
variables appear exactly once, either
complemented or uncomplemented
 Maxterm: a sum term in which all the variables
appear exactly once, either complemented or
uncomplemented

October 17, 2008 Chapter 2. Combinational Logic Circuits 30

 Minterm

 Represents exactly one combination in the truth

table.
 Denoted by mj, where j is the decimal equivalent of
the minterm’s corresponding binary combination
(bj).
 A variable in mj is complemented if its value in bj is
0, otherwise is uncomplemented.
 Example: Assume 3 variables (A,B,C), and j=3.
Then, bj = 011 and its corresponding minterm is
denoted by mj = A’BC
October 17, 2008 Chapter 2. Combinational Logic Circuits 31
 Maxterm

 Represents exactly one combination in the truth

table.
 Denoted by Mj, where j is the decimal equivalent of
the maxterm’s corresponding binary combination
(bj).
 A variable in Mj is complemented if its value in bj is
1, otherwise is uncomplemented.
 Example: Assume 3 variables (A,B,C), and j=3.
Then, bj = 011 and its corresponding maxterm is
denoted by Mj = A+B’+C’
October 17, 2008 Chapter 2. Combinational Logic Circuits 32
 Truth Table notation for Minterms and
Maxterms

 Minterms and x y z Minterm Maxterm

Maxterms are 0 0 0 x’y’z’ = m0 x+y+z = M0
easy to denote 0 0 1 x’y’z = m1 x+y+z’ = M1
using a truth 0 1 0 x’yz’ = m2 x+y’+z = M2
table. 0 1 1 x’yz = m3 x+y’+z’= M3
 Example: 1 0 0 xy’z’ = m4 x’+y+z = M4
Assume 3 1 0 1 xy’z = m5 x’+y+z’ = M5
variables x,y,z 1 1 0 xyz’ = m6 x’+y’+z = M6
(order is fixed) 1 1 1 xyz = m7 x’+y’+z’ = M7
October 17, 2008 Chapter 2. Combinational Logic Circuits 33
 Canonical Forms (Unique)

 Any Boolean function F( ) can be expressed

as a unique sum of minterms and a unique
product of maxterms (under a fixed variable
ordering).
 In other words, every function F() has two
canonical forms:
 Canonical Sum-Of-Products (sum of minterms)
 Canonical Product-Of-Sums (product of
maxterms)
October 17, 2008 Chapter 2. Combinational Logic Circuits 34
Canonical Forms (cont.)

 Canonical Sum-Of-Products:
The minterms included are those mj such
that F( ) = 1 in row j of the truth table for
F( ).
 Canonical Product-Of-Sums:
The maxterms included are those Mj such
that F( ) = 0 in row j of the truth table for
F( ).

October 17, 2008 Chapter 2. Combinational Logic Circuits 35

 Example

 Truth table for f1(a,b,c) at right a b c f1

 The canonical sum-of-products 0 0 0 0
form for f1 is
0 0 1 1
f1(a,b,c) = m1 + m2 + m4 + m6
= a’b’c + a’bc’ + ab’c’ + 0 1 0 1
abc’ 0 1 1 0
 The canonical product-of-sums 1 0 0 1
form for f1 is
1 0 1 0
f1(a,b,c) = M0 • M3 • M5 • M7
1 1 0 1
= (a+b+c)•(a+b’+c’)•
(a’+b+c’)•(a’+b’+c’) 1 1 1 0
October 17, 2008 Chapter 2. Combinational Logic Circuits 36
 Observe that: mj = Mj’
 Shorthand: ∑ and ∏

 f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this

is a sum-of-products form, and m(1,2,4,6) indicates
that the minterms to be included are m1, m2, m4, and
m 6.
 f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this
is a product-of-sums form, and M(0,3,5,7) indicates
that the maxterms to be included are M0, M3, M5,
and M7.
 Since mj = Mj’ for any j,
∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)
October 17, 2008 Chapter 2. Combinational Logic Circuits 37
Conversion Between Canonical Forms

 Replace ∑ with ∏ (or vice versa) and replace

those j’s that appeared in the original form
with those that do not.
 Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m 2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
=
(a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
October 17, 2008 Chapter 2. Combinational Logic Circuits 38
 Standard Forms (NOT Unique)

 Standard forms are “like” canonical forms,

except that not all variables need appear in
the individual product (SOP) or sum (POS)
terms.
 Example:
f1(a,b,c) = a’b’c + bc’ + ac’
is a standard sum-of-products form
 f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
is a standard product-of-sums form.
October 17, 2008 Chapter 2. Combinational Logic Circuits 39
 Conversion of SOP from standard to
canonical form
 Expand non-canonical terms by inserting
equivalent of 1 in each missing variable x:
(x + x’) = 1
 Remove duplicate minterms
 f1(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + (a+a’)bc’ + a(b+b’)c’
= a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc + ab’c’

October 17, 2008 Chapter 2. Combinational Logic Circuits 40

 Conversion of POS from standard to
canonical form
 Expand noncanonical terms by adding 0 in terms
of missing variables (e.g., xx’ = 0) and using the
distributive law
 Remove duplicate maxterms

 f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•
(a’+b+c’)•(a’+b’+c’)
=
a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)
October 17, 2008 Chapter 2. Combinational Logic Circuits 41
Karnaugh Maps

 Karnaugh maps (K-maps) are graphical

representations of boolean functions.
 One map cell corresponds to a row in the
truth table.
 Also, one map cell corresponds to a minterm
or a maxterm in the boolean expression
 Multiple-cell areas of the map correspond to
standard terms.

October 17, 2008 Chapter 2. Combinational Logic Circuits 42

 Two-Variable Map
x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1 0 m0 m2

2 3 OR 1 3
1 m2 m3 1 m1 m3

NOTE: ordering of variables is IMPORTANT for

f(x1,x2), x1 is the row, x2 is the column.

Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc. If a

minterm is present in the function, then a 1 is placed in
the corresponding cell.
October 17, 2008 Chapter 2. Combinational Logic Circuits 43
Two-Variable Map (cont.)

 Any two adjacent cells in the map differ by

ONLY one variable, which appears
complemented in one cell and
uncomplemented in the other.
 Example:
m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and m2
(=x1x2’) but NOT m3 (=x1x2)

October 17, 2008 Chapter 2. Combinational Logic Circuits 44

 2-Variable Map -- Example

 f(x1,x2) = x1’x2’+ x1’x2 + x1x2’

= m0 + m1 + m2
= x1’ + x2’
x2
 1s placed in K-map for
specified minterms m0, m1, m2 x1 0 1
 Grouping (ORing) of 1s allows 0 1
simplification 1 1
0
 What (simpler) function is
represented by each dashed 2 3
rectangle?
 x1’ = m0 + m1 1 1 0
 x2’ = m0 + m2
 Note m0 covered twice
October 17, 2008 Chapter 2. Combinational Logic Circuits 45
Minimization as SOP using K-map

 Enter 1s in the K-map for each product term

in the function
 Group adjacent K-map cells containing 1s
to obtain a product with fewer variables.
Groups must be in power of 2 (2, 4, 8, …)
 Handle “boundary wrap” for K-maps of 3 or
more variables.
 Realize that answer may not be unique

October 17, 2008 Chapter 2. Combinational Logic Circuits 46

 Three-Variable Map

yz
00 01 11 10
x
0 1 3 2
0 m0 m1 m3 m2

4 5 7 6
1 m4 m5 m7 m6

- Note: variable ordering is (x,y,z); yz specifies column,

x specifies row.
- Each cell is adjacent to three other cells (left or right
or top or bottom or edge wrap)
October 17, 2008 Chapter 2. Combinational Logic Circuits 47
Three-Variable Map (cont.)
minterm

The types of structures that

are either minterms or are
generated by repeated
application of the
minimization theorem on a
three variable map are
shown at right.
Groups of 1, 2, 4, 8 are
possible. group of 2 terms

group of 4 terms
October 17, 2008 Chapter 2. Combinational Logic Circuits 48
Simplification

 Enter minterms of the Boolean function into

the map, then group terms
 Example: f(a,b,c) = ac’ + abc + bc’
 Result: f(a,b,c) = ac’+ b
abc
1 1 1
1 1
1 1 1
1 1

October 17, 2008 Chapter 2. Combinational Logic Circuits 49

 More Examples

yz
X 00 01 11 10
 f1(x, y, z) = ∑ m(2,3,5,7)
0 1 1
 f1(x, y, z) = x’y + xz 1 1 1

 f2(x, y, z) = ∑ m (0,1,2,3,6)
 f2(x, y, z) = x’+yz’ 1 1 1 1
1

October 17, 2008 Chapter 2. Combinational Logic Circuits 50

Four-Variable Maps
yz
WX
00 01 11 10

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

 Top cells are adjacent to bottom cells. Left-edge

cells are adjacent to right-edge cells.
 Note variable ordering (WXYZ).
October 17, 2008 Chapter 2. Combinational Logic Circuits 51
 Four-variable Map Simplification

 One square represents a minterm of 4 literals.

 A rectangle of 2 adjacent squares represents a
product term of 3 literals.
 A rectangle of 4 squares represents a product
term of 2 literals.
 A rectangle of 8 squares represents a product
term of 1 literal.
 A rectangle of 16 squares produces a function
that is equal to logic 1.
October 17, 2008 Chapter 2. Combinational Logic Circuits 52
 Example

 Simplify the following Boolean function

(A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,10,12,13).
 First put the function g( ) into the map, and then
group as many 1s as possible.
cd
ab
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1
1 1 1 1 1 1
g(A,B,C,D) = c’+b’d’+a’bd
October 17, 2008 Chapter 2. Combinational Logic Circuits 53
5-Variable K-Map

DE
A=1
BC
16 17 19 18
DE
20 21 23 22
BC
0 1 3 28 2 29 31 30

4 5 7 24 6 25 27 26

12 13 15 14
ABCDE’
8 9 11 10

A=0 A’BCDE’

October 17, 2008 Chapter 2. Combinational Logic Circuits 54

 Implicants and
Prime Implicants (PIs)

 An Implicant (P) of a function F is a product

term which implies F, i.e., F(P) = 1.
 An implicant (PI) of F is called a Prime
Implicant of F if any product term obtained
by deleting a literal of PI is NOT an implicant
of F
 Thus, a prime implicant is not contained in
any “larger” implicant.

October 17, 2008 Chapter 2. Combinational Logic Circuits 55

Example

 Consider function f(a,b,c,d) whose

K-map is shown at right. b’
 a’b’ is not a prime implicant ad
cd ab
because it is contained in b’. 1 1
 acd is not a prime implicant 1 1 1
because it is contained in ad.
1 1 1
 b’, ad, and a’cd’ are prime
a’b’ 1 1 1
implicants.
acd
a’cd’

October 17, 2008 Chapter 2. Combinational Logic Circuits 56

Essential Prime Implicants (EPIs)

 If a minterm of a function F is included in ONLY

one prime implicant p, then p is an essential
prime implicant of F.
b’
 An essential prime implicant MUST appear in all
ad
possible SOP expressions of a function
1 1
 To find essential prime implicants:
1 1 1
 Generate all prime implicants of a function 1 1 1
 Select those prime implicants that contain at 1 1 1
least one 1 that is not covered by any other
prime implicant. a’cd’
 For the previous example, the PIs are b’, ad,
and a’cd’; all of these are essential.
October 17, 2008 Chapter 2. Combinational Logic Circuits 57
Systematic Procedure for Simplifying
Boolean Functions
 Generate all PIs of the function.
 Include all essential PIs.
 For remaining minterms not included in the
essential PIs, select a set of other PIs to
cover them, with minimal overlap in the set.
 The resulting simplified function is the
logical OR of the product terms selected
above.

October 17, 2008 Chapter 2. Combinational Logic Circuits 58

Example

 f(a,b,c,d) =
∑m(0,1,2,3,4,5,7,14,15). cd
ab
 Five grouped terms, not all 1 1 1 1

needed. 1 1 1
 3 shaded cells covered by only 1 1
one term
 3 EPIs, since each shaded cell is
covered by a different term.
 F(a,b,c,d) = a’b’ + a’c’ + a’d + abc

October 17, 2008 Chapter 2. Combinational Logic Circuits 59

 Product of Sums Simplification

 Use sum-of-products simplification on the

zeros of the function in the K-map to get F’.
 Find the complement of F’, i.e. (F’)’ = F
 Recall that the complement of a boolean function
can be obtained by (1) taking the dual and (2)
complementing each literal.
 OR, using DeMorgan’s Theorem.

October 17, 2008 Chapter 2. Combinational Logic Circuits 60

 POS Example

cd
ab
1 1 1 1

1 1 1 0

0 0 1 1

0 0 0 0

• F’(a,b,c,d) = ab’ + ac’ + a’bcd’

• Find dual of F’, dual(F’) = (a+b’)(a+c’)(a’+b+c+d’)
• Complement of literals in dual(F’) to get F
F = (a’+b)(a’+c)(a+b’+c’+d)
October 17, 2008 Chapter 2. Combinational Logic Circuits 61
Don't Care Conditions

 There may be a combination of input values

which
 will never occur
 if they do occur, the output is of no concern.
 The function value for such combinations is
called a don't care.
 They are denoted with x or –. Each x may be
arbitrarily assigned the value 0 or 1 in an
implementation.
 Don’t cares can be used to further simplify a
function
October 17, 2008 Chapter 2. Combinational Logic Circuits 62
Minimization using Don’t Cares

 Treat don't cares as if they are 1s to

generate PIs.
 Delete PI's that cover only don't care
minterms.
 Treat the covering of remaining don't care
minterms as optional in the selection
process (i.e. they may be, but need not be,
covered).

October 17, 2008 Chapter 2. Combinational Logic Circuits 63

 cd
Example ab 00 01 11 10
00 0 1 0 1
01 1 1 0 1
 Simplify the function f(a,b,c,d)
11 0 0 x x
whose K-map is shown at the right.
10 1 1 x x
 f = a’c’d+ab’+cd’+a’bc’
or 0 1 0 1

 f = a’c’d+ab’+cd’+a’bd’ 1 1 0 1
0 0 x x
 The middle two terms are EPIs,
1 1 x x
while the first and last terms are
selected to
0 1 0 1
cover the minterms m1, m4, and m5.
1 1 0 1
 (There’s a third solution!)
0 0 x x
1 1 x x
October 17, 2008 Chapter 2. Combinational Logic Circuits 64
Another Example cd
ab
x 1 0 0
1 x 0 x
 Simplify the function 1 x x 1
g(a,b,c,d) whose K-map 0 x x 0

is shown at right. x 1 0 0
 g = a’c’+ ab 1 x 0 x
1 x x 1
or
0 x x 0
 g = a’c’+b’d
x 1 0 0
1 x 0 x
1 x x 1
0 x x 0
October 17, 2008 Chapter 2. Combinational Logic Circuits 65
Algorithmic minimization

 What do we do for functions with more than

4-5 variables?
 You can “code up” a minimizer (Computer-
Aided Design, CAD)
 Quine-McCluskey algorithm
 Iterated consensus
 We won’t discuss these techniques here

October 17, 2008 Chapter 2. Combinational Logic Circuits 66

More Logic Gates

 We can construct any combinational circuit with

AND, OR, and NOT gates
X X
F F X F

Y Y
X Y F = XY X Y F = X+Y
X F=X’
0 0 0 0 0 0
0 1
0 1 0 0 1 1
1 0
1 0 0 1 0 1
1 1 1 1 1 1

 Additional logic gates are used for practical

reasons
October 17, 2008 Chapter 2. Combinational Logic Circuits 67
BUFFER, NAND and NOR

X X
X F F F

Y Y

X Y F = (XY)’ X Y F = (X+Y)’
X F=X
0 0 1 0 0 1
0 0
0 1 1 0 1 0
1 1
1 0 1 1 0 0
1 1 0 1 1 0

October 17, 2008 Chapter 2. Combinational Logic Circuits 68

 XOR and XNOR

XOR: “not-equal” gate X Y F = X⊕Y

0 0 0
X F 0 1 1

Y 1 0 1
1 1 0

X Y F = (X⊕Y)’
XNOR: “equal” gate 0 0 1
0 1 0
X F 1 0 0
Y 1 1 1

October 17, 2008 Chapter 2. Combinational Logic Circuits 69

NAND Gate

 Known as a “universal” gate because ANY

digital circuit can be implemented with NAND
gates alone.
 To prove the above, it suffices to show that
AND, OR, and NOT can be implemented
using NAND gates only.

October 17, 2008 Chapter 2. Combinational Logic Circuits 70

 NAND Gate Emulation

F = (X•X)’ X F = X’
X
= X’+X’
= X’

X X
F = ((X•Y)’)’ F X•Y
Y = (X’+Y’)’
Y
= X’’•Y’’
= X•Y
X X
F = (X’•Y’)’ F = X+Y
= X’’+Y’’
Y Y
= X+Y

October 17, 2008 Chapter 2. Combinational Logic Circuits 71

 The 3-State Buffer

 For the symbol and truth table, Symbol

IN is the data input, and EN,
IN OUT
the control input.
 For EN = 0, regardless of the
EN
value on IN (denoted by X), the
output value is Hi-Z.
 For EN = 1, the output value
Truth Table
follows the input value. EN IN OUT
 Variations: 0 X Hi-Z
 Data input, IN, can be inverted
 Control input, EN, can be inverted 1 0 0
by addition of “bubbles” to signals. 1 1 1
October 17, 2008 Chapter 2. Combinational Logic Circuits 72
Resolving 3-State Values on a
Connection
 Connection of two 3-state buffer
outputs, B1 and B0, to a wire, OUT Resolution
 Assumption: Buffer data inputs can Table
take on any combination of values
B1 B0 OUT
0 and 1
 Resulting Rule: At least one buffer 0 Hi-Z 0
output value must be Hi-Z. Why? 1 Hi-Z 1
 How many valid buffer output Hi-Z 0 0
combinations exist?
Hi-Z 1 1
 What is the rule for n 3-state
buffers connected to wire, OUT? Hi-Z Hi-Z Hi-Z
 How many valid buffer output
combinations exist?
October 17, 2008 Chapter 2. Combinational Logic Circuits 73
3-State Logic Circuit

 Data Selection Function: If s = 0, OL = IN0, else

OL = IN1
 Performing data selection with 3-state buffers:
EN0 IN0 EN1 IN1 OL
IN0
0 X 1 0 0
0 X 1 1 1 S EN0 OL
1 0 0 X 0 IN1
1 1 0 X 1
EN1
0 X 0 X X
 Since EN0 = S’ and EN1 = S, one of the two buffer
outputs is always Hi-Z plus the last row of the table
never occurs.
October 17, 2008 Chapter 2. Combinational Logic Circuits 74
Transmission Gates

 The transmission gate is one of the designs

for an electronic switch for connecting and
disconnecting two points in a circuit:

C’ X Y
C=1 and C’=0
(b) X TG Y
X TG Y

X Y
C C=0 and C’=1 C
(a) (c) (d)

October 17, 2008 Chapter 2. Combinational Logic Circuits 75

 Transmission Gates (continued)

 In many cases, X can be regarded as a data input

and Y’ as an output. C and C, with complementary
values applied, is a control input.
 With these definitions, the transmission gate,
provides a 3-state output:
 C = 1, Y = X (X = 0 or 1)
 C = 0, Y = Hi-Z
 Care must be taken when using the TG in design,
however, since X and Y as input and output are
interchangeable, and signals can pass in both
directions.
October 17, 2008 Chapter 2. Combinational Logic Circuits 76
 Circuit Example Using TG

 Exclusive OR F = A ⊕ C

A TG0 A C TG1 TG0 F

0 0 No path Path 0
C F 0 1 Path No path 1
1 0 No path Path 1
TG1 1 1 Path No path 0

(a) (b)

 The basis for the function implementation

is TG-controlled paths to the output
October 17, 2008 Chapter 2. Combinational Logic Circuits 77
More Complex Gates

 The remaining complex gates are SOP or

POS structures with and without an output
inverter.
 The names are derived using:
 A - AND
 O - OR
 I - Inverter
 Numbers of inputs on first-level “gates” or
directly to second-level “gates”

October 17, 2008 Chapter 2. Combinational Logic Circuits 78

More Complex Gates (continued)

 Example: AOI - AND-OR-Invert consists of a

single gate with AND functions driving an OR
function which is inverted.
 Example: 2-2-1 AO has two 2-input ANDS
driving an OR with one additional OR input
 These gate types are used because:
 the number of transistors needed is fewer than
required by connecting together primitive gates
 potentially, the circuit delay is smaller, increasing
the circuit operating speed
October 17, 2008 Chapter 2. Combinational Logic Circuits 79