Digital Logic Design

Ch 2

Combinational Logic

note 6
Topics

¨ Combinational logic definition

¨ Axioms and Theorems of Boolean algebra
¨ Realizing Boolean formulas
¨ Levels of logic expressions
¤ Two-level logic
¤ Canonical forms
¤ Multi-level logic
¨ Simplifying two-level logic expressions
¤ Boolean cubes
¤ Karnaugh maps

2 Digital Logic Design

Combinational logic

¨ Define
¤ the kind of digital system whose output behavior depends only
on the current inputs è each output is defined as a function
(combination) of inputs
¤ memoryless: its outputs are independent of the historical sequence of
values presented to it as inputs
¤ (cf.) sequential logic
¨ Many ways to describe combination logic
¤ Boolean algebra expression
¤ wired up logic gates
¤ truth tables tabulating input and output combinations
¤ graphical maps
¤ program statements in a hardware description language (e.g. Verilog)
3 Digital Logic Design
Examples of combinational logic

¨ The equivalence circuit ¨ The tally circuit

X Y Equal X Y Zero One Two
0 0 1 0 0 1 0 0
0 1 0 0 1 0 1 0
1 0 0 1 0 0 1 0
1 1 1 1 1 0 0 1

¨ Binary Adder
X Y Cout S X Y Cin Cout S
0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
< Half-adder> 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
< Full-adder>
4 Digital Logic Design
Laws and theorems of Boolean logic

¨ Basic concept
¤ Boolean algebra is the mathematical foundation of digital systems
¤ laws (axioms) : the properties to which the operations of Boolean
algebra must adhere
¤ axioms can be used to prove more general laws
¨ Boolean operations
¤ operation order
COMPLEMENT à AND à OR
¤ parentheses : change the default order of evaluation
¤ examples :
(( ) )
1) A · B + C = A · B + C
2) A + B · C = (A ) + (B · C )

5 Digital Logic Design

Axioms of Boolean algebra

¨ A Boolean algebra consists of

¤ a set of elements B
¤ binary operations { + , • }
¤ and a unary operation { ’ }
¤ such that the following axioms hold (Huntington's postulates):
¨ Axioms
A1. the set B contains at least two elements: a, b
A2. closure: a + b is in B a • b is in B
A3. commutativity: a+b=b+a a•b=b•a
A4. associativity: a + (b + c) = (a + b) + c a • (b • c) = (a • b) • c
=a+b+c =a•b•c
A5. identity: a+0=a a•1=a
A6. distributivity: a + (b • c) = (a + b) • (a + c) a • (b + c) = (a • b) + (a • c)
A7. complementarity: a + a’ = 1 a • a’ = 0

6 Digital Logic Design

 Theorems of Boolean algebra
¨ Operations with 0 and 1 (Unit/Zero properties)
1. X + 0 = X 1D. X • 1 = X
2. X + 1 = 1 2D. X • 0 = 0
¨ Idempotent theorem:
3. X + X = X 3D. X • X = X
¨ Involution theorem: 4. (X’)’ = X
¨ Theorem of complementarity:
5. X + X’ = 1 5D. X • X’ = 0
¨ Commutative law:
6. X + Y = Y + X 6D. X • Y = Y • X
¨ Associative law:
7. (X + Y) + Z = X + (Y + Z) 7D. (X • Y) • Z = X • (Y • Z)
=X+Y+Z =X•Y•Z
7 Digital Logic Design
 Theorems of Boolean algebra
¨ Distributive law:
8. X • (Y + Z) = (X • Y) + (X • Z) 8D. X + (Y • Z) = (X + Y) • (X + Z)
¨ Simplification theorems:
9. X • Y + X • Y’ = X 9D. (X + Y) • (X + Y’) = X
10. X + X • Y = X 10D. X • (X + Y) = X
11. (X + Y’) • Y = X • Y 11D. (X • Y’) + Y = X + Y
¨ DeMorgan’s law: (XY)’ both X and Y are not ... = X’+Y’ neither X nor Y is ...
12. (X + Y + Z +...)’ 12D. (X • Y • Z • ...)’
= X’ • Y’ • Z’ •... = X’ + Y’ + Z’ +...
¨ General form:
13. {f(X1, X2, ... , Xn, 0, 1, +, •)}’ = {f(X1’, X2’, ... , Xn’, 1, 0, •, +)}

8 Digital Logic Design

 Theorems of Boolean algebra

¨Duality:
14. (X + Y + Z + ...)D 14D. (X • Y • Z • ...)D
= X • Y • Z • ... = X + Y + Z + ...
¨ General form:

15. {f(X1,X2,...,Xn,0,1,+,•)}D = f(X1,X2,...,Xn,1,0,•,+)

¨ Theorem for multiplying and factoring

16. (X + Y) • (X’ + Z) 16D. X • Y + X’ • Z

= XX’+XZ+X’Y+YZ = X • Z + X’ • Y XÞZ = (X + Z) • (X’ + Y)
¨ Consensus theorem:

17. X • Y + Y • Z + X’ • Z 17D. (X + Y) • (Y + Z) • (X’ + Z)

= X • Y + X’ • Z = (X + Y) • (X’ + Z)
Proofè XY+X’Z+YZ = XY+X’Z+(X+X’)YZ = XY+X’Z+XYZ+X’YZ = X(Y+YZ)+X’(Z+YZ)

9 Digital Logic Design

 Verifying the Boolean theorems

¨ Verifying the theorems using the axioms of Boolean algebra

¨ Proving the uniting theorem(9): X • Y + X • Y’ = X
Distributive law (8) X • (Y + Y’) =X
Complementarity theorem (5) X • (1) =X
Identity (1D) X =X

¨ Proving the simplification theorem(10): X + X • Y = X

Identity (1D) X•1+X•Y =X
Distributive law (8) X(1 + Y) =X
Identity (2) X(1) =X
Identity (1) X =X

10 Digital Logic Design

 Duality vs. DeMorgan’s law
¨ Duality
¤ a dual of a Boolean expression is derived by replacing
• by +, + by •, 0 by 1, and 1 by 0, and leaving variables unchanged
¤ Any theorem that can be proven is thus also proven for its dual!

º implies º

¤ A meta-theorem (a theorem about theorems) that allow to derive new

theorems: (e.g.) the dual of the uniting theorem(9), X • Y + X • Y’ = X, is
(X + Y) • (X + Y’) = X. è The proof of the dual follows step-by-step, simply
using the duals of the laws used in the original proof.
(X + Y) • (X + Y’) = X?

X + (Y •Y’) =X Distributive law (8D)

X+0 =X Complementarity theorem (5D)
X =X Identity (1)
11 Digital Logic Design
 Duality vs. DeMorgan’s law

¨ DeMorgan’s law Augustus De Morgan

1806-1871 England
¤ (a+b)’ º a’b’ º
(ab)’ º a’+b’

¤ give a procedure for complementing a complex function

¤ the complemented expression is derived by replacing
all literals by their complements, 0 by 1, 1 by 0, • by + and + by •
¤ (e.g.) the complement of Z = ABC + ABC + ABC + ABC
Z = (ABC + ABC + ABC + ABC)
Z = ABC • ABC • ABC • ABC
Z = (A + B + C) (A + B + C) (A + B + C) (A + B + C)

12 Digital Logic Design

 Possible logic functions of two variables

¨ There are 16 possible functions of 2 input variables:

X F
Y

X Y 16 possible functions (F0–F15)

0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 not X 1
X Y X xor Y not Y
X and Y X=Y X nand Y
NOT (Y implies X) X or Y X nor Y Y implies X not (X and Y)
NOT (X implies Y) not (X or Y)
X implies Y

13 Digital Logic Design

 Cost of different logic functions
¨ Different functions are cheaper or more expensive to
implement in CMOS technology
¤ Each has a cost associated with the number of switches needed
¤ 0(F0) and 1(F15): require 0 switches, directly connect output to low/high
¤ X(F3) and Y(F5): require 0 switches, output is one of inputs
¤ X’(F12) and Y’(F10): require 2 switches for "inverter" or NOT-gate
¤ X nor Y (F4) and X nand Y (F14): require 4 switches
¤ X or Y (F7) and X and Y (F1): require 6 switches à AB = ((AB)’)’
¤ X = Y (F9) and X Å Y (F6): require 16 switches à AB’+A’B = ((A’B)’(AB’)’)’
¨ Thus…
¤ A simpler expression for a Boolean function does not necessarily
minimize the number of transistors for its realization.
¤ Because NOT, NOR, and NAND are the cheapest, they are the functions
that we implement the most in practice.
14 Digital Logic Design
 Realizing Boolean formulas: logic gates
X Y Z
¨ NAND X 0 0 1
Z 0 1 1
Y
1 0 1
1 1 0

X Y Z
¨ NOR X 0 0 1
Z 0 1 0
Y 1 0 0
1 1 0

¨ XOR X
X
0
Y
0
Z
0 X xor Y = X Y’ + X’ Y
XÅY Y
Z 0 1 1 X or Y but not both
1 0 1 ("inequality", "difference")
1 1 0

¨ XNOR X Y Z
X xnor Y = X Y + X’ Y’
X=Y X 0 0 1
Z 0 1 0 X and Y are the same
Y
1 0 0
1 1 1 ("equality", "coincidence")
15 Digital Logic Design
 Realizing Boolean formulas: logic blocks
& hierarchy
¨ Complex logic function can be constructed from more
primitive functions by wiring up logic gates
¨ example : 2-bit adder Full Adder
A S Cin S
Half Adder HA
A Cout
B C HA
B

2 bit Adder

C0 =0
A0 S0
FA
B0 C1
S1
A1 FA Cout
B1 Cout

16 Digital Logic Design

 Time behavior and waveforms
¨ Waveform: represent signal propagation over time
Simplified assumptions
¤ x-axis: the time step Ci
2 units
HA S
A
¤ y-axis: the logical value B
HA Co
3 units

¨ Unit delay model: considering the delay through any gate as

taking exactly one time unit for a simplifying assumption
Time

A0 2 bit Adder

A1
C0 =0
B0
S0
B1 A0 FA
B0 C1
C0 S1
A1
C1 FA C2
B1 C2
S0
2 units 2 units
S1
3 units
C2
1 unit for HA (xor, and)
Digital Logic Design
Minimizing the number of gates & wires
¨ Different implementations of one function
A B C Z
0 0 0 0
0 0 1 1 8+6+6+8 transistors
0 1 0 0
0 1 1 1 two-level realization
1 0 0 0 Z1 = Z = A’B’C+A’BC+AB’C+ABC’
1 0 1 1 = ABC’+A’(B’+B)C+(A’+A)B’C
1 1 0 1
1 1 1 0 = ABC’+A’C+B’C

Z=A’B’C+A’BC 4+2+6+6+6 transistors multi-level realization

+AB’C+ABC’ (simple gates but long path)
Z2 = Z1 = ABC’+(A’+B’)C
= ABC’+(AB)’C

6+16 transistors XOR gate (lowest gate count)

Z3 = Z2 = TC’+T’C, T=AB
= (AB) Å C

Digital Logic Design

 Waveforms for three implementations

¨ Waveforms are essentially identical

¤ except for timing hazards (glitches)
¤ delays almost identical (modeled as a delay per level, not type of gate
or number of inputs to gate)
glitch! A=1
Z=A’B’C+A’BC +AB’C+ABC’ B=1ß0
C=0ß1

19 Digital Logic Design

 Two-level logic
¨ Nested levels to express Boolean logics
¤ One-level: Z = A + B, F = AB’, G = A’B
¤ Two-level: Y = F + G = AB’ + A’B
¨ Two-level are sufficient to represent any Boolean expression.
¤ Canonical form: standard form to represent a Boolean expression
¤ unique algebraic signature of the function
¨ Two alternative canonical forms
¤ sum-of-products: AB’ + A’B
¤ product-of-sums: (A + B’)(A’ + B)
¨ Incompletely specified function
¤ In the original form, all 2n possible input combinations must be
considered for a function with n inputs.
¤ For flexibility, we consider one more set: don’t care set
20 Digital Logic Design
 Sum-of-products canonical forms

¨ a.k.a. minterm expansion or a disjunctive normal form (DNF)

¨ An expression in DNF consists of an ORed list of minterms.

F = 001 011 101 110 111

F = A’B’C + A’BC + AB’C + ABC’ + ABC

A B C F F’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 0 F’ = A’B’C’ + A’BC’ + AB’C’

21 Digital Logic Design

 Sum-of-products canonical forms

¨ Product term (or minterm)

¤ ANDed product of literals – input combination for which output is true
¤ each variable appears exactly once, true or inverted (but not both)

A B C minterms
F in canonical form:
0 0 0 A’B’C’ m0
F(A, B, C) = Sm(1,3,5,6,7)
0 0 1 A’B’C m1
= m1 + m3 + m5 + m6 + m7
0 1 0 A’BC’ m2
= A’B’C + A’BC + AB’C + ABC’ + ABC
0 1 1 A’BC m3
1 0 0 AB’C’ m4
canonical form ¹ minimal form
1 0 1 AB’C m5
F(A, B, C) = A’B’C + A’BC + AB’C + ABC + ABC’
1 1 0 ABC’ m6
= (A’B’ + A’B + AB’ + AB)C + ABC’
1 1 1 ABC m7
= ((A’ + A)(B’ + B))C + ABC’
= C + ABC’
short-hand notation for = ABC’ + C
minterms of 3 variables = AB + C
22 Digital Logic Design
 Product-of-sums canonical forms

¨ a.k.a, maxterm expansion or a conjunctive normal form (CNF)

¨ An expression in CNF consists of an ANDed list of maxterms
F= 000 010 100
F = (A + B + C)(A + B’ + C) (A’ + B + C)
A B C F F’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1 A’B’C’ = 1 è (A’B’C’)’ = 0 è (A+B+C) = 0
1 0 1 1 0 000
1 1 0 1 0
1 1 1 1 0

F’ = (A + B + C’) (A + B’ + C’) (A’ + B + C’) (A’ + B’ + C) (A’ + B’ + C’)

23 Digital Logic Design

 Product-of-sums canonical forms

¨ Sum term (or maxterm)

¤ ORed sum of literals – input combination for which output is false
¤ each variable appears exactly once, true or inverted (but not both)

A B C maxterms
F in canonical form:
0 0 0 A+B+C M0
F(A, B, C) = PM(0,2,4)
0 0 1 A+B+C’ M1
= M0 • M2 • M4
0 1 0 A+B’+C M2
= (A + B + C) (A + B’ + C) (A’ + B + C)
0 1 1 A+B’+C’ M3
1 0 0 A’+B+C M4
canonical form ¹ minimal form
1 0 1 A’+B+C’ M5
F(A, B, C) = (A + B + C) (A + B’ + C) (A’ + B + C)
1 1 0 A’+B’+C M6
= (A + B + C) (A + B’ + C)
1 1 1 A’+B’+C’ M7
(A + B + C) (A’ + B + C)
= (A + C) (B + C)
short-hand notation for
maxterms of 3 variables

24 Digital Logic Design

 S-o-P, P-o-S and DeMorgan’s law

¨ Sum-of-products
¤ F’ = A’B’C’ + A’BC’ + AB’C’
¨ Apply DeMorgan’s
¤ (F’)’ = (A’B’C’ + A’BC’ + AB’C’)’
¤ F = (A + B + C) (A + B’ + C) (A’ + B + C)

¨ Product-of-sums
¤ F’ = (A + B + C’) (A + B’ + C’) (A’ + B + C’) (A’ + B’ + C) (A’ + B’ + C’)
¨ Apply DeMorgan’s
¤ (F’)’ = ( (A + B + C’)(A + B’ + C’)(A’ + B + C’)(A’ + B’ + C)(A’ + B’ + C’) )’
¤ F = A’B’C + A’BC + AB’C + ABC’ + ABC

25 Digital Logic Design

 4 alternative two-level implementations of F
Note
A + A’ = 1
A
A’B’+A’B+AB’+AB = 1

B canonical sum-of-products
F1
F1 = A’B’C + A’BC + AB’C + ABC’ + ABC
C

minimized sum-of-products
F2
F2 = AB + C
= ((AB+C)‘)’ = ((A’+B’)C’)’
= (A’C’+B’C’)’
canonical product-of-sums
F3 F3 = (A + B + C)(A + B’ + C)(A’ + B + C)

minimized product-of-sums
F4 F4 = (A + C)(B + C)

26 Digital Logic Design

 Conversion between canonical forms
¨ Minterm to maxterm conversion
¤ use maxterms whose indices do not appear in DNF
¤ e.g., F(A,B,C) = Sm(1,3,5,6,7) = PM(0,2,4)
¨ Maxterm to minterm conversion
¤ use minterms whose indices do not appear in CNF
¤ e.g., F(A,B,C) = PM(0,2,4) = Sm(1,3,5,6,7)
¨ DNF of F to DNF of F’
¤ use minterms whose indices do not appear
¤ e.g., F(A,B,C) = Sm(1,3,5,6,7) F’(A,B,C) = Sm(0,2,4)
¨ CNF of F to CNF of F’
¤ use maxterms whose indices do not appear
¤ e.g., F(A,B,C) = PM(0,2,4) F’(A,B,C) = PM(1,3,5,6,7)
27 Digital Logic Design
 Incompletely specified functions
¨ Example: binary coded decimal (BCD) increment by 1
¤ BCD digits encode the decimal digits 0 – 9
in the bit patterns 0000 – 1001
A B C D W X Y Z
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0 off-set of W
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0 on-set of W
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0 don’t care (DC) set of W
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
these inputs patterns should
1 1 0 0 X X X X
never be encountered in practice
1 1 0 1 X X X X
– "don’t care" about associated
1 1 1 0 X X X X
output values, can be exploited
1 1 1 1 X X X X
in minimization

28 Digital Logic Design

 Notation for incompletely specified functions
¨ Don’t cares and canonical forms
¤ so far, only represented on-set
¤ also represent don’t-care-set
¤ need two of the three sets (on-set, off-set, dc-set)
¨ Canonical representations of the BCD increment by 1 function:
A B C D W X Y Z
¤ Z = m0 + m2 + m4 + m6 + m8 0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
+ d10 + d11 + d12 + d13 + d14 + d15 0 0 1 0 0 0 1 1
= S [ m(0,2,4,6,8) + d(10,11,12,13,14,15) ] 0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
1
0 1 0 1 0 1 1 0
¤ Z = M1 • M3 • M5 • M7 • M9 0 1 1 0 0 1 1 1
• D10 • D11 • D12 • D13 • D14 • D15 0
1
1
0
1
0
1
0
1
1
0
0
0
0
0
1
= P [ M(1,3,5,7,9) • D(10,11,12,13,14,15) ] 1 0 0 1 0 0 0 0
1 0 1 0 X X X X
¤ For realization of Z, don’t care terms will be 1 0 1 1 X X X X
1 1 0 0 X X X X
eventually assigned 0 or 1 in a way to simplify 1 1 0 1 X X X X
the circuit of Z as much as possible. 1
1
1
1
1
1
0
1
X
X
X
X
X
X
X
X
29 Digital Logic Design
Simplification: 2-level combinational logic
¨ Finding a minimal S-of-P or P-of-S realization
¨ Algebraic simplification
¤ not an algorithmic/systematic procedure
¤ how do you know when the minimum realization has been found?
¨ Computer-aided design tools
¤ precise solutions require very long computation times, especially for
functions with many inputs (> 10) NP-hard!
¤ heuristic methods employed – "educated guesses" to reduce amount
of computation and yield good if not best solutions
¨ Hand methods still relevant
¤ to understand automatic tools and their strengths and weaknesses
¤ ability to check results (on small examples)
30 Digital Logic Design
 Essence of Boolean simplification

¨ Key tool to simplification: the Uniting theorem

à AB’ + AB = A (B’ + B) = A
¨ Essence of simplification of two-level logic with uniting
¤ Find two element subsets of the ON-set where only one variable
changes its value
¤ This single varying variable can be eliminated and a single product
term used to represent both elements
F = A’B’+AB’ = (A’+A)B’ = B’
A B F
B has the same value in both on-set rows
0 0 1
– B remains
0 1 0
1 0 1
A has a different value in the two rows
1 1 0 – A is eliminated
31 Digital Logic Design
 Boolean cubes
abbreviated as n-cube

¨ Visual technique for identifying when the uniting theorem

can be applied
¨ truth table with n input variables = n-dimensional cube
01 11
0 1
Y 2-cube
1-cube
X 10
00
X

111 1111
0111

3-cube Y Z 4-cube
101
Y
Z W
000 X 1000
0000 X
32 Digital Logic Design
 Mapping truth tables onto Boolean cubes

¨ The uniting theorem combines two faces of a cube into one

larger face
¨ Adjacency plane
¤ circled elements of the on-set that are directly adjacent
¤ each adjacency plane corresponds to a product term
¨ Example:
G
A B G
01 11
0 0 1 Two 0-dimensional faces (nodes)
0 1 0 B combine into an 1-dimensional
face (line)
1 0 1 00 10
A A varies within face, B does not.
1 1 0
ON-set = solid nodes This face represents the literal B’.
OFF-set = empty nodes B’
DC-set = ´'d nodes
33 Digital Logic Design
 Three variable example
Three 1-dimensional adjacency planes
¨ Binary full-adder carry-out logic (A'+A)BCin

A B Cin Cout AB(Cin'+Cin)

111
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 B C 101
1 0 0 0 A(B+B')Cin
1 0 1 1 000 A
1 1 0 1
1 1 1 1 The on-set is completely covered by
the combination (OR) of the subcubes
of lower dimensionality - note that “111”
is covered three times.

Cout = BCin+AB+ACin Four nodes (0-dimensional) are combined

into three lines (1-dimensional)
34 Digital Logic Design
 Higher dimensional cubes

¨ Sub-cubes of higher dimension than 1

¨ Example: 2-dimensional adjacency plane in a 3-cube
F(A,B,C) = Sm(4,5,6,7)
On-set forms a square
011 111
i.e., a cube of dimension 2
110
010 represents an expression in one variable
001 i.e., 3 dimensions – 2 dimensions
B C 101
A is asserted (true) and unchanged
000 A 100 B and C vary

This subcube represents the

literal A
Four nodes (dimension 0) are
combined into four lines (dimension 1), AB’C’+ABC’+AB’C+ABC
which are then combined into one 2- = AB + AB’ + AC + AC’
dimensional sub-cube (square) =A
35 Digital Logic Design
 m-cubes in n-dimensional Boolean space
¨ In a 3-cube (three variables):
¤ 0-dimensional plane, i.e., a single node, yields a term in 3 literals
n example : 101 = AB’C

¤ 1-dimensional plane, i.e., a line of two nodes, yields a term in 2 literals

n example : 100 101 = AB’
¤ 2-dimensional plane, i.e., a squire plane of four nodes, yields a term in 1
literal 100 101
n example : 110 111 =A
¤ 3-dimensional plane, i.e., a cube of eight nodes, yields 0 literal meaning
a constant logic "1"
¨ In general, an m-dimensional adjacency plane within an
n-dimensional cube (m < n) yields a term with n – m literals
36 Digital Logic Design
Karnaugh maps
Maurice Karnaugh
1924~
¨ The cube notation provides visual clues as to where the
uniting theorem is applied to elements of on-set.
¨ But, humans have the difficulty of visualizing adjacencies in
more than 3 dimensional cubes.
¨ Karnaugh maps alternative reformulation of the truth table
¤ perfectly for expressions with up to four variables
¤ wrap–around at edges
¤ On-set elements with only one variable changing value are adjacent
unlike the situation in a linear truth-table
A B F
A
B 0 1 0 0 1
0 1 1 0 1 0
0 2

1 0 0 1 0 1
1 3
1 1 0
Digital Logic Design
Karnaugh maps (K-Maps)
000
001
011
¨ Numbering scheme based on Gray–code 010
¤ e.g., 00, 01, 11, 10 (for every advancement, a single bit changes) 110
111
¤ only a single bit changes in code for adjacent map cells 101
100
AB A K-map for five/six (=2+2/3+3) variables
C 00 01 11 10 Is in theory possible… but…
A
0
0 2 6 4
0 4 12 8
C 1
1 3 7 5
1 5 13 9 D
B
A 3 7 15 11
C
0 2 6 4 2 6 14 10
B
C
1 3 7 5
B 13 = 1101= ABC’D

Digital Logic Design

 Adjacencies in K-Maps

¨ Wrap from first to last column

¨ Wrap top row to bottom row
A
wrap-around
000 010 110 100 adjacent
A
C 001 011 111 101
B 0 4 12 8

1 5 13 9 D
011 111
110 3 7 15 11
010
C
001 2 6 14 10
B C 101 B

000 A 100

39 Digital Logic Design

 Karnaugh map examples

¨ 2-variable maps
¤ F = AB’ + AB = A
A B F
A
0 0 0
0 1
0 1 0
A
1 0 1 B 0 1

1 1 1

A B G A
¤ G = A’B’ + AB’ = B’
0 0 1 1 1
B’
0 1 0
B 0 0
1 0 1
1 1 0

40 Digital Logic Design

 Karnaugh map examples
¨ 3-variable maps
¤ full adder A B Cin Cout A
0 0 0 0 0 0 1 0
0 0 1 0
0 1 0 0 Cin 0 1 1 1
0 1 1 1 B
1 0 0 0
1 0 1 1 AB + BCin + ACin
1 1 0 1
1 1 1 1

¨ F(A,B,C) = Sm(0,4,5,7) obtain the

A
complement
1 0 0 1 of the function
by covering 0s
C 0 0 1 1
with subcubes
B AC + B’C’ + AB’
(see next page)
41 Digital Logic Design
 More K-Map examples
A
0 0 1 1 G(A,B,C) = A
C 0 0 1 1

A
1 0 0 1 F(A,B,C) = Sm(0,4,5,7) = AC + B’C’
C 0 0 1 1 How to get the maxterms for F from K-Map?

B ② (F’)’ = (BC’ + A’C)’ = (B’+C)(A+C’)

A ①
0 1 1 0 Complement of F(A,B,C) = m(0,4,5,7)
F' simply replace 1's with 0's and vice versa
C 1 1 0 0
F'(A,B,C) = S m(1,2,3,6) = BC’ + A’C
B

42 Digital Logic Design

 Karnaugh map: 4-variable example

¨ F(A,B,C,D) = Sm(0,2,3,5,6,7,8,10,11,14,15)

F = C + A’BD + B’D’
A 1111
0111
1 0 0 1

0 1 0 0
D
C
1 1 1 1 D
C A
1000
1 1 1 1 0000 B
B
find the smallest number of the largest possible
subcubes to cover the On-set
(fewer terms with fewer inputs per term)

43 Digital Logic Design

 Karnaugh maps: don’t cares

¨ f(A,B,C,D) = S m(1,3,5,7,9) + d(6,12,13)

¤ without don't cares
nf = A’D + B’C’D

A
0 0 X 0

1 1 X 1
D
1 1 0 0
C
0 X 0 0
B

44 Digital Logic Design

 Karnaugh maps: don’t cares

¨ f(A,B,C,D) = S m(1,3,5,7,9) + d(6,12,13)

¤ f = A'D + B'C'D without don't cares
¤ f = A'D + C'D with don't cares

A
by using don't care as a "1"
0 0 X 0
a 2-cube can be formed
1 1 X 1 rather than a 1-cube to cover
D this node
1 1 0 0
C don't cares can be treated as
0 X 0 0 1s or 0s
B depending on which is more
advantageous

45 Digital Logic Design

 Multilevel Logic
¨ Comparison with 2-level logic
¤ gain: reduce the number of wires, gates and inputs to each gate
¤ lose: add up more combined delay due to the increased levels of logic
¨ Example
¤ 2-level logic
Z = ADF + AEF + BDF + BEF + CDF + CEF + G
à six 3-input AND gates, one 7-input OR gate
¤ multilevel logic
Z = (AD + AE + BD + BE + CD + CE)F + G
Z = [(A + B + C)D + (A + B + C)E]F + G
Z = (A + B +C)(D + E)F + G
à one 3-input OR gate, two 2-input OR gates, one 3-input AND gate

46 Digital Logic Design

 Chapter review
¨ Variety of primitive logic building blocks
¤ NOT, AND, OR, NAND, NOR, XOR and XNOR gates
¨ Axioms and theorems of Boolean algebra
¤ proofs by re-writing and perfect induction
¨ Two-level logic
¤ canonical forms: sum-of-products and product-of-sums
¤ incompletely specified functions
¨ Simplification
¤ a start at understanding two-level simplification
¤ Boolean cubes
¤ K-Map

47 Digital Logic Design