Chapter 7

Memory and Programmable

Logic

7-1. Introduction

There are two types of memories that are used in

digital systems:
Random-access memory(RAM): perform both the write and
read operations.
Read-only memory(ROM): perform only the read operation.

The read-only memory is a programmable logic

device. Other such units are the programmable logic
array(PLA), the programmable array logic(PAL), and
the field-programmable gate array(FPGA).

Array logic

A typical programmable logic device may have

hundreds to millions of gates interconnected
through hundreds to thousands of internal paths.

In order to show the internal logic diagram in a

concise form, it is necessary to employ a special
gate symbology applicable to array logic.

7-2. Random-Access
Memory
A memory unit stores binary information in groups of bits called
words.
1 byte = 8 bits
1 word = 2 bytes

The communication between a memory and its environment is

achieved through data input and output lines, address selection lines,
and control lines that specify the direction of transfer.

Content of a memory

Each word in memory is

assigned an identification
number, called an
address, starting from 0
up to 2k-1, where k is the
number of address lines.

The number of words in a

memory with one of the
letters K=210, M=220, or
G=230.
64K = 216 2M = 221
4G = 232

Write and Read operations

1.

2.

3.

Transferring a new word to be stored into

memory:
Apply the binary address of the desired
word to the address lines.
Apply the data bits that must be stored in
memory to the data input lines.
Activate the write input.

Write and Read operations

1.

2.

Transferring a stored word out of memory:

Apply the binary address of the desired word to
the address lines.
Activate the read input.
Commercial memory sometimes provide the two
control inputs for reading and writing in a
somewhat different configuration in table 7-1.

Memory description in HDL

A memory of 1024 words
with 16-bits per word is
declared as
reg [15:0]
memword[0:1023];

Read/Write = 1
DataOut Mem[Address];
Read/Write =0
Mem[Address] DataIn;
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Timing Waveforms (write)

The access time and cycle

time of the memory must be
within a time equal to a fixed
number of CPU clock cycles.

The memory enable and the

read/write signals must be
activated after the signals in
the address lines are stable
to avoid destroying data in
other memory words.

Enable and read/write signals

must stay active for at least
50ns.
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Timing Waveforms (read)

The CPU can

transfer the data
into one of its
internal registers
during the negative
transition of T3.

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Types of memories

In random-access memory, the word

locations may be thought of as being
separated in space, with each word
occupying one particular location.

In sequential-access memory, the

information stored in some medium is not
immediately accessible, but is available only
certain intervals of time. A magnetic disk or
tape unit is of this type.
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Types of memories

In a random-access memory, the access time

is always the same regardless of the
particular location of the word.

In a sequential-access memory, the time it

takes to access a word depends on the
position of the word with respect to the
reading head position; therefore, the access
time is variable.

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Static RAM

SRAM consists essentially of internal latches that

store the binary information.

The stored information remains valid as long as

power is applied to the unit.

SRAM is easier to use and has shorter read and write

cycles.

Low density, low capacity, high cost, high speed,

high power consumption.

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SRAM Cell (6 Transistors)

SRAM memory cell depicting Inverter

Loop as gates
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SRAM memory cell

SRAM memory cell depicting Inverter Loop as gates
Storage
The working principle of SRAM memory cell can be easier to understand if we
draw transistors M1 through M4 as logic gates. That way we can clearly see
that at its heart the cell storage is built using of two cross-coupled inverters.
This simple loop, creates a bi-stable circuit. A logic 1 at the input of the first
inverter turns into a 0 at its output, and it is fed into the second inverter which
transforms that logic 0 back to a logic 1 feeding back the same value to the
input of the first inverter. That creates a stable state that does not change over
time. Similarly the other stable state of the circuit is to have a logic 0 at the
input of the first inverter. After been inverted twice it will also feedback the
same value. Therefore there are only two stable states that the circuit can be in:

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Reading
To read the contents of the memory cell stored in the loop, the transistors M5
and M6 must be turned on. when they receive voltage to their gates from the
word line WL ,they become conductive and so the Q and Q values get
transmitted to the bit line BL and to its complement BL(BAR). Finally this
values get amplified at the end of the bit lines.
Writing
The writing process is similar, the difference is that now the new value that we
want to store in the memory cell is driven into the bit line and into its
complement . Next transistors M5 and M6 are open by driving a logic one
(voltage high) into the word line connecting the bit lines to the loop. There are
two possible cases: If the value of the loop is the same as the new value driven,
there is no change.
If the value of the loop is different from the new value driven there are two
conflicting values, in order for the voltage in the bit lines to overwrite the
output of the inverters, the size of the M5 and M6 transistors must be larger
than that of the M1-M4 transistors to allow more current to flow through them
and tip the voltage in the new value direction, the loop will then amplify it to
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full rail.

Bi Polar RAM cell

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18

Dynamic RAM

DRAM stores the binary information in the form of

electric charges on capacitors.

The capacitors are provided inside the chip by MOS

transistors.

The capacitors tends to discharge with time and

must be periodically recharged by refreshing the
dynamic memory.

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DRAM Cell (1 Transistor and one capacitor)

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DRAM memory cell

Storage
The storage element of the DRAM memory cell is the capacitor labeled in
the diagram above. The charge stored in the capacitor degrades over
time, so its value must be refreshed (read and rewritten) periodically.
The nMOS transistor acts as a gate to allow reading or writing when
open or storing when closed.
Reading
For reading the Word line drives a logic 1 (voltage high) into the gate of the nMOS
transistor which makes it conductive and the charge stored at the capacitor is
then transferred to the bit line. The bit line will have a parasitic capacitance that
will drain part of the charge and slow the reading process. The capacitance of the
bit line will determine the needed size of the storage capacitor . It is a trade-off. If
the storage capacitor is too small, the voltage of the bit line would take too much
time to raise or not even rise above the threshold needed by the amplifiers at the
end of the bit line. Since the reading process degrades the charge in the storage
capacitor its value is rewritten after each read.
Writing
The writing process is the easiest, the desired value logic 1 (high voltage) or logic
0 (low voltage) is driven into the bit line. The word line activates the nMOS
transistor connecting it to the storage capacitor . The only issue is to keep it open
enough time to ensure that the capacitor is fully charged or discharged before
turning off the nMOS transistor .
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Dynamic RAM

DRAM offers reduced power consumption and larger

storage capacity in a single memory chip.

High density, high capacity, low cost, low speed, low

power consumption.

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Types of memories

Memory units that lose stored information

when power is turned off are said to be
volatile.

Both static and dynamic, are of this category

since the binary cells need external power to
maintain the stored information.

Nonvolatile memory, such as magnetic disk,

ROM, retains its stored information after
removal of power.
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7-3. Memory decoding

The equivalent logic of a binary cell that stores one

bit of information is shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

SR latch with NOR gates

Ref. Figure 5-3

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4X4 RAM

There is a need for decoding

circuits to select the
memory word specified by
the input address.

During the read operation,

the four bits of the selected
word go through OR gates to
the output terminals.

During the write operation,

the data available in the
input lines are transferred
into the four binary cells of
selected word.
Athe
memory with 2k words of n bits per word requires k address lines that go into

kx2k decoder.

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Coincident decoding
address

A decoder with k inputs

and 2k outputs requires 2k
AND gates with k inputs
per gate.

Two decoding in a twodimensional selection

scheme can reduce the
number of inputs per
gate.

1K-word memory, instead

of using a single 10X1024
decoder, we use two
5X32 decoders.

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Address multiplexing

DRAMs typically have four times the density of

SRAM.

The cost per bit of DRAM storage is three to four

times less than SRAM. Another factor is lower power
requirement.

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Address multiplexing

Address multiplexing will reduce the number of pins

in the IC package.

In a two-dimensional array, the address is applied in

two parts at different times, with the row address
first and the column address second. Since the same
set of pins is used for both parts of the address, so
can decrease the size of package significantly.

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Address multiplexing for 64K

DRAM

After a time equivalent

to the settling time of
the row selection, RAS
goes back to the 1 level.

Registers are used to

store the addresses of
the row and column.

CAS must go back to the

1 level before initialing
another memory
operation.

Column Address Selection

Row Address Selection

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7-5. Read-Only Memory

A block diagram of a ROM is shown below. It consists

of k address inputs and n data outputs.

The number of words in a ROM is determined from

the fact that k address input lines are needed to
specify 2k words.

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Construction of ROM

Each output of the decoder represents a memory address.

Each OR gate must be considered as having 32 inputs.
A 2k X n ROM will have an internal k X 2 k decoder and n
OR gates.

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Truth table of ROM

A programmable connection between to lines is

logically equivalent to a switch that can be altered
to either be close or open.
Intersection between two lines is sometimes called a
cross-point.

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Programming the ROM

In Table 7-3,

0 no connection
1 connection
Address 3 = 10110010 is permanent storage using fuse link

X : means connection
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Combinational circuit
implementation

The internal operation of a ROM can be interpreted

in two way: First, a memory unit that contains a
fixed pattern of stored words. Second, implements a
combinational circuit.

Fig. 7-11 may be considered as a combinational

circuit with eight outputs, each being a function of
the five input variables.

A7(I4, I3, I2, I1, I0) = (0,2,3,29)

Sum of minterms
In Table 7-3, output A7
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Example
Design a combinational circuit using a ROM. The circuit accepts a 3-bit
number and generates an output binary number equal to the square of
the input number.
Derive truth table first

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Example

36

Types of ROMs

1.
2.

3.

4.

The required paths in a ROM may be programmed

in four different ways.
Mask programming: fabrication process
Read-only memory or PROM: blown fuse /fuse
intact
Erasable PROM or EPROM: placed under a special
ultraviolet light for a given period of time will
erase the pattern in ROM.
Electrically-erasable PROM(EEPROM): erased with
an electrical signal instead of ultraviolet light.
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Combinational PLDs

A combinational PLD is an integrated circuit with

programmable gates divided into an AND array and
an OR array to provide an AND-OR sum of product
implementation.

PROM: fixed AND array constructed as a decoder

and programmable OR array.

PAL: programmable AND array and fixed OR array.

PLA: both the AND and OR arrays can be

programmed.
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Combinational PLDs

39

7-6. Programmable Logic

Array

Fig.7-14, the decoder in PROM is replaced by an

array of AND gates that can be programmed to
generate any product term of the input variables.

The product terms are then connected to OR gates

to provide the sum of products for the required
Boolean functions.

The output is inverted when the XOR input is

connected to 1 (since x1 = x). The output doesnt
change and connect to 0 (since x0 = x).

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PLA
F1 = AB+AC+ABC
F2 = (AC+BC)

41

Programming Table
1.
2.

3.

4.

First: lists the product terms numerically

Second: specifies the required paths
between inputs and AND gates
Third: specifies the paths between the AND
and OR gates
For each output variable, we may have a
T(ture) or C(complement) for programming
the XOR gate
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Simplification of PLA

Careful investigation must be undertaken in

order to reduce the number of distinct
product terms, PLA has a finite number of
AND gates.

Both the true and complement of each

function should be simplified to see which
one can be expressed with fewer product
terms and which one provides product terms
that are common to other functions.
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Example 7-2
Implement the following two Boolean functions with a PLA:
F1(A, B, C) = (0, 1, 2, 4)
F2(A, B, C) = (0, 5, 6, 7)
The two functions are simplified in the maps of Fig.7-15

1 elements
0 elements

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PLA table by simplifying the

function

Both the true and

complement of the functions
are simplified in sum of
products.
We can find the same terms
from the group terms of the
functions of F1, F1,F2 and F2
which will make the
minimum terms.
F1 = (AB + AC + BC)
F2 = AB + AC + ABC
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PLA implementation

AB
AC
BC
ABC

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7-7. Programmable Array

Logic

The PAL is a programmable logic device with a fixed OR array

and a programmable AND array.

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PAL

When designing with a PAL, the Boolean

functions must be simplified to fit into each
section.

Unlike the PLA, a product term cannot be

shared among two or more OR gates.
Therefore, each function can be simplified by
itself without regard to common product terms.

The output terminals are sometimes driven by

three-state buffers or inverters.
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Example
w(A, B, C, D) = (2, 12, 13)
x(A, B, C, D) = (7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = (1, 2, 8, 12, 13)
Simplifying the four functions as following Boolean functions:
w = ABC + ABCD
x = A + BCD
y= AB + CD + BD
z = ABC + ABCD + ACD + ABCD = w + ACD + ABCD

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PAL Table

z has four product terms, and we can replace by w

with two product terms, this will reduce the number
of terms for z from four to three.

50

PAL implementation
w
A
x
B
y
C
z
D
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Fuse map for example

52

7-8. Sequential Programmable

Devices

Sequential programmable devices include

both gates and flip-flops.

There are several types of sequential

programmable devices, but the internal logic
of these devices is too complex to be shown
here.

We will describe three major types without

going into their detailed construction.
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Sequential Programmable
Devices
1.

Sequential (or simple) Programmable Logic Device

(SPLD)

2.

Complex Programmable Logic Device (CPLD)

3.

Field Programmable Gate Array (FPGA)

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FPLS

The first programmable device developed to support

sequential circuit implementation is the fieldprogrammable logic sequencer(FPLS).

A typical FPLS is organized around a PLA with

several outputs driving flip-flops.

The flip-flops are flexible in that they can be

programmed to operate as either JK or D type.

The FPLS did not succeed commercially because it

has too many programmable connections.

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SPLD

Each section of an SPLD is called a

macrocell.

A macrocell is a circuit that contains a sumof-products combinational logic function and

an optional flip-flop.

We will assume an AND-OR sum of products

but in practice, it can be any one of the twolevel implementation presented in Sec.3-7.
56

Macrocell

Fig.7-19 shows the logic of a basic macrocell.

The AND-OR array is the same as in the combinational
PAL shown in Fig.7-16.

57

CPLD

A typical SPLD has from 8 to 10 macrocells within

one IC package. All the flip-flops are connected to
the common CLK input and all three-state buffers
are controlled by the EO input.

The design of a digital system using PLD often

requires the connection of several devices to
produce the complete specification. For this type of
application, it is more economical to use a complex
programmable logic device (CPLD).

A CPLD is a collection of individual PLDs on a single

integrated circuit.
58

CPLD

Fig.7-20 shows a general configuration of a CPLD. It

consists of multiple PLDs interconnected through a
programmable switch matrix. 8 to 16 macrocell per PLD.

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Gate Array

The basic component used in VLSI design is

the gate array.
A gate array consists of a pattern of gates
fabricated in an area of silicon that is
repeated thousands of times until the entire
chip is covered with the gates.
Arrays of one thousand to hundred thousand
gates are fabricated within a single IC chip
depending on the technology used.

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FPGA

FPGA is a VLSI circuit that can be programmed in the

users location.

A typical FPGA logic block consists of look-up tables,

multiplexers, gates, and flip-flops.

Look-up table is a truth table stored in a SRAM and

provides the combinational circuit functions for the
logic block.

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Differential of RAM and ROM in

FPGA

The advantage of using RAM instead of ROM to store

the truth table is that the table can be programmed
by writing into memory.

The disadvantage is that the memory is volatile and

presents the need for the look-up table content to
be reloaded in the event that power is disrupted.

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