Unit IV

MEMORY DEVICES
 Semiconductor memories – used
as an internal memory
1.Main Memory/Working memory-Computer’s internal
memory –constant communication with CPU (RAM and
ROM)-fast –stores the current program used by CPU

2.Auxiliary memory/Mass storage (works at slower speed)

- stores the program currently not used by CPU
(magnetic tape, Magnetic bubble memory)
Memory cell- a device or electrical circuit used to
store a single bit (0 or 1) Eg: FF , charged capacitor
Memory Unit - a device to which binary information
is stored and retrieved when needed-
collection of storage cells together with associated
circuits needed to transfer information in and out of
storage.

Block diagram of a memory unit

 Memory word / Word
• A memory unit stores binary information in groups of
bits called words .
• A word in memory is an entity of bits that move in
and out of storage as a unit. A memory word is a
group of 1’s and 0’s and may represent a number, an
instruction, one or more alphanumeric characters, or
any other binary‐coded information.
• Group of 8 bits=byte
• Word Size : no of bits per word
• a 16‐bit word contains two bytes, and a 32‐bit word
is made up of four bytes
 Memory Capacity
• the total number of bytes that the memory unit can
store.
It is Denoted by :
No of Words in the memory * No of bits per word
Eg: a memory with 4096 twenty bit words
Specified as : 4096 * 20
1 KB of memory  2^10= 1024 is the memory capacity
4 KB = 4*1024 = 4096
Specified as : 4K* 20

So Memory Capacity can be represented as 4K*20

1K = 210 ; 1M = 220 1G = 230
64K = 26 210 = 216
Memory operation

Memory enable
=Chip select
 Write and Read Operations
Write Operation (store operation) Read Operation(fetch operation)
1. Apply the binary address of the • 1. Apply the binary address of
desired word to the address lines. the desired word to the
2. Apply the data bits that must address lines.
be stored in memory to the data • 2. Activate the read input.
input lines.
3. Activate the write input.
 Memory Density
• another term for memory capacity
• Memory device A has greater density than
another memory device B .It means that A can
store more bits in the same amount of space.
Access time and Cycle time of Memory
• The access time of memory is the time required
to select a word and read it. (tacc)
• The cycle time of memory is the time required to
complete a write operation.
• The CPU must provide the memory control
signals in such a way as to synchronize its internal
clocked operations with the read and write
operations of memory.
• This means that the access time and cycle time of
the memory must be within a time equal to a
fixed number of CPU clock cycles.
 Address lines
- Special input lines that selects one particular
word .
- Each word has a IDENTIFIACTION Number
called as address starting from 0,1,2,….2k – 1.
- Why K address lines?
To address 2k words
-
 Problem
1.How many words can be stored on a certain SC
memory chip specified by 2K*8?

Total no of words: 2K= 2*1024=2048 words

8 bits per word.
Total bits stored in chip: 2048*8 = 16,384 bits.
 Problem
Which memory stores the most bits
1. 5M * 8 memory (OR)
2. A memory that stores 1M words at a word
size of 16 bits
1.5*1048576*8 = 41943040 bits
2. 1048576 *16 = 16777216 bits

5M * 8 memory stores more bits.

Types of Memories
 ROM
• ROM can perform only the read operation. This means that
suitable binary information is already stored inside
memory and can be retrieved or read at any time.
• However, that information cannot be altered by writing.
• ROM is a programmable logic device (PLD). The binary
information that is stored within such a device is specified
in some fashion and then embedded within the hardware
in a process is referred to as programming the device.
• The word “programming” here refers to a hardware
procedure which specifies the bits that are inserted into the
hardware configuration of the device.
 RAM
RAM stores new information for later use.

The process of storing new information into

memory is referred to as a memory write operation.

The process of transferring the stored information

out of memory is referred to as a memory read
operation.

RAM can perform both write and read operations.

 RAM
 Can be written to or read from.
Read/Write memory
 Reading from RAM is non-destructive.
 Access time to read from any memory
location is the same.
As compared to serial access memory.
 Volatile
Information is lost when power is removed.
 Types of RAM
 Static Random Access Memory (SRAM)
Based on the Flip-Flop
Requires a large number of transistors
Fast
VOLATILE MEMORY(Memory units that lose
stored information when power is turned off are
said to be volatile.
- reduced power consumption and larger storage
capacity
• Static RAM (SRAM) consists essentially of internal latches
that store the binary information. The stored information
remains valid as long as power is applied to the unit.
 Dynamic Random Access Memory (DRAM)
Uses a single transistor to store charge
Requires very few transistors
Must be periodically refreshed
Slow(er)
- Reduced power consumption and larger
storage capacity
• Dynamic RAM (DRAM) stores the binary information in the
form of electric charges on capacitors provided inside the
chip by MOS transistors.
- VOLATILE MEMORY
 RAM
 Access time to read from any memory location is the same.

RAM
Contents of a 1024 * 16 memory
Control inputs to Memory Chip
 Timing Waveforms
Access time
Cycle time
• The CPU must provide the memory control
signals in such a way as to synchronize
its internal clocked operations with the read
and write operations of memory.
Memory Cycle Timing Waveforms-
Write Cycle
Memory Cycle Timing Waveforms-
Read Cycle
• CPU operates with a clock frequency of 50 MHz, giving a
period of 20 ns for one clock cycle.
• The two lines that cross each other in the address and data
waveforms designate a possible change in value of the
multiple lines.
• The memory enable and the read/write signals must be
activated after the signals in the address lines are stable in
order to avoid destroying data in other memory words.
• The memory enable signal switches to the high level and
the read/write signal switches to the low level to indicate a
write operation.
• The two control signals must stay active for at least 50 ns.
 MEMORY DECODING
• Decoding circuits to select the memory word
specified by the input address
• Memory unit : small capacity of 16 bits,
arranged in four words of 4 bits each.
 Memory Cell- Binary Cell (BC)
Internal Construction Block Diagram

The select input enables the cell for reading or writing, and the read/write input
determines the operation of the cell when it is selected. A 1 in the read/write
input provides the read operation by forming a path from the latch to the output
terminal. A 0 in the read/write input provides the write operation by forming a
path from the input terminal to the latch.
Construction of 4x4 RAM
 Operation
A memory with four words needs two address lines.
The decoder is enabled with memory enable signal.
Memory enable = 0, all outputs of the decoder
are 0 and none of the
memory words are selected
= 1 , one of the four words is
selected, dictated by the value in
the two address lines.
Read operation
• the four bits of the selected word go through OR
gates to the output terminals
Word operation
• the data available in the input lines are
transferred into the four binary cells of the
selected word.
• The binary cells that are not selected are
disabled, and their previous binary values remain
unchanged.
• A memory with 2k words of n bits per word
requires k address lines that go into a k * 2k
decoder. Each one of the decoder outputs
selects one word of n bits for reading or
writing.
• This decoder requires 2k AND gates with k
inputs each.
 Coincident Decoding
• For 1K-word memory instead of using 10 x1024 decoder, we
use two 5x32 decoder in a two dimensional selection scheme.
• A 10x1024 decoder requires 1024 AND gates with 10 inputs
each, whereas when we use two 5x32 decoder it requires
totally 64 AND gates with five inputs each
• 10 Bit address is split into MSB 5 bits and LSB 5 bits. The MSB
bits are given to X and LSB bits are given to Y.
Coincident Decoding-Example
 Example
• consider the word whose address is 404.
• The 10‐bit binary equivalent of 404 is
01100 10100.
This makes
X = 01100 (binary 12) and Y = 10100 (binary 20).
The n ‐bit word that is selected lies in the X decoder
output number 12 and the Y decoder
output number 20.
All the bits of the word are selected for reading or
writing.
 SRAM Cell
Internal Construction Block Diagram

The select input enables the cell for reading or writing, and the read/write input
determines the operation of the cell when it is selected. A 1 in the read/write
input provides the read operation by forming a path from the latch to the output
terminal. A 0 in the read/write input provides the write operation by forming a
path from the input terminal to the latch.
Bipolar RAM Cell
6 Transistor (MOSFET) SRAM Cell
DRAM- Address multiplexing for 64K word memory
 Explanation
• The memory consists of a two‐dimensional array of cells
arranged into 256 rows by 256 columns.
• 28 * 28 = 216 = 64KB words
• It contains a single data input line, a single data output line, and
a read/write control, as well as an eight‐bit address input and
two address strobes
• Row address strobe (RAS) enables the eight‐bit row register
• Column Address strobe (CAS) enables the eight‐bit column
register.
• The bar on top of the name of the strobe symbol
indicates that the registers are enabled on the zero level
of the signal.
 Explanation
• The 16‐bit address is applied to the DRAM in two steps using RAS and CAS.
• Initially,both strobes are in the 1 state. The 8‐bit row address is applied to
the address inputs and RAS is changed to 0.
• This loads the row address into the row address register.
• RAS also enables the row decoder so that it can decode the row address
and select one row of the array.
• After a time equivalent to the settling time of the row selection, RAS goes
back to the 1 level.
• The 8‐bit column address is then applied to the address inputs, and CAS is
driven to the 0 state. This transfers the column address into the column
register and enables the column decoder. Now the two parts of the
address are in their respective registers, the decoders have decoded them
to select the one cell corresponding to the row and column address, and a
read or write operation can be performed on that cell.
• CAS must go back to the 1 level before initiating another memory
operation.
 DRAM
• SRAM typically has 6 transistors
• DRAM consists of only one transistor and capacitor
• Capacitor charge will be discharged with respect to time.
Hence it should be periodically recharged.
• DRAMS have 4 times the density and cost is also 4 times less
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