William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 5
Internal Memory
Memory cell
• The basic element of a semiconductor
memory is the memory cell.
—They exhibit two stable (or semistable) states,
which can be used to represent binary 1 and
0.
—They are capable of being written into (at
least once), to set the state.
—They are capable of being read to sense the
state.
 Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility

Random-access
Read-write memory Electrically, byte-level Electrically Volatile
memory (RAM)

Read-only
Masks
memory (ROM)
Read-only memory Not possible

Programmable
ROM (PROM)

Erasable PROM
UV light, chip-level
(EPROM) Nonvolatile

Electrically

Electrically Erasable Read-mostly memory

Electrically, byte-level
PROM (EEPROM)

Flash memory Electrically, block-level

Semiconductor Memory
• RAM
—Misnamed as all semiconductor memory is
random access
—Read/Write
• Volatile
• (RAM must be provided with a constant power supply. If the
power is interrupted, then the data are lost)

• Temporary storage
• The two traditional forms of RAM used in
computers are DRAM and SRAM.
• Dynamic or Static
 Memory Cell Operation

Select, Selects a memory cell for a read or write operation.

The control terminal indicates read or write.
Dynamic RAM
• A dynamic RAM (DRAM) is made with cells that
store data as charge on capacitors
— Bits stored as charge in capacitors
— The presence or absence of charge in a capacitor is
interpreted as a binary 1 or 0.
• Because capacitors have a natural tendency to
discharge, dynamic RAMs require periodic charge
refreshing to maintain data storage. The term
dynamic refers to this tendency of the stored
charge to leak away, even with power
continuously applied.
• Charges leak
• Need refreshing even when powered
Dynamic RAM Structure
DRAM Operation
• Address line active when the bit value from this cell is to be
read or written
• Transistor acts as a switch i.e closed (current flows) if a voltage is
applied to the address line & open (no current flows) if no voltage
is present on the address line
• For the Write Operation
— Voltage signal is applied to bit line
– High voltage for 1 low voltage for 0
– A signal is then applied to the address line to Transfer
charge to capacitor
• For the Read Operation
— When Address line is selected
– transistor turns on
— Charge from capacitor fed out via bit line to sense amplifier
– Sense amplifier Compares capacitor voltage with reference value
to determines if the cell contains a logic 1 or a logic 0
– The readout from the cell discharges the capacitor, which
must be restored to complete the operation.
Dynamic RAM
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
• Essentially analogue device
—The capacitor can store any charge value
within a range; a threshold value determines
whether the charge is interpreted as 1 or 0.
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• More expensive
• Does not need refresh circuits
• Faster
• A static RAM will hold its data as long as power is
supplied to it.
• Digital Device
—binary values are stored using traditional flip-
flop logic-gate configurations
Stating RAM Structure for an individual
cell

Four transistors
(T1,T2,T3,T4) are cross
connected in an
arrangement that
produces a stable logic
state

State 1 and State 0

Both states are stable as

long as the direct current
(dc) voltage is applied.
Static RAM Operation
• Transistor arrangement gives stable logic
state
• In Logic State 1
—C1 high, C2 low
—T1 T4 off, T2 T3 on
• In Logic State 0
—C2 high, C1 low
—T2 T3 off, T1 T4 on
• As in the DRAM, the SRAM address line is
used to open or close a switch.
Read & Write
• The address line controls two transistors
(T5 and T6)
• When a signal is applied to address line,
the two transistors are switched on,
allowing a read or write operation.
• For a write operation, the desired bit
value is applied to line B, while its
complement is applied to line . This
forces the four transistors (T1, T2, T3, T4)
into the proper state.
• For a read operation, the bit value is
read from line B.
SRAM v DRAM
• Both volatile
— Power needed to preserve data (bit values)
• Dynamic cell
— Simpler to build, smaller
— More dense
— Less expensive
— Needs refresh
— Larger memory units
• Static
— Faster than DRAMs.
— Cache
• Because of these relative characteristics, SRAM is
used for cache memory (both on and off chip),
and DRAM is used for main memory.
Read Only Memory (ROM)
• Permanent storage
—While it is possible to read a ROM, it is not
possible to write new data into it
• Nonvolatile (that is, no power source is
required to maintain the bit values in
memory)
• An important application of ROMs is
microprogramming(see later), Other
potential applications include:
—Library subroutines
—Systems programs (BIOS)
—Function tables
Types of ROM
• Advantage of ROM is that the data or program is
permanently in main memory and need never be
loaded from a secondary storage device
• Written during manufacture
— Very expensive for small runs, no room for error
• Programmable (once)
— PROM
— Needs special equipment to program
• Read “mostly”
— Erasable Programmable (EPROM)
– Erased by UV
— Electrically Erasable (EEPROM)
– Takes much longer to write than read
— Flash memory
– Erase whole memory electrically
EPROM
• The optically erasable programmable read-only
memory (EPROM) is read and written electrically, as with
PROM.
• However, before a write operation, all the storage cells
must be erased to the same initial state by exposure of the
packaged chip to ultraviolet radiation.
• Erasure is performed by shining an intense ultraviolet light
through a window that is designed into the memory chip.
• This erasure process can be performed repeatedly; each
erasure can take as much as 20 minutes to perform.
• Thus, the EPROM can be altered multiple times and, like
the ROM and PROM, holds its data virtually indefinitely.
• For comparable amounts of storage, the EPROM is more
expensive than PROM, but it has the advantage of the
multiple update capability.
EEPROM
• A more attractive form of read-mostly memory is
electrically erasable programmable read-only
memory (EEPROM).
• This is a read-mostly memory that can be written into at
any time without erasing prior contents; only the byte or
bytes addressed are updated.
• The write operation takes considerably longer than the
read operation, on the order of several hundred
microseconds per byte.
• The EEPROM combines the advantage of nonvolatility with
the flexibility of being updatable in place, using ordinary
bus control, address, and data lines.
• EEPROM is more expensive than EPROM and also is less
dense, supporting fewer bits per chip.
Flash memory
• flash memory (so named because of the speed with which
it can be reprogrammed). First introduced in the mid-
1980s, flash memory is intermediate between EPROM and
EEPROM in both cost and functionality.
• Like EEPROM, flash memory uses an electrical erasing
technology.
• An entire flash memory can be erased in one or a few
seconds, which is much faster than EPROM.
• In addition, it is possible to erase just blocks of memory
rather than an entire chip.
• Flash memory gets its name because the microchip is
organized so that a section of memory cells are erased in a
single action or “flash.” However, flash memory does not
provide byte-level erasure.
• Like EPROM, flash memory uses only one transistor per bit,
and so achieves the high density (compared with EEPROM)
of EPROM.
Advanced DRAM Organization
• Basic DRAM same since first RAM chips
• In recent years, a number of enhancements to
the basic DRAM architecture have been explored,
and some of these are now on the market.
• The schemes that currently dominate the market
are SDRAM,DDR-DRAM,and RDRAM.
ADVANCED DRAM ORGANIZATION
(Self Reading)
• Synchronous DRAM (SDRAM)
• RAMBUS
• DDR SDRAM
• Cache DRAM
Cache DRAM
• Mitsubishi
• Integrates small SRAM cache (16 kb) onto
generic DRAM chip
• Used as true cache
—64-bit lines
—Effective for ordinary random access
• To support serial access of block of data
—E.g. refresh bit-mapped screen
– CDRAM can prefetch data from DRAM into SRAM
buffer
– Subsequent accesses solely to SRAM