Power Plan
BY : Abhishek Mandole
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create_net -power VDD
▪ create_net : This suggests a function or command used to create a new net (connection) within
the design.
▪ -power VDD : This option specifies the type and name of the net being created.
▪ -power : This indicates that the net is designated as a power net.
▪ VDD : This is a commonly used name for the positive power supply net.
create_net –ground VSS
▪ -ground : This indicates that the net is designated as a ground net
▪ VSS : This is a commonly used name for the negative or reference voltage net.
connect_pg_net -net VDD [get_pins -hierarchical "*/*/*/*/VDD"]
▪ Deals with connecting power rings.
▪ connect_pg_net : Command used to establish connections between pins within the design. The
“pg_net” likely refers to a power or ground net.
▪ -net VDD : This option specifies the target net for the connection. Here, "VDD" (common power
supply net) is specified.
▪ [get_pins –hierarchical “*/*/*/*/VDD”] : This section retrieves info about the pins that will be
connected to the VDD net.
▪ get_pins : Likely retrieves the info about pins within the design
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▪ -hierarchical : This flag might instruct the tool to search for pins hierarchically within the
design (potentially across different levels of cell nesting).
▪ “*/*/*/*/VDD” : ‘*’ potentially targeting all levels of cell hierarchy. “VDD” specifies that
the tool should search for the pins with name “VDD”.
connect_pg_net -net VSS [get_pins -hierarchical "*/*/*/*/VSS"]
▪ -net VSS :This option specifies the net to which the pins will be connected, which is the
ground net (VSS) in this case.
▪ “*/*/*/*/VSS” : ‘*’ potentially targeting all levels of cell hierarchy. “VSS” specifies that the
tool should search for the pins with name “VSS”.
set_attribute [get_lib_cells */*TIE*] don’t_touch false
▪ set_attribute : Common used to modify attribute values of cells within the design.
▪ get_lib_cells : This command retrieves info about standard library cells placed in the design.
▪ */*TIE* : The search pattern to filter the library cells. “TIE” specify that the target cells have
names containing the string “TIE”.
set_lib_cell_purpose –include optimization [get_lib_cells */*TIE]
▪ set_lib_cell_purpose : Command used to define the purpose or optimization intent of
standard cells within the design.
▪ -include optimization: This instructs the tool to include these cells in the optimization
process during placement and routing
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create_pg_mesh_pattern P_top_two \
-layers { \
{{horizontal_layer : M9}{width :0.12}{spacing : interleaving}{pitch: 2.40} {offset:0.00} {trim: true}}\
{{vertical_layer : M8}{width :0.12}{spacing : interleaving}{pitch: 2.40} {offset:0.00} {trim: true}}\
}
▪ create_pg_mesh_pattern : This suggests a function or command used to create a new power mesh
pattern within the design.
▪ P_top_two : This is the user-assigned name for the power mesh pattern being created.
▪ -layers : option defines the metal layers that will be used to create the power mesh
▪ “horizontal_layer : M9” : This specifies M9 as the metal layer to be used for the horizontal mesh.
▪ “vertical_layer : M8” : This specifies M8 as the metal layers to be used for the vertical mesh.
▪ “width :0.12” : This sets the width of the mesh lines to 0.12.
▪ “spacing : interleaving” : This specifies the spacing between mesh lines using “interleaving” pattern
▪ “pitch : 2.4” : This defines the pitch as 2.4
▪ “offset : 0.00” : This set the offset of the mesh pattern from origin.
▪ “trim : true” : This instructs the tool to trim the edges of the mesh pattern
BY : Abhishek Mandole
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set_pg_strategy s_default_vddvss \
-core\
-pattern {{name : P_top_two} {nets : {VSS VDD}} }\
-extension { { stop:design_boundary_and_generate_pin}} }
▪ set_pg_strategy : This suggests a function or command used to define a power grid (pg) strategy
for power delivery within the design
▪ s_default_vddvss : This assigns a name “s_default_VDD_VSS” to the power grid strategy being
defined. This strategy likely applies to the power supply (VDD) and ground (VSS) nets.
▪ -core : This option might specify that this strategy applies to the core area of the design
▪ -pattern {{ name : P-top_two} {nets : {VSS VDD}}} : This part defines the power mesh pattern
to be used for this strategy.
▪ {{name : P_top_two}} : This references the power mesh pattern named "p_top_two" that you
previously defined .
▪ {nets : {VSS VDD}} : This specifies that the mesh pattern should be applied to both VDD (power
supply) and VSS (ground) nets.
▪ -extension { { stop:design_boundary_and_generate_pin}} } : This option defines an extension
rule for the strategy.
▪ { { stop:design_boundary_and_generate_pin}} : This might instruct the tool to stop extending
the power mesh pattern at the design boundary and also generate pins for the mesh at those
boundaries.
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compile_pg –strategies {s_default_vddvss}
▪ Appears to be the final step in defining your power grid strategy for the design
▪ compile_pg : This suggests a function or command used to compile or finalize the power grid (pg)
strategy for the design.
▪ -strategies {s_default_vddvss} : This option specifies the power grid strategies that should be
compiled.
▪ {s_default_vddvss} : This references the strategy named “s_default_VDD_VSS” that you
previously defined using “set_pg_strategy”.
create_pg_std_cell_conn_pattern std_pattern –layers {M1} –check_std_cell_drc true –
mark_as_follow_pin false
▪ create_pg_std_cell_conn_pattern : This suggests a function or command used to create a new
pattern for how standard cells connect to the power grid.
▪ std_pattern : This assigns the name “std_pattern” to the standard cell connection pattern being
created.
▪ -layers {M1} : This option specifies the metal layer that this pattern applies to. Here, “M1”
indicates the first metal layer.
▪ –check_std_cell_drc true : This option instructs the tool to perform standard cell Design Rule
Checks (DRCs) when applying this pattern.
▪ -mark_as_follow_pin false : This option controls how pins connected using this pattern are treated.
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set_pg_strategy rail_strat –core –pattern {{name:std_pattern} {nets:{VDD VSS}} }
▪ set_pg_strategy : This suggests a function or command used to define a power grid (pg) strategy
for power delivery within the design.
▪ rail_strat : This assigns the name “rail_strat” to the power grid strategy being defined.
▪ -core : This option specifies that this strategy applies to the core area of the design. The core
typically refers to the central region containing the main logic circuitry.
▪ -pattern {{name:std_pattern} {nets:{VDD VSS}} } : This part defines the power mesh pattern to
be used for this strategy.
▪ {{name:std_pattern}} : This references a power mesh pattern named “std_pattern” that you likely
defined earlier using create_pg_mesh_pattern.
▪ {nets:{VDD VSS}} : This specifies that the mesh pattern should be applied to both VDD (power
supply) and VSS (ground) nets.
compile_pg –strategies rail_strat
▪ compile_pg : This suggests a function or command used to compile or analyze the power grid
(PG) within your design.
▪ -strategies : This option specifies that you're defining strategies for power grid optimization.
▪ rail_strat : This argument likely refers to a specific power grid strategy named “rail_strat”.
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create_pg_vias –nets {VDD VSS} –from_layers M1 –to_layers M8
▪ create_pg_vias : This function or command creates vias specifically for the power grid (PG).
▪ –nets {VDD VSS} : This option specifies the nets for which vias will be created. In this case, it
targets both the power net (VDD) and the ground net (VSS).
▪ –from_layers M1 : This option defines the metal layer where the vias will be originating from.
Here, “M1” refers to a specific metal layer in your design stackup (the order of different metal
layers used for routing).
▪ –to_layers M8 : This option defines the metal layer where the vias will be terminating. Here,
"M8" refers to another metal layer in your stackup.
check_pg_connectivity
▪ This command instructs the tool to perform a series of checks to ensure proper connectivity and
integrity of the power grid.(It gives you Number of floating wires, vias, standard cells, IO pads
floating treminals etc).
check_pg_drc
▪ This command instructs the tool to compare the layout of your power grid against a set of
predefined design rules( It gives you minimum width and spacing for metal, minimum width and
spacing for via, minimum area and etc).
save_block –as powerplan_done
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Thank You
BY : Abhishek Mandole
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