PnR: (Place and Route)

The main intention of PnR is:

Density should be under control.

Should met timing.

No DRC’s.

INPUTS:
1) Verilog Netlist
2) Timing libraries (.libs)
3) Physical libraries (.lefs)
a. Tech lefs
b. Standard cell lefs
c. Memory lefs
d. IP lefs
4) Constraint file (SDC)
5) Extraction related files (QRC TechFiles/captables)
6) DEF (IO File)
7) MMMC setup for timing
• LEFS
• Technology LEFS
▪ LAYER:
Type,Direction,minspace,spacingtable,parallelrunlength,Thickness,width,pitch,
Area,Min enclosure area, Resistance, capacitance, End Cap, Min and Max
densities.
▪ VIA:
Type, spacing table, property, Antenna information
▪ Non-default Rules
▪ Core site information: It includes class (core), size width X Height.
• Standard cell , Memories and IO lefs
▪ Macro Name, Class(std cells = core , remaining = block), Origin, Size, OBS
▪ pin : Direction,Use,Port,Layer Metals
Initial Checks:
Netlist Related:
1) Multi driven Nets (Will Inform to synth)
2) Empty Modules (Will Inform to Synth)
3) Net list Unique (will inform to synth)
Will move forward with this command set init_design_uniquify {1}
4) I/P Floating terminals (will inform to synth and will add Tie cells)
5) Dangling Nets (will inform to synth)
6) checkDesign -netlist –dangling
7) Assign statements.

SDC Related
1) Unconstrained endpoints (will inform to synth)
2) Clock not found where clock is expected (will inform to synth)

Validating Timing constraints

timeDesign -prePlace

check_timing -verbose

Extraction File Checks:

Make sure the Quantus techfile and lef files should match.
Floor Plan:
Floor Plan Guide lines:
1) Communication between modules using Design hierarchy, connectivity module.
2) Soft and Hard Macros
3) I/O placement
4) Channel calculation based on metal scheme used in design and minimum space for PG set.
5) Macro placement should be at the edges of the core area. So that core area will not split.
6) Usage of Floor planning Tool box
7) Macro pins towards core area and should be on the track.
8) Hallow creation
9) Do’s
a. Should not rotate the hard macros. Macro orientation (should not have R270 and R90
orientations they will cause polysilicon issues )
b. Should place macros as their successive numbers.
c. Placing the hard macros nearby highly communicating macros.
d. Leaving center core area for standard cell placement.
e. Proper Blockages at area in between Hard Macros.
f. After floor plan change the macros status should be COVER of FIXED

Macro Orientations: The poly orientation in macro and the poly orientation of standard cell
should be in same direction. The poly orientation will be vertical in R0, R180,Mx for lower technologies
like 22nm. That’s why the rotation of the macro not allowed. If we change the rotation of macro the
impact will be cached in Physical verification tools.

Ports and Pins:

1. The input, inout and output terminals which are communicating with external world is
call ports.
2. The input, inout and output terminal which are communicating with in the module is
called as pins.
3. Things we have to look after assigning IO ports
a. Whether the ports are on track are not?
b. Whether the ports layers are in preferred direction or not?
4. Things we have to look with respect to Pins
a. Whether the macro pins are aligning with layer track or not?
Bases of Macro Placement:
1. Macro should be placed at the boundaries of block only. If we place the macros middle of the core
area module will be split.
2. Placing the same module macros at same place.
3. Placing the macros by understanding communication between modules.
4. Placing the macros with respective of ports. (macros which are directly communicating with IOs)
5. Orientation of macro. ( Preferred direction is macro pins facing the core area)

Why Hallow:
1. Hallow is more like a hard blockage. The difference is the hard blockage will not move with macro
move. But, hallows will move the hard macros moving.
2. Usually the pins layers which are available for macro are higher than the pins layers of the
standard cells. (Ex: Macro pins in 4th layer and std cell pins in 2nd layer)
3. There is no problem if two standard cells are setting by each other. But, if the standard cells sit by
Macros (aborted) then some DRC issues will be there in between layers used in macro and layers
which are connecting to the standard cell.

Estimation of channels between macros:

1. (No pins pins*Pitch*2) / No of available layers.
2. A minimum area is needed in between the macros for one set of PG stripes.
3. For current project we are estimating channel as 1micron for 10 wires.

How can we Freeze the Floor:

After one iteration of placement floor plan will be freeze by seeing the module communication,
congestion, tran and timing.

Floor plan checks:

1. Fixed attribute for all macros in design.
2. Fixed attribute for all IO ports in the design.
3. Overlapping of macros. (Not allowed)
4. Macros outside boundary. (Not allowed)
5. Whether hallow is present for all macros.
6. Pins of Macros towards the core.
7. Minimum channel in between macros for the one set of PG stripe.
8. Utilization.
Physical cells: Endcaps & Well taps were added
END CAPS:
1. The end caps are used for the cell characterization.
2. To limit the wells.
3. Design for manufacturability.

Different kind of end caps were added at each different edge. Like below

• LeftBottomCorner - SC7P5T_CNREXTANTENNANRX9_CSC36L
• LeftTopCorner -SC7P5T_CNREXTANTENNAPRX9_CSC36L
• RightBottomCorner -SC7P5T_CNREXTANTENNANLX9_CSC36L
• RightTopCorner -SC7P5T_CNREXTANTENNAPLX9_CSC36L
• LeftBottomEdge -SC7P5T_CONCAVENRX9_CSC36L
• LeftTopEdge -SC7P5T_CONCAVEPRX9_CSC36L
• LeftEdge -SC7P5T_ROWCAPANTENNARX9_CSC36L
• RightBottomEdge -SC7P5T_CONCAVENLX9_CSC36L
• RightTopEdge -SC7P5T_CONCAVEPLX9_CSC36L
• RightEdge -SC7P5T_ROWCAPANTENNALX9_CSC36L
• TopEdge -SC7P5T_COLCAPPX1_CSC36L
• BottomEdge -SC7P5T_COLCAPNX1_CSC36L

WELL TAPS:
1. Due to bulk resistance occur in the CMOS both NMOS & PMOS are in ON state it causes the latch
up problem in CMOS devices. If this bulk resistance go on increasing then sever problem will be
there.
2. To avoid this latch up problem well tap cells are added.

NAME: SC7P5T_TAPZBX7_CSC36L

Cell Interval: 70

Physical cells check:

1. Whether End caps are added or not? Their placement?
2. Whether well Taps are added or not? Are they placed by interval or not?
Power Planning:
GUIDELINES
1. Global net connections.
2. Enable pins shapes of cells
3. Add PG rings (Depends on flip chip and bounded chip technologies)
4. Add PG stripes
5. Add physical cells
6. Check connections (Violations: Opens & shorts) -> Undefined connections which are not specified in
the netlist.

PG Pin Connectivity:
1. Global Net connections: Through naming convention the nets should connected to all same
named nets.

PG short:
Connection established between two different named nets. (Verify Geometry)

PG Opens:
No connection established for the defined net connections. (Verify Connectivity)

Creating Power Mesh:

1. Requirements:
a) Width, Set to set distance, Spacing
b) Type of layers
c) Number of layers
2. Based on attributes specified in the technology lef we will assign spacing and width of the metals.
3. The set to set distance and number of stripes in PG Mesh are fully based on current (I)
requirement for the chip.
4. For power planning the top layers will be used because for top layers the width is higher. As the
width of the layers is high the resistance will low then obviously the drop will be low. And one
more thing is if stripe width is too high then it cause blockage of routing resources.

5. Current project PG Mesh is

 Power stripes are in M7 and M8

a) M7 (VERTICAL) (VDD_VIRTUAL, VDD_CM4, VSS_VIRTUAL)

a. Set-to-set-distance: 8
b. Width: 1.6
c. Spacing: 0.51
d. VERITCAL OFFSET: 1.76
b) M8 (HORIZONTAL) (VDD_VIRTUAL,VSS_VIRTUAL,VDD_CM4)
a. Set –to –set –distance: 13.2
b. Width: 2.2
c. Spacing: 2.2
d. HORIZONTAL OFFSET: 1

VIA’s used in PG Mesh:

1. Stack Via (a stack of layers from to layer to bottom layer or PG pin layers).

Do’s:

1. Power names, Ground names.

2. Vertical and horizontal stripes.
3. Fallow pins
4. Shorts and Opens
5. Strips should not exceed boundary.

Power grid Checks:

1. Global net connections.
2. Availability of one set of PG stripes in each and every channel.
3. Verify drc for shorts.
4. Verify connectivity for opens.
5. Verify power via for checking via’s are placed or not.
PLACEMENT:
Intention of Placement: Placing the standard cells in core area. We have to look in to
congestion and timing.

The placement is two types:

1. Timing driven placement: If the design is timing critical then we have to use timing driven
placement. In timing driven placement tool will place standard cells based on module
communication and timing delays.
2. Congestion driven placement: In congestion driven placement it will give priority to
congestion.

Buffer count after Place optimization: 24084.

Goals of Placement:
a) Congestion.
b) Tran fixed.
c) Timing.
d) Module Placemen

Things we have to look after Placement:

1. Module placement. (Floor plan Freeze or updates)

2. Congestion. ( Cell padding, partial blockage addition)
3. Timing. (Check whether the logic place at far distance or not)
4. Timing QOR.
5. Density bins (Checks: setPlaceMode –uniform density true or false, more number of Buffer
addition, Clustered logic, given area should be within the limit.)

Checks before placement checks after placement

a) timeDesign – preplace. a) Utilization
b) check_timing. b) TrailRouteCongestion
c) Check_design –all c) checkPlace
d) checkFplan –reportUtill d) module placement
e) checkPlace e) density map
f) report_clocks
g) report_congestion
CTS:
CTS Intention:
The main intention of CTS is to meet the frequency of the design by balancing the skew and reducing the
insertion delay.

CTS Goals:
a) Building the clock tree.
b) Clock coverage (Each and every sequential cells in the design should have the clock).
c) Balancing the clock tree and minimizing the insertion delays in order to meet timing, power
requirement.
d) Clock tree optimization.

CTS Spec file:

A. Non default Rules:
Detail Routing
Spacing
Width
Preferred layer
Bottom laye
B. Default Rules:
Auto CTS Route Pin, Max delay, min delay, Max skew, Sink max tran, Buf max tran, No
gating, Non leaf pins, Route clk Net, Macro model pin, Global Exclude pin,Through pin

Buffer Count : 1994

Checks after CTS: 11. CkSynthesis –check {setCTSMode –engine ck

or ccopt}
1. Clock tree coverage and skew and insertion 12. Clock Desig
delays are in with in the limit or not.
2. Trace file (Drawing of clock tree and check CTSopt checks:
for the re-convergent and cross over points.)
3. Chceck_timing 1. How many buffers are added
4. timeDesign 2. checkDesign
5. check_timing 3. timeDesign
6. CheckPlace 4. check_timing
7. Congestion 5. Congestion
8. Utilization 6. Density
9. Reportclocktree 7. Utilization
10. AnalyzeClockTreeSpec 8. LEC
CTS spec file Terminology and use:
ROUTE & ROUTE OPT:
Main intention of Routing: The basic intention of routing is to provide physical connectivity by
considering the logical connectivity (Net list). And the main intention of routing is to establish physical
connectivity by considering the logical connection with respect to density, timing and DRCs.

How Density, Timing and DRC’s effects the routing?

1. If Density of the design is high, while routing detours will exist in the design it may
effect the timing. And in density congested areas probability of DRCs is high.
2. As in routing realistic RC values will be considered so that, timing may effect.
3. Because of cells which have high pin density (more number of pins) DCR’s effect is
high.

Algorithm of Routing:

Basically routing algorithm having two steps to complete the routing.

1. Global routing / initial routing:

In Global routing it will not do actual routing. It will do only track
assignment and congestion calculation based on G-cells.
2. Global Detail routing:
Based on global routing provided inputs (track assignment, congestion
calculations). The global detail routing will start detail routing by considering some
switches like cross talk aware, DFM aware and NDR.
Once first iteration of detail routing is done it will check for the DRCs. To
reduce those DRCs it will go to multiple iterations till the DRCs reduced.
While fixing the DRC violations toll will compromise DFM and cross talk
aware routing. And sometimes it will prefer off-track routing based on the user
inputs.

Checks after Route:

• DRCs, SI aware and replacing the multi cut vias for strong connectivity and reducing
manufacturing errors
• Process antenna violations, glitches and noice.
• timeDesign • congestion
• check filler • Density
• LEC • Utilization
• check_timing • verifyConnectivity
• checkPlace • verifyGeomet
Physical Verification:
1. Stream out GDS
2. Initial Merging.
3. Fill generation.
4. Extraction.
5. Double patterning.
6. Final Merging.
7. Spice Netlist

Checks:

1. DRC : sign off tool (caliber) DRC count

2. LEC : sign off netlist should not contain any shorts and opens
3. LVS : Logic vs schematic
4. PM checks (Pattern matching) : avoiding the particular patterns
5. Mass checks (Manufacturing Analysis score) : Vias count in particular area. (Vias score)

Flow:

RouteOpt DB •From PnR

•All
StreamOut GDS standard
cells GDS's

InitialMerge •Merging all GDS's.

s
Setup and Hold equations:
R2R
Setup: (T clk + T cap – T setup – T uncertainty) – (T launch + T cq + T combi)

Hold: (T launch + T cq + T combi) – (T cap +T hold + T uncertainty )

I2R
Setup: (T clk + T cap – T setup – T uncertainty) – (I/P external delay + Tcombi internal)

Hold: (I/P external delay + Tcombi internal) – ( T cap +T hold – T uncertainty)

[I/P External delay = T launch + Tcq + T cmobi external]

R2O

Setup: (Virtual clock – o/p external delay) – (T launch + T combi internal + Tcq + T uncertainty )

[o/p External delay = Tsetup + Tcombi external – T capture]

Hold: (T launch + T combi internal + Tcq ) – ( -(o/p external delay ) + T uncertainty )

[o/p External delay = - T hold+ T cmobi – T cap]

Possibilities of setup violations:

1. More Data path delay.
2. Memories in data path
 3. Negative skew
4. High launch clock path insertion delays.
5. Less capture clock path insertion delays.
6. Far placement of capture flop.

How can we met setup?

1. Upsizing the cells in data path.
2. Skew management
3. Defining macro models for high delay producing launching paths which contains macros.
4. Adding of cells in data path.

Possibilities of hold violations:

1. Less data path delay.
2. More capture clock path delay.
3. Less launch clock path delay.
4. More skew.
5. Cell types used in path and their placement.

How can we met Hold?

1. Sizing and skew management. Delays cells addition in Date path.
Miscellaneous:
1. How congestion will be calculated?
Based on G-Cell overflow the tool will estimates tracks and reports the congestion values for
that particular area.
2. What is utilization?
Utilization is two types
a. Core utilization: Total occupied area of standard cells, macros and blockages / Available
area.
b. Standard cell utilization (Avg module density): Standard cell area / allocated area of
core.
c. Manageable utilization should be 72 to 75. If the utilization is more manageable
utilization that will leads to high density bins.
d. Utilization should be monitored at each stage.
3. What are the possibilities of utilization jump?
a. Need to check whether it is because of Tran, setup or hold.
b. If it is because of hold we need to look into CTS.
c. If it is because of setup we should look from placement itself.
d. If it is because of Tran we need to look into the placement and Tran limits used in design
too.
4. How can we compensate routing stage timing violation in before stages?
a. Uncertainty:
• Adding uncertainty in before stages will compensate the timing violations in next
stages.
• Uncertainty is the unintended parameters which effect the timing violations.
• The parameters in Uncertainty is Clock jitter, ocv, cross talk, wireload model and
skew.
Clock jitter (for setup) Placement CTS Routing
OCV of cells and nets Placement CTS Routing
Cross talk of nets Placement CTS
Wire load model Placement CTS
Skew Placement

b. RC Factors:
• The RC Factors are generated based on the two engines for extraction in Quantus
Tool. Those two are
a. Default engine: This engine generates RC values of nets based on the trail
route which is not realistic.
 b. Detailed engine: This engine enables the post route stage. It will do
extraction based on detailed routing which is accurate.
• By using these two engines extracted reports the tool called ostrich will generates
RC Factors for each net. Based on these factors before stages of routing will
increase the delays of nets.
5. Which layers are used for the clock routing.? Why ?
Top signal layers are usually preferred for the clock routing (5, 6). As the width is
indirectly proportional to the resistance cross talk will effect should be less. And one more
thing is if we prefer lower layers for clock routes as we use double width and double spacing
the layers tracks will be blocked. And routing for signal nets are a bit congested.
6. Timing Is violated in placeOpt stage then what will you do?
a. First thing is module placement. We need to visually check whether the cells are
placed far away.
b. Trans in the design. In this case we need to resolve the trans changing the floor
plan, placement of some macros or usage of proper module constraints.
c. Check the buffers count in data path and should know the reason for buffer count
and resolve them. The reason Is the tool may use buffers to overcome the tran
violations and max fan out violations.
d. If all above cases are good then we need to check the cell delays of the path. The
memories (Hard macros) produces more delays. As the memories are harden we
will some macro models before going into the CTS stage.
7. How to balance the CTS ?
a. With lesser insertion delays and better skewing.
b. Better clock tran limits.
c. Observing the min and max latencies.
d. If the latencies are high then it will leads to bad skewing.
e. Clock buffers types.
f. For high delay consuming paths like macros path applying the macro models.
8. If setup is violated after CTS what will you do?
a. We have to check the skew value between begin and end pair. If the skew is
negative then it will automatically leads to setup violation. Then we need to
resolve the negative skew.
b. If there is no negative skew. Then we need to look in to the data path for possibility
of decreasing the delays.
c. Or else decrease the launch path delay. Else increase capture path delay.
9. If hold is violated after CTS what will you do?
a. Need to check the skew. If the skew is more then we need to resolve this skew.
b. If there is no problem with more skew. Then we should try to add some delay to
the data path.
c. Else try to increase the launch path. Or else decrease the capture path delay.
10. Routing and Route Opt difference?
a. Routing intention is to provide physical connectivity by considering the logical
connectivity in the netlist. Here realistic routing will be done (honoring the design
rule checks). Because of this realistic routing net lengths are changed, then these
nets will offer more delays. Because of this realistic routing the violations will be
observed. For balancing these violated paths we should need to do optimization
after routing.
11. Differences observed in between 22nm and 44nm?
a. Area will be decrease.
b. Cell delays are less.
c. Routing wise quiet difficult for DRCs aware routing.
d. DFM related changes like End caps around the core area.
e. Will be challenging for the Physical verification perspective.
12. Techniques to reduce the latencies?
a. Nearby placement of clock gating cells.
b. Try reduce the clock gating cells delays by upsizing.
c. Defining the macro models.
13. Effect of higher latencies?
a. Will effect when OCV come in to the picture more skew will be observed for high
latency paths.
b. Possibility of bad timig QOR.
14. What are the reasons for IR Drop?
a. No vias on metal layers.
b. High Density bins region.
c. More Sequential elements are placed at on place. Need to spread them by padding
of partial blockages.
d. If it is ON-OFF then, power gaters placement.
e. Defining the source point for PG.
15. What are Inputs for LVS ?
a. .pv (Netlist) file from PnR stage. By using spice tool we will convert .pv into the
schematic. By merging the schematic with library cells schematic. We will have
final schematic (spice netlist).
b. And another input is merged Layout.
c. When comparing this layout and schematic the tool will convert this layout into
intermediate schematic form which is called as extraction.
16. Dynamic power dissipation formula?

Pdynamic = ∑ αi . Ci. 𝑉𝑑𝑑 2 . 𝑓

𝑖=1
.i = nodes
α = switching activity of node i.
C = capacitance at node i
f = operating frequency.
N= Number of nodes.
17. Congestion fixing techniques?
a. Step 1:
• Set the value of the -congEffort option to high. The default in Innovus is auto.
setPlaceMode -congEffort high
• For congested designs, set congEffort to high, prior to running placeDesign. A
high effort mode runs more iterations of placement in an effort to achieve better
congestion results. However, this parameter increases the run time.
• Rerun the placement.
b. Step 2:
• Run the congRepair command
• This command performs an incremental placement based on the trialRoute
congestion results and improves the congestion hot spots by spreading out the
cells. It is mostly used after running the placeDesign command. However,
sometimes it can be used after a pre-CTS optimization as well. Because this
command tends to move many cells around, it should not be run after a post-CTS
optimization.
• Note: The congRepair command can be used to remove congestion in a local
design area using the -area option.
c. Step 3:
• Use module padding
• setPlaceMode -modulePadding module factor
• This is typically used where there is a module that is very congested and hence,
hard to route. This option specifies a module that needs padding (placement
clearance), and a factor that is used to calculate the padding dimension.
• The placer multiplies the instance area of all the cell instances under the specified
module by the factor. For example, a factor of 2 means that the placer "sees"
each cell as twice its actual size. In most cases, a factor of 1.2 (increases the area
by 20 percent) is adequate.
 • When you add padding, it reduces the placement density and localized
congestion (hotspots) by spreading out the cell instances in the specified
modules. Module padding provides guidance for global placement only, and is
ignored during placement legalization (refinePlace).
d. Step 4:
• Use density screens
• You can use the createDensityArea command to create density screens, also
known as partial placement blockages. Density screens guide the placer to spread
cells over the region by limiting the utilization to a specified value instead of
generating "hot spots".
• Density screens are useful tools that you can use to solve numerous congestion-
related issues, particularly the localized routing congestion. If there is some
channel through which many signals must travel (for example, a wide bus), use
density screens or outright placement blockages to keep instances from being
placed in the area.
• When you see routing or other violations centered around a specific area, or
when the congestion map is hotter in specific areas, use a partial or complete
placement blockage and then run placeDesign again. Alternately, run placeDesign
-incremental to spread out the cells.
e. Step5:
• Use cell padding
• specifyCellPad cellName 6
• This command pads the right of cellName by 6 sites. This can be used to provide
extra area around specific cells, such as level shifters, isolation cells, or the ones
with high pin counts such as AOI/OAI cells.

18. How does tool calculated congestion?

• Problem
TrialRoute reports the following congestion "Overflow" along with the
"Congestion distribution" values in the log file:

Phase 1l Overflow: 1.13% H + 3.59% V (0:00:12.7 9096.1M)

Congestion distribution:
Remain cntH cntV
-------------------------------------------------------
-5: 362 0.02% 3288 0.15%
-4: 841 0.04% 4188 0.19%
-3: 2302 0.10% 8662 0.39%
-2: 5568 0.25% 15919 0.71%
-1: 11114 0.49% 26896 1.20%
---------------------------------------------------------
0: 20747 0.92% 41752 1.86%
 However, if the Vertical over-congestion percentages as reported in the
"Congestion distribution" table are added up (that is, 1.2 + .71 + .39 + .19 + .15),
the value is 2.64. So why does TrialRoute report an overflow value of 3.59% in
the Vertical direction?

• Solution

TrialRoute computes the overflow value using the squared root weighted sum
method. Hence, for the example report shown in the Problem section, the
overflow in the Vertical direction is actually computed using:

1.2*1+0.71*sqrt(2)+0.39*sqrt(3)+0.19*sqrt(4)+0.15*sqrt(5) = 3.59

This method is used to distinguish the low overflow from the high overflow
GCells but assign the higher weight on the high overflow GCells.
 1. Inputs to run the block ?)
Ans. Netlist, libs, lef, sdc, captables, MMC file, QRCtechfile
2. Checks performed on inputs?

Ans.

Check Unique, check design –netlist, time design,

3. To whom we have to report the checks reports or faults?

Floor_Plan

1. Macro orientation?
2. On which layers pins are available?
3. Pins on track or not?
4. On what bases macro placement is done ?
5. Estimation of macro channels ?
6. How can we freeze the floorplan ?

Physical cells

1. Which type of cells were added and their names ? why ?

2. Tap cells name ? distance ? why ?

Power Grid generation

1. On which layers power stripes were added?

2. What type of vias were used on power grid generation?
3. Width, spacing and set (power grid spec) to set distance of power stripes ?
4. Where we got that power grid spec?

Placement & opt stage

1. Main intention of placement ?

2. What are the checks & things we have to see after placement ?
3. Tran limits ?
4. How many buffers were added after placement opt stage ?

CTS & opt stage

1. What are the things in spec file ?

2. Intention of CTS ?
3. Checks after CTS ?
 4. Buffers count after CTS?
5. Buffers count after CTS &OPT?

Route & Route opt stage

1. Intention of Routing ?
2. Checks after Routing ?
3. Buffers count after RouteOpt?

PV

1. Checks performed in pv

Setup equations for (r2r, i2r, r2o) :

Hold equations for (r2r,i2r,r20):

Possibilities of setup and hold violations :