Chip Design Overview

VLSI Design Flow

System Architecture

Architectural Design

Functional Design

Logic Design

Circuit Design

Physical Design

Fabrication

Packaging and Testing

 VLSI Design Process

System Specification – High level specification of the chip are laid down. What
market is this chip going to be geared towards? How fast will this chip be? What is it
estimated size?

Architecture Design – The Design specification is further refined by deciding on the

architectural aspect of the design. How much on chip memory is going to be needed.
Is this going to be a RISC or CISC design?

Behavioral/Functional Design – In this step the chip is broken down into units. The
high level functionality and interconnects between the units described. The units are
described based on the behavior, and the specific implementation is not of
importance at this point.

Logic Design – This step involves using a HDL (Hardware description Language) to
describe the control flow, word widths, register allocation, arithmetic operation, and
logic operation. This description uses RTL (Register Transfer Level) to describe the
flow of information using Boolean expression.

Circuit design – The logic design description is converted into a circuit

representation. A netlist is produced that contains the circuit elements and their
connectivity. A logic synthesis tool can automate the conversion of RTL into a netlist.

Physical design – The circuit design is converted into geometric shapes that
represent the circuit elements. The process of converting the circuit to geometric
shape is known as Layout.
 Types of Design

Full Custom - The layout of every transistor is optimized for functionality, speed
and area. This method very time consuming, but yields the best performance.
Some analog devices such as OpAmps and PLL are exclusively drawn in custom
layout. Custom layout is needed to ensure that these sensitive circuits will behave
in an expected manner

Standard Cell - In this method of design , a library of standard cell is used. Each
cell represents a function. By connecting these standard cell together, a
specific design can be obtained. Logic Synthesis uses this standard cell design
style. The RTL description of a design is fed into a logic synthesis tool. The tool
synthesis a circuit, and this circuit is mapped to standard cell. The output of a
synthesis tool is usually a netlist. The design is usually placed and routed through
some automation tool (APR).
 System Level Block Diagram

CPU CPU

400 MT/s =
3.2GB/s

DDR DIMM
DDR DIMM
200MHz DDR DDRDDRDIMMS
DIMM
(Registered Only)

Plumas MCH
HL 8 42.5 mm2
1012 OLGA
DDR DIMM
DDR DIMM
200MHz DDR DDRDDRDIMMS
DIMM
(Registered Only)
HL 16

HL 16
HL 16
 Typical Die Floor Plan

DDR PLL

DDR1

AGP

AGP PLL
Core Logic DDR2
HL

DPLL

DAC
FSB PLL

FSB CM0S

wireless
 Design Flow
Custom Functional
MAS
Ckt design MAS2 VHDL Full Chip
(ebb,io,lib) Sim
RTL
Design Synthesis Formal Gate Level
views
Verification Sim
Layout netlist
Verif. Perform. Performance
Place&Route Verification
Func.
Physical
Verif.
Layout
LO
Verification
Tapeout
 M A S E X A M P L E
M ic r o A r c h ite c tu r e S p e c
Signal Equation Comments
sig4 S[1:0] ? D : C : B : A 4:1 Mux example

M A S2VH D L
BEGIN
--4:1 Example:
CASE (S[1:0]) IS
WHEN “11” =>
sig4 <= D;
WHEN “10” =>
sig4 <= C;
WHEN “01” =>
sig4 <= B;
WHEN “00” =>
sig4 <= A;
WHEN OTHERS =>
sig4 <= ‘X’
END CASE;
 S y n th e s is E x a m p le
-V H D L C O D E

If (A = '1 ') t h e n
Y < = C a n d D ;
e ls if ( B = '1 ') t h e n
Y < = C o r D ;
e ls e
Y < = C ;
e n d if

S y n th e s is = T r a n s la tio n + O p tim iz a tio n

Synthesis Flow
C u s to m c e lls
C lo c k
VHDL (S y n o p s y s
d e fin itio n s
d e s c r ip tio n )

S ta n d a rd
c e lls
W ir e -lo a d
m o d e ls S ynopsys
s y n th e s is
C o n s tr a in ts
(D e s ig n
C o m p ile r )

D e la y s
(S D F )
N e tlis t

PV G LS
APR
(S ta tic (D y n a m ic
Layout
T im in g ) tim in g )
Automated Place and Route (APR)
F lo o r p la n N e tlis t T im in g
- p o w e r g r id c o n s tr a in ts
- I/O s h a p e s

P la c e m e n t S c a n c h a in
C lo c k
in fo r m a tio n
s tru c tu re s
and skew s
Scan
o r d e r in g
C lo c k tr e e
and
g e n e r a tio n
s titc h in g

R o u tin g
P o s t-la y o u t P a r a s itic
n e tlis t e x tr a c tio n

D e la y
S D F - c e ll a n d c a lc u la tio n
w ir e d e la y s
 Types of Netlist
Spice netlist - (Simulation Program for Integrated Circuits Emphasis) A general purpose analog circuit simulator develop
by Electronics Research Laboratory of the University of California.. A spice netlist is a structural representation of a circuit.
HERC netlist - Similar to a spice file. It also represents the structure of a circuit, but is intended for the Hercules
verification engine.
Verilog netlist - A verilog netlist is used to describe the connectivity at the cell level, but it also has the capability to
describe connectivity at the gate level. It doesn’t have the capability of specifying Z/L ratio of gates.
SPICE EXAMPLE
.SUBCKT M10BF00X10 A O
MG1.QNA N0 A VSS VSS N W=1.14 L=0.16
MG1.QPA N0 A VCC VCC P W=1.6 L=0.16
MG2.QNA O N0 VSS VSS N W=2.02 L=0.16
MG2.QPA O N0 VCC VCC P W=2.52 L=0.16
HERC EXAMPLE
{CELL M10BF00X10
{PORT A O}
{INST MG2.QPA=P
{PROP L=0.16 W=2.52}
{PIN O=DRN N0=GATE VCC=SRC VCC=BULK}}
{INST MG2.QNA=N VERILOG EXAMPLE
module M10BF00X10 ( A O ) ;
input A;
output O ;
wire N0 ;
nmos MG1.QNA (N0 VSS A) ;
nmos MG2.QNA (O VSS N0) ;
pmos MG1.QPA (N0 VCC A) ;
pmos MG2.QPA (O VCC N0 ;
 Full chip verification
A P R

V e r ilo g w it h b a c k
S E _ T O P .g d s a n n o t a t e d c lo c k
tre e
C e lls . s p ic e

IO _ R IN G .G D S

E m b e d d e d
c e lls .s p ic e
M e r g in g th e S p ic e N e t lis t
S ta n d a r d C e ll E m b e d d e d B lo c k
d a ta b a s e C o n v e r s io n
G D S G D S
(G D S G E N ) ( v e r ilo g 2 s p )

F u ll C h ip G D S F u ll C h ip S p ic e

H e r c n e t lis t
c o n v e r s io n
( N e t T r a n - N e t lis t
T r a n s la t o r )

F u ll C h ip H E R C

F u ll C h ip
V e r ific a tio n
Layout Verification
• ERC - Electrical Rules Checking
• look for opens and shorts in power supplies
• DRC - Design rule checking
• e.g. spacing, minimum sizes, overlaps
• LVS - Layout versus schematic
• presence and sizes of transistors, connectivity
• compares GDS layout database with (Spice) netlist
• TFC - Thin Film Cracking
• cannot have large metal wires at edge of die
• NAC - Node Antenna Check
• long wires can destroy transistors during manufacturing
 Density checks
• While etching (polishing), have to maintain a uniform density of
features (e.g. metal), otherwise will be etched unevenly
• limits for total min and max density
• transitions in density cannot be too abrupt
• dummification adds extra features in white space
• density estimates run before fracture
• CAMDEX
• tool that simulates polishing effect
• gives accurate numbers for each layer using post-fracture data
• gate to tapeout
Tapeout flow
A P R C u s to m
( S C TS )
d a ta b a s e c e lls S a n ta C la ra
T a p e o u t s e r v ic e s

M e rg e F ra c tu re

G D S II C A TS
d a ta b a s e v ie w
D a ta b a s e
C A M D E X
V e r ify

D u m m ify
M ask
m a k in g IM O
V e r ify (In te l M ask
O p e ra tio n s )
FAB S a n ta C la r a
D a ta r e le a s e R e tic le s e t
fo rm
(T a p e o u t)
Tapeout Flow -Details

Full chip .GDS file

Fracture

Using Cats View look

at individual layers

Poly Via Metal

Mask Making by
IMO

FAB
 V C C P V C C P

V S S V S S

V C C P D e - c o u p l in g C a p s V C C P
~ 2 5 0 u (~ 1 0 0 p F )

V S S V S S

S IG
S IG

E
B u f fe r
S ~ 6 6 0u S IG
D
S IG 17 0 0 u

S IG S IG

V S S V S S
5 6 1 .4 u
D e -c o u p lin g C a p s
~ 5 0 0 u (~ 1 9 0 p F )
S IG S IG

S IG S IG
R C O M P
B U F F E R

P L U M A S H L S P L IN E A N D B U M P P L U M A S H L S P L IN E A N D B
R O U T IN G R O U T IN G F O R R C O M P B U F F
Bumpout Example
 Ballout Example
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VC C _ VS S - VC C _ VS S -
AN DDR 5V
BA_ A0 BA_A1
DDR 5V
DQ_A01 DQ_A06
DDR 5V
DQ_A08 DQ_ A09
DDR 5V
DQ_A15 DQ_ A11
DDR 5V
DQ_A21 DQ_A18
DDR 5V 1_ 5 V
RS P # HA 3 3
FS B 1_ 5 V
HA 2 6
FS B
AN
VS S - CMDCL CMDCL VS S - VS S - DQS _A DQS _A VS S - VS S - DQS _A VS S - VS S - DQS _A DQS _A1 VS S - VS S - VS S - VS S - VCC_1_
AM DDR K_A1# K_A0# DDR
CS _A1# DQ_ A0 4
DDR 09 00 DDR
DQ_A03 DQ_A12
DDR 01
DQ_A14
DDR
DQ_A10 DQ_ A20
DDR 02 1 DDR
DQ_ A19
FS B
A P 1#
FS B
HA2 7 HA3 5
FS B
HA2 0
5V
AM
VS S - CMDCL CMDCL VS S - CMDCL CS _A0 VS S - VS S - VS S - DQS _A1 VS S - CKE_A1 CKE_A0 VS S - VS S - B ER R B IN IT VS S - VS S - VS S -
AL DDR K_A2# K_A1 DDR K_ A3# # DDR
DQ_A00 DQ_A05
DDR
DQ_A0 2 DQ_A07
DDR
DQ_ A13
0 DDR # # DDR
DQ_A16 DQ_A17
DDR
DQ_A2 2 DQ_ A23
# #
HA 3 1
FS B
HA3 4 HA 2 1
FS B
HA 2 2
FS B
AL
VCC_2_ CMDCL VS S - CMDCL CMDCL VS S - DQS _A1 VS S - VS S - VS S - VS S - VS S - VS S - VS S - VC C _ VS S - H A VR
AK 5V K_ A2 DDR K_ A0 K_A3 DDR
DQ_ A2 5
2 DDR
DQ_A31 WE_A#
DDR
CB_A5 CB_ A1
DDR
CB_A6 CB_A7
DDR
DQ_ A32 DQ_A37
DDR
DQ_A34 DQ_A3 9
DDR
AP 0 #
FS B
HA 3 2 HA3 0
1_ 5 V
HA 2 3 HA2 9
FS B EF 1
AK
VS S - VS S - MA_A0 VCC_2_ VCC_2_ VCC_2 _ CS _A3 VCC_2_ DQS _A1 VCC_2_ CS _A5 VCC_2_ DQS _A VCC_2 _ VCC_2_ VC C _ IER R VS S - VS S - VCC_1_
AJ DDR DDR 2
MA_A01
5V
DQ_A2 8 DQ_ A2 9
5V
DQ_A26 DQ_A27
5V #
CB_A4
5V 7
CB_A2
5V #
DQ_ A36
5V 04
DQ_A38
5V 5V 1_ 5 V # FS B
HA 13 HA2 4
FS B
HA2 5 HA 2 8
5V
AJ
MA_A0 MA_A0 MA_A0 VS S - MA_ A0 VS S - DQS _ A VS S - DRCOM CS _A2 VS S - DQS _A VS S - CS _A4 VS S - DQS _A1 VS S - CS _A7 VS S - H LO C VS S - VS S - HA DS
AH 6 4 3 DDR 0
DQ_A2 4
DDR 03
DQ_A30
DDR P _A # DDR
CB_ A0
08 DDR
CB_A3
# DDR
DQ_A33
3 DDR
DQ_A3 5
# FS B K#
H A 14
FS B
H A 17 H A 18
FS B
H A 19
TB 1#
AH
MA_A0 MA_A0 VS S - MA_A0 VS S - VS S - VS S - VS S - VS S - VS S - CS _A6 HTR D VS S - VC C _ VS S - HA DS
AG 7 8 DDR 5
MA_A10
DDR
DQ_ A4 5 DQ_A40
DDR
DQ_A42 DQ_A4 3
DDR
DQ_A48 DQ_ A53
DDR
DQ_A54 DQ_A50
DDR
DQ_ A60 DQ_A56
DDR
DQ_A62 DQ_A5 8
# Y# FS B
H A 10 HA 12
1_ 5 V
H A 15 H A 11
FS B TB 0 #
AG
DRCOM
VCC_2_ VS S - MA_A0 VS S - BYTEDQ RCVENI VS S - DQS _A1 DQS _A VS S - DRCOM VS S - DQS _A1 DQS _A VS S - CAS _ A VS S - DQS _A1 DQS _A VS S - VS S - C C VR DB S Y VS S - VS S - VS S -
AF 5V DDR 9
MA_A11
DDR S IN_A N_A# DDR 4 05 DDR P VOL_A
P VOH_
DDR 5 06 DDR # DDR 6
DQ_ A61
07 DDR DDR EF # FS B
HA 16 HA0 9
FS B
HA0 8 HA 0 6
FS B
AF
RCVEN A
A_S P A VCC_2_ VS S - VREF_A VREF_A VREF_ A VREF_A VREF_A RAS _A VREF_A VCC_2_ VS S - D R D Y H R EQ VS S - HR EQ H R EQ VS S - H A VR
AE RE2
OUT_A MA_A12
5V DDR 6
DQ_ A4 4 DQ_A41
5
DQ_A46 DQ_A4 7
4
DQ_A52 DQ_ A49
3
DQ_A55 DQ_A51
2 #
DQ_A57
1
DQ_A63 DQ_A5 9
5V FS B # 4# FS B 1# 0# FS B
HA 0 5
EF 0
AE
#
VCC_2_ VS S - VCC_2_ CS _B7 CS _B6 VS S - VCC_2_ VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_1_ VS S - HA D S VC C _ VS S - VCC_1_
AD 5V
DQ_ B19 DQ_B23
DDR 5V # # DDR 5V 5V DDR 5V DDR 5V DDR 5V DDR 5V DDR 5V DDR 5V DDR 5V
RS 2 #
FS B #
HA0 3
1_ 5 V
HA 0 4 HA0 7
FS B 5V
AD
VS S - VS S - VCC_2_ VS S - VS S - VS S - VS S - VS S - VS S - VS S - VS S - VCC_1_ VS S - HYR C B P RI VS S - B R EQ VS S - H R EQ H R EQ VS S -
AC DDR DDR
DQ_B22 DQ_B39
5V
DQ_B3 5 DQ_ B5 8
DDR
DQ_B59
DDR DDR DDR DDR DDR DDR DDR 5V FS B OMP # FS B 0#
BNR#
FS B 2# 3# FS B
AC
DQS _B1 VS S - VS S - DQS _ B VCC_2_ VS S - VCC_1_ HYS W H ITM VS S - VS S - HD S T
AB DQ_B18
1 DDR
DQ_B34 DQ_ B38
DDR
DQ_ B6 2
07
DQ_B63
5V
VS S
FS B 5V NG #
R S 1#
FS B
H IT# RS 0#
FS B
HD 5 3
BP 3
AB
DQS _B VS S - DQS _B DQS _B1 VS S - DQS _B1 VREF_B VS S - VCC_1_ VS S - D EF E VS S - VC C _ VS S - HD S T
AA DQ_B2 1
02
DQ_B17
DDR 04 3 DDR 6 1 DDR 5V FS B R# FS B
HD 5 8 HD6 1
1_ 5 V
HD 5 4 HD5 5
FS B BN3
AA
VCC_2_ VS S - VCC_2_ VS S - VCC_2_ VS S - VS S - VS S - VS S - VCC_1_ VS S - D IN V HD VR VS S - VCC_1_
Y 5V DDR
DQ_B16 DQ_B37
5V
DQ_B3 3 DQ_ B5 6
DDR
DQ_B57
5V
VS S vc c a
CORE
vc c a
CORE
vc c a
CORE
vc c a
FS B 5V
HD 6 0 HD 6 3
FS B 3# EF 3 FS B
HD5 1 HD 5 2
5V
Y
VS S - VS S - VS S - RAS _B VS S - VS S - VCC_1_ VS S - VCC_1_ VS S - VCC_1_ VS S - VCC_1_ VS S - VS S - VS S - VS S -
W DDR
DQ_ B20
DDR
DQ_B32 DQ_ B36
DDR
DQ_ B6 0 DQ_B61
# DDR CORE 2V CORE 2V CORE 2V CORE 5V FS B
HD 5 9 HD 5 7 HD 5 6
FS B
HD6 2 HD 4 8
FS B
HD 4 9
FS B
W
CKE_ B0 VS S - CS _ B5 CS _B4 VS S - CAS _ B VREF_B VCC_2_ VS S - VCC_1_ VS S - VCC_1_ VS S - VCC_2_ VS S - VCC_1_ VS S - VS S - VC C _ VS S - HD S T
V DQ_ B11 DQ_ B10
# DDR # # DDR # 2 5V
VS S vc c a
CORE 2V CORE 2V CORE 5V FS B 5V FS B FS B
HD 4 6 HD4 4
1_ 5 V
HD 5 0 DP 3 #
FS B BP 2
V
VS S - CKE_ B1 VCC_2_ VS S - VS S - VS S - VCC_1_ VS S - VCC_1_ VS S - VCC_1_ VCC_1_ VS S - HC LK VS S - VS S - HD VR VS S - D IN V HD S T
U DQ_B15
DDR #
CB_B7
5V
CB_B3 DQ_ B5 0
DDR
DQ_B51
DDR CORE 2V CORE 2V CORE 2V
VREFB6
5V FS B IN P FS B FS B
HD4 2
EF 2 FS B 2#
HD 3 8
BN2
U
VCC_2_ VS S - VS S - DQS _ B VCC_2_ VS S - VCC_1_ VS S - VCC_1_ VS S - VCC_1_ VS S - VCC_1_ HC LK VS S - VS S - VS S - VCC_1_
T 5V
DQ_ B14
DDR
CB_B6 CB_ B2
DDR
DQ_ B5 4
06
DQ_B55
5V
VS S vc c a
CORE 2V CORE 2V CORE 2V FS B 5V IN N FS B
HD 4 7
FS B
HD4 5 HD 4 3
FS B
HD 3 9
5V
T
VS S - DQS _B DQS _B1 VS S - DQS _B1 DQS _B VS S - DQS _B1 VREF_B VS S - VS S - VCC_1_ VS S - VCC_1_ VCC_1_ VCC_2_ VS S - VCC_1_ VS S - VS S - VS S - VC C _ VS S - VS S -
R DDR 01 0 DDR 7 08 DDR 5 3 DDR CORE 2V CORE 2V 2V 5V CORE 5V FS B FS B FS B
DP 2 # HD4 0
1_ 5 V
HD 4 1 HD3 5
FS B FS B
R
VS S - VCC_2_ VS S - VCC_2_ VS S - VCC_1_ VS S - VS S - VCC_1_ VS S - VCC_1_ C P U R VS S - VS S - HD S T
P DQ_B0 9
DDR
DQ_B13 CB_B1
5V
CB_B0 DQ_ B5 3
DDR
DQ_B49
5V
VS S vc c a
CORE 2V CORE CORE
VREFB6
2V FS B 5V S T#
HD 3 3
FS B
HD3 7 HD3 2
FS B
HD3 0 HD 2 4
BP1
P
DRCOM
VS S - VS S - VS S - VCC_1_ VS S - VS S - VS S - HD S T
N DQ_B0 8 DQ_ B12
DDR
CB_B5 CB_ B4
DDR
DQ_ B4 8 P VOH_ DQ_B52
DDR 5V FS B
HD 3 6 HD 3 4 H D 19
FS B
HD2 7 HD 2 5
FS B
D P 1#
BN1
N
B
VCC_2_ VS S - CS _ B3 CS _B2 VS S - DRCOM VREF_B VCC_2_ VS S - VCC_1_ VS S - VC C _ D IN V1 VS S - VC C _
M 5V
DQ_ B03 DQ_B07
DDR # # DDR P VOL_B 4 5V
VS S
FS B 5V
HD 3 1
FS B
HD 2 1 HD2 2
1_ 5 V #
HD2 8
FS B 1_ 5 V
M
VS S - VS S - VCC_2_ DRCOM VS S - VS S - VCC_1_ VCC_1_ VCC_1_ VCC_1_ VCC_1_ VCC_1_ VCC_1_ VS S - HXR C VS S - HD VR VS S - VS S -
L DDR DDR
DQ_B02 WE_B#
5V _B
DQ_ B4 3
DDR
DQ_B47
DDR 2V
VS S
2V
VS S
2V
VS S
2V
VS S
2V
VS S
2V
VS S
2V FS B OMP
H D 17
FS B
HD2 0
EF 1 FS B
HD2 6 HD 2 9
FS B
L
DQS _B VS S - VS S - DQS _ B VCC_2_ VCC_1_ VCC_1_ VCC_1_ VCC_1_ VCC_1_ VCC_1_ VS S - VCC_1_ HXS W VS S - VS S - HD S T
K DQ_B0 6
00 DDR
DQ_B31 DQ_ B27
DDR
DQ_ B4 2
05
DQ_B46
5V 2V
VS S
2V
VS S
2V
VS S
2V
VS S
2V
VS S
2V
VS S
HUB 2V NG
H D 16 H D 18
FS B
HD2 3 H D 14
FS B
H D 12
BP 0
K
DQS _B VS S - VS S - DQS _B1 VREF_B VS S - P RCOM VS S - P S TOP VS S - VCC_1_ P RCOM VS S - P RCOM VS S - P S WIN P S TOP VS S - VS S - VC C _ VS S - HD S T
J DQ_B0 1
09
DQ_B05
DDR
DQ_ B26 DQ_B3 0
DDR 4 5 DDR P _D
P REF_D
HUB _D
RQI_D
HUB 2V P _C HUB
RQI_C
P _B HUB G_B _B HUB FS B
H D 10 DP 0 #
1_ 5 V
H D 11 H D 15
FS B BN0
J
VCC_2_ VS S - DQS _B1 VCC_2_ DQS _B VS S - P WRGO P S WIN VS S - P S TRB VS S - P S WIN VS S - P S TOP VS S - VS S - VS S - VC C _ VS S - HD VR VS S - VC C _
H 5V DDR
DQ_B00
2 5V 03
DQ_ B4 0
DDR
DQ_B41
OD G_D HUB
RQM_D
_D0 HUB G_C
P REF_C
HUB
RQM_ C
_C HUB
P REF_B RQM_B
HUB
RQI_B
HUB 1_ 5 V FS B EF 0 FS B
HD0 9 H D 13
1_ 5 V
H
VS S - VS S - VS S - RCVENI VS S - VS S - VS S - VS S - VS S - VCC_1_ VS S - VS S - D IN V VS S -
G DDR
DQ_ B04
DDR
DQ_B25 DQ_ B29
DDR
DQ_ B4 5
N_B#
DQ_B44 RS TINB
HUB
P D_D00 P D_D03
HUB
P D_D06 P D_C01
HUB
P D_C03 P D_ C07
HUB
P D_B02 P D_B00
HUB
P D_ B07
2V HUB
GCLKIN
FS B 0#
HD 0 2
FS B
HD 0 5 VS S G
CS _B0 VS S - VS S - BYTDQ VREF_B TES TIN VS S - P S TRB VS S - VS S - VS S - P S TRB VS S - VS S - VS S - VS S - VC C _ VS S -
F BA_B1 CS _ B1#
# DDR
DQ_ B28 DQ_B2 4
DDR S IN_B# 6 B
P D_D0 2 P D_D04
HUB _D0 #
P D_D08
HUB
P D_C00 P D_C05
HUB
P D_C08 P D_B01
HUB
P D_B0 3
_B0 HUB HUB HUB HUB 1_ 5 V
HD 0 8 HD0 3
FS B
HD 0 6 F
VS S - CMDCL CMDCL VCC_2_ MA_B0 VS S - VS S - VCC_1_ VCC_1_ VCC_1_ P S TRB VCC_1_ VCC_1_ VCC_1_ P RCOM VS S -
E BA_B0
DDR K_B3 # K_ B3 5V 0
MA_B10
DDR DDR
S S I_S T P D_D0 1
2V
P D_D05 P D_ D07
2V
P D_C02 P D_C04
2V _C0#
P D_C06
2V
P D_B04 P D_B0 5
2V
P D_ B0 6 RQI_A
2V
RQM_A
P _A FS B
HD0 1 HD 0 0 HD 0 7 E
VCC_2_ CMDCL VS S - CMDCL VS S - MA_B0 VCC_2_ XORMO VS S - VS S - P ECC_ VS S - P S TRB VS S - P S TRB VS S - P S TRB VS S - P S TOP VS S - VS S - VC C _
D 5V K_B0# DDR K_ B0
MA_B01
DDR 5
MA_B11
5V DE HUB
P D_D10 P D_D11
HUB D1
P D_C09
HUB
P D_C13
_C0 HUB
P D_B10
_B1 HUB _B0 #
P D_ B0 8
HUB _A
P AR_ A
HUB
P REF_A
FS B
HD 0 4
1_ 5 V
D
VS S - CMDCL CMDCL VS S - MA_ B0 MA_B0 VS S - MA_B0 S MBUS P ECC_ VS S - VS S - P S TRB P S TRB VS S - VS S - VS S - VS S - VS S - VC C _ VS S -
C DDR K_ B1# K_B1 DDR 2 3 DDR 9
MA_ B12
2 D0
P D_D09
HUB
P D_ D12 P D_D15
HUB _C1# _C1 HUB
P D_C15 P D_B09
HUB
P D_B13 P D_ B14
HUB
P D_A2 P D_A3
HUB
P D_A5 P D_A7
HUB 1_ 5 V FS B
C
RCVEN
VS S - CMDCL CMDCL VS S - MA_B0 MA_B0 VS S - S MBUS VCC_1_ VS S - P S TRB VS S - P ECC_ VS S - P ECC_ VS S - P S TRB VS S - VS S - P S TRB P S TRB VS S - VCC_1_ VCC_1_
B DDR K_B2 # K_ B2 DDR 4 8 DDR
OUT_B
1 2V HUB _D1
P D_ D14
HUB C0
P D_C10
HUB
P D_ C14
C1 HUB _B1#
P D_B12
HUB
P D_ B15 P D_A1
HUB _A _A# HUB 2V 2V
B
#
VS S - VCC_2_ VS S - MA_B0 MA_B0 VCC_2_ B_S P A VCC_2_ VS S - VCC_1_ P S TRB VS S - VCC_1_ VS S - VCC_1_ P ECC_ VS S - VCC_1_ P ECC_ VS S - VCC_1_ VS S -
A DDR 5V DDR 6 7 5V RE2 5V HUB 2V _ D1#
P D_ D13
HUB 2V
P D_C11 P D_C12
HUB 2V B0
P D_B11
HUB 2V B1
P D_A0
HUB 2V
P D_A4 P D_A6
HUB
A
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
 FCBGA1 Stack-up(6 layer)

Die Layer
3F-SIG
3F Signal Signal/Shielding
2F Signal
2F Signal /vss Signal/Shielding
1F Signal
1F Vss Vss Vss
1B Vccrac Vcc2.5
1B Vcc2.5
2B 2B Vccraca/Vss Vss
Signal/Vss
3B
3B Land/Vss Land/Vcc25
Land/Vss
FCBGA Ball
 Definition
Hercules – Primary software package used for verification in the PDE group. We use this tool to perform
verification such as DRC (Design Rule Check), NAC (Nodal Area Check), LVS (Layout VS. Verification).

Dracula – another verification tool used here at Intel. Its uses are limited.

Stream outs – the process of converting any other format of graphical information into GDS format. The
GDS format is an industry standard file format for transferring/archiving graphical design data. The reason
it is call streaming out is because the GDS format is a collection of sequential records. In the earlier days
of computing, the reel tape was the primary storage device. Because of this data must have been
represented by a collection of record. These records ar e then organized in a strict manner and save on the
reel tape.

Stream In – the process of converting GDS into a CBDA format (Cadence Design Framework format).

Tapeout – The final phase in the PDE group in which the clean database is now ready to be sen t to the FAB
for mask generation. This term was used in the earlier days when the database was sent to the mask maker
on reels of magnetic tape.

Dummification – the process of adding small pieces of metal in the design in order to meet a certain
metalX/Area Ratio.

NAC (Nodal Area Check) – (In process) ESD protection. Basically the design is checked to see it there is a
violation in the metal/gate ratio.

C4_bumps- (C4) Controlled Collapse Chip Connectoin (Flip Chip).

Over-con – an APR(auto place & route) term used to indicated the relative routability of a design. The
term it outdate; today it is call over-cap;

Fracture – The process of converting a GDS database into the series of boxes which represent the aperture
setting that eventually create each mask used in the manufacture and fabrication of the IC

MOS – (Metal –Oxide – Silicon) sandwich that make up a transistor.

Fracture – The process of converting a GDS databse in to the series of boxes which represent the aperture
setting that eventually create each mask used in the manufacture/fabrication of the IC.
 Full Custom Design
Standard Cell Design
ROW FINISHING CELL (RFC)

IORING

CORE - core logic synthesis from VHDL

and laid out by automated tool

Embedded Blocks (EBB) - electrically critical/ laid out ny hand (PLL, SRAM, IO_BUFFERS)